efm32: registers for leds
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chrysn
parent
692817059c
commit
da4567a035
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@ -1,2 +1,3 @@
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- emu
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- cmu
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- lcd
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @file
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* @see EFM32TG_LCD
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*/
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/** Definitions for the LCD subsystem (Liquid Crystal Display driver).
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*
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* This corresponds to the description in d0034_efm32tg_reference_manual.pdf
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* section 29.
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*
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* @ingroup EFM32TG
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* @defgroup EFM32TG_LCD LCD (Liquid Crystal Display driver)
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* @{
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*/
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#ifndef LIBOPENCM3_EFM32_TINYGECKO_LCD_H
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#define LIBOPENCM3_EFM32_TINYGECKO_LCD_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/efm32/memorymap.h>
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/** Register definitions and register value definitions for the LCD subsystem
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*
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* @defgroup EFM32TG_LCD_regsandvals LCD registers and values
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* @{
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*/
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/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 29.4
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*
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* @defgroup EFM32TG_LCD_registers LCD registers
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* @{
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*/
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#define LCD_CTRL MMIO32(LCD_BASE + 0x000) /**< @see EFM32TG_LCD_CTRL_bits */
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#define LCD_DISPCTRL MMIO32(LCD_BASE + 0x004) /**< @see EFM32TG_LCD_DISPCTRL_bits */
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#define LCD_SEGEN MMIO32(LCD_BASE + 0x008)
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#define LCD_BACTRL MMIO32(LCD_BASE + 0x00c) /**< @see EFM32TG_LCD_BACTRL_bits */
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#define LCD_STATUS MMIO32(LCD_BASE + 0x010) /**< @see EFM32TG_LCD_STATUS_bits */
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#define LCD_AREGA MMIO32(LCD_BASE + 0x014)
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#define LCD_AREGB MMIO32(LCD_BASE + 0x018)
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#define LCD_IF MMIO32(LCD_BASE + 0x01c) /**< @see EFM32TG_LCD_I_bits */
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#define LCD_IFS MMIO32(LCD_BASE + 0x020) /**< @see EFM32TG_LCD_I_bits */
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#define LCD_IFC MMIO32(LCD_BASE + 0x024) /**< @see EFM32TG_LCD_I_bits */
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#define LCD_IEN MMIO32(LCD_BASE + 0x028) /**< @see EFM32TG_LCD_I_bits */
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#define LCD_SEGD0L MMIO32(LCD_BASE + 0x040) /**< @see EFM32TG_LCD_SEG_bits */
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#define LCD_SEGD1L MMIO32(LCD_BASE + 0x044) /**< @see EFM32TG_LCD_SEG_bits */
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#define LCD_SEGD2L MMIO32(LCD_BASE + 0x048) /**< @see EFM32TG_LCD_SEG_bits */
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#define LCD_SEGD3L MMIO32(LCD_BASE + 0x04c) /**< @see EFM32TG_LCD_SEG_bits */
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#define LCD_FREEZE MMIO32(LCD_BASE + 0x060) /**< @see EFM32TG_LCD_FREEZE_bits */
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#define LCD_SYNGBUSY MMIO32(LCD_BASE + 0x064) /**< @see EFM32TG_LCD_SYNGBUSY_bits */
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#define LCD_SEGD4L MMIO32(LCD_BASE + 0x0cc) /**< @see EFM32TG_LCD_SEG_bits */
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#define LCD_SEGD5L MMIO32(LCD_BASE + 0x0d0) /**< @see EFM32TG_LCD_SEG_bits */
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#define LCD_SEGD6L MMIO32(LCD_BASE + 0x0d4) /**< @see EFM32TG_LCD_SEG_bits */
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#define LCD_SEGD7L MMIO32(LCD_BASE + 0x0d8) /**< @see EFM32TG_LCD_SEG_bits */
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/** @} */
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/** Bit states for the LCD_CTRL register
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*
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* See d0034_efm32tg_reference_manual.pdf section 29.5.1 for definitions.
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*
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* @defgroup EFM32TG_LCD_CTRL_bits LCD CTRL bits
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* @{
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*/
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#define LCD_CTRL_DSC (1<<23)
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#define LCD_CTRL_UDCTRL_REGULAR (0<<1)
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#define LCD_CTRL_UDCTRL_FCEVENT (1<<1)
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#define LCD_CTRL_UDCTRL_FRAMESTART (2<<1)
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#define LCD_CTRL_UDCTRL_MASK (0x3<<1)
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#define LCD_CTRL_EN (1<<0)
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/** @} */
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/** Bit states for the LCD_DISPCTRL register
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*
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* See d0034_efm32tg_reference_manual.pdf section 29.5.2 for definitions.
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*
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* @defgroup EFM32TG_LCD_DISPCTRL_bits LCD DISPCTRL bits
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* @{
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*/
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#define LCD_DISPCTRL_VBLEV_LEVEL0 (0<<18)
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#define LCD_DISPCTRL_VBLEV_LEVEL1 (1<<18)
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#define LCD_DISPCTRL_VBLEV_LEVEL2 (2<<18)
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#define LCD_DISPCTRL_VBLEV_LEVEL3 (3<<18)
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#define LCD_DISPCTRL_VBLEV_LEVEL4 (4<<18)
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#define LCD_DISPCTRL_VBLEV_LEVEL5 (5<<18)
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#define LCD_DISPCTRL_VBLEV_LEVEL6 (6<<18)
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#define LCD_DISPCTRL_VBLEV_LEVEL7 (7<<18)
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#define LCD_DISPCTRL_VBLEV_MASK (0x7<<18)
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#define LCD_DISPCTRL_VLCDSEL_VDD (0<<16)
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#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (1<<16)
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#define LCD_DISPCTRL_VLCDSEL_MASK (0x1<<16)
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#define LCD_DISPCTRL_CONCONF_VLCD (0<<15)
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#define LCD_DISPCTRL_CONCONF_GND (1<<15)
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#define LCD_DISPCTRL_CONCONF_MASK (0x1<<15)
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/** By this parameter, the voltage V_LCD_OUT is interpolated linearly from
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* 0.5V_LCD to V_LCD.
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*/
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#define LCD_DISPCTRL_CONLEV_MASK (0x1f<<8)
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#define LCD_DISPCTRL_WAVE_LOWPOWER (0<<4)
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#define LCD_DISPCTRL_WAVE_NORMAL (1<<4)
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#define LCD_DISPCTRL_WAVE_MASK (0x1<<4)
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#define LCD_DISPCTRL_BIAS_STATIC (0<<2)
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#define LCD_DISPCTRL_BIAS_ONEHALF (1<<2)
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#define LCD_DISPCTRL_BIAS_ONETHIRD (2<<2)
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#define LCD_DISPCTRL_BIAS_ONEFOURTH (3<<2)
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#define LCD_DISPCTRL_BIAS_MASK (0x3<<2)
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/** These definitions munge the MUX and the MUXE fields, as they are described
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* in the documentation only together too.
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*/
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#define LCD_DISPCTRL_MUX_STATIC 0x00000000
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#define LCD_DISPCTRL_MUX_DUPLEX 0x00000001
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#define LCD_DISPCTRL_MUX_TRIPLEX 0x00000002
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#define LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003
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#define LCD_DISPCTRL_MUX_SEXTAPLEX 0x00400001
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#define LCD_DISPCTRL_MUX_OCTAPLEX 0x00400003
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#define LCD_DISPCTRL_MUX_MASK 0x00400003
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/** @} */
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/** Bit states for the LCD_BACTRL register
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*
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* See d0034_efm32tg_reference_manual.pdf section 29.5.4 for definitions.
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*
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* @defgroup EFM32TG_LCD_BACTRL_bits LCD BACTRL bits
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* @{
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*/
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#define LCD_BACTRL_FCTOP_MASK (0x3f<<18)
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#define LCD_BACTRL_FCPRESC_DIV1 (0<<16)
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#define LCD_BACTRL_FCPRESC_DIV2 (1<<16)
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#define LCD_BACTRL_FCPRESC_DIV4 (2<<16)
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#define LCD_BACTRL_FCPRESC_DIV8 (3<<16)
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#define LCD_BACTRL_FCPRESC_MASK (0x3<<16)
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#define LCD_BACTRL_FCEN (1<<8)
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#define LCD_BACTRL_ALGOSEL_AND (0<<7)
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#define LCD_BACTRL_ALGOSEL_OR (1<<7)
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#define LCD_BACTRL_ALGOSEL_MASK (0x1<<7)
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#define LCD_BACTRL_AREGBSC_NOSHIFT (0<<5)
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#define LCD_BACTRL_AREGBSC_SHIFTLEFT (1<<5)
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#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (2<<5)
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#define LCD_BACTRL_AREGBSC_MASK (0x3<<5)
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#define LCD_BACTRL_AREGASC_NOSHIFT (0<<3)
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#define LCD_BACTRL_AREGASC_SHIFTLEFT (1<<3)
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#define LCD_BACTRL_AREGASC_SHIFTRIGHT (2<<3)
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#define LCD_BACTRL_AREGASC_MASK (0x3<<3)
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#define LCD_BACTRL_AEN (1<<2)
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#define LCD_BACTRL_BLANK (1<<1)
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#define LCD_BACTRL_BLINKEN (1<<0)
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/** @} */
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/** Bit states for the LCD_STATUS register
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*
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* See d0034_efm32tg_reference_manual.pdf section 29.5.5 for definitions.
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*
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* @defgroup EFM32TG_LCD_STATUS_bits LCD STATUS bits
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* @{
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*/
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#define LCD_STATUS_BLINK (1<<8)
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#define LCD_STATUS_ASTATE_MASK (0xf<<0)
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/** @} */
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/** Bit states for the LCD_FREEZE register
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*
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* See d0034_efm32tg_reference_manual.pdf section 29.5.16 for definitions.
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*
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* @defgroup EFM32TG_LCD_FREEZE_bits LCD FREEZE bits
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* @{
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*/
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#define LCD_FREEZE_REGFREEZE_UPDATE (0<<0)
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#define LCD_FREEZE_REGFREEZE_FREEZE (1<<0)
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#define LCD_FREEZE_REGFREEZE_MASK (0x1<<0)
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/** @} */
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/** Bit states for the LCD_SYNGBUSY register
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*
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* See d0034_efm32tg_reference_manual.pdf section 29.5.17 for definitions.
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*
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* @defgroup EFM32TG_LCD_SYNGBUSY_bits LCD SYNGBUSY bits
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* @{
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*/
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#define LCD_SYNGBUSY_SEGD7L (1<<19)
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#define LCD_SYNGBUSY_SEGD6L (1<<18)
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#define LCD_SYNGBUSY_SEGD5L (1<<17)
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#define LCD_SYNGBUSY_SEGD4L (1<<16)
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#define LCD_SYNGBUSY_SEGD3L (1<<7)
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#define LCD_SYNGBUSY_SEGD2L (1<<6)
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#define LCD_SYNGBUSY_SEGD1L (1<<5)
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#define LCD_SYNGBUSY_SEGD0L (1<<4)
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#define LCD_SYNGBUSY_AREGB (1<<3)
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#define LCD_SYNGBUSY_AREGA (1<<2)
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#define LCD_SYNGBUSY_BACTRL (1<<1)
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#define LCD_SYNGBUSY_CTRL (1<<0)
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/** @} */
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/** Bit states for the LCD "I" group of registers (IF, IFS, IFC, IEN)
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*
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* These registers use this:
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*
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* <ul>
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*
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* <li>The LCD_IF register; see d0034_efm32tg_reference_manual.pdf section
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* 29.5.8 for definitions.</li>
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*
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* <li>The LCD_IFS register; see d0034_efm32tg_reference_manual.pdf section
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* 29.5.9 for definitions.</li>
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*
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* <li>The LCD_IFC register; see d0034_efm32tg_reference_manual.pdf section
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* 29.5.10 for definitions.</li>
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*
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* <li>The LCD_IEN register; see d0034_efm32tg_reference_manual.pdf section
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* 29.5.11 for definitions.</li>
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*
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* </ul>
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*
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* @defgroup EFM32TG_LCD_I_bits LCD I bits group
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* @{
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*/
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#define LCD_I_FC (1<<0)
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/** @} */
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/** Bit states for the LCD "SEG" group of registers (SEGD0L, SEGD1L, SEGD2L,
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* SEGD3L, SEGD4L, SEGD5L, SEGD6L, SEGD7L)
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*
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* These values are used by the SEGDxL registers, as defined in
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* d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21.
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*
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* @defgroup EFM32TG_LCD_SEG_bits LCD SEG bits group
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* @{
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*/
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#define LCD_SEG_23 (1<<23)
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#define LCD_SEG_22 (1<<22)
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#define LCD_SEG_21 (1<<21)
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#define LCD_SEG_20 (1<<20)
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#define LCD_SEG_19 (1<<19)
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#define LCD_SEG_18 (1<<18)
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#define LCD_SEG_17 (1<<17)
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#define LCD_SEG_16 (1<<16)
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#define LCD_SEG_15 (1<<15)
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#define LCD_SEG_14 (1<<14)
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#define LCD_SEG_13 (1<<13)
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#define LCD_SEG_12 (1<<12)
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#define LCD_SEG_11 (1<<11)
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#define LCD_SEG_10 (1<<10)
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#define LCD_SEG_9 (1<<9)
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#define LCD_SEG_8 (1<<8)
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#define LCD_SEG_7 (1<<7)
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#define LCD_SEG_6 (1<<6)
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#define LCD_SEG_5 (1<<5)
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#define LCD_SEG_4 (1<<4)
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#define LCD_SEG_3 (1<<3)
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#define LCD_SEG_2 (1<<2)
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#define LCD_SEG_1 (1<<1)
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#define LCD_SEG_0 (1<<0)
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/** @} */
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/** @} */
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/** @} */
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#endif
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@ -0,0 +1,238 @@
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copyright: "2012 chrysn <chrysn@fsfe.org>"
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license: lgpl-3+
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ingroup: EFM32TG
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shortdocname: EFM32TG_LCD
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shortname: LCD
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longname: Liquid Crystal Display driver
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baseref: d0034_efm32tg_reference_manual.pdf section 29
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registers_baserefext: ".4"
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templateregs:
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- name: I
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comment: Bits for the various LCD interrupt registers
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fields:
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- {name: FC, shift: 0}
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- name: SEG
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comment: Bits for the individual SEG pins
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override_backref: These values are used by the SEGDxL registers, as defined in d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21.
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fields:
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- {name: 23, shift: 23}
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- {name: 22, shift: 22}
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- {name: 21, shift: 21}
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- {name: 20, shift: 20}
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- {name: 19, shift: 19}
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- {name: 18, shift: 18}
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- {name: 17, shift: 17}
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- {name: 16, shift: 16}
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- {name: 15, shift: 15}
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- {name: 14, shift: 14}
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- {name: 13, shift: 13}
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- {name: 12, shift: 12}
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- {name: 11, shift: 11}
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- {name: 10, shift: 10}
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- {name: 9, shift: 9}
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- {name: 8, shift: 8}
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- {name: 7, shift: 7}
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- {name: 6, shift: 6}
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- {name: 5, shift: 5}
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- {name: 4, shift: 4}
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- {name: 3, shift: 3}
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- {name: 2, shift: 2}
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- {name: 1, shift: 1}
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- {name: 0, shift: 0}
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registers:
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- name: CTRL
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offset: 0x000
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definition_baserefext: .5.1
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fields:
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- name: DSC
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shift: 23
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- name: UDCTRL
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shift: 1
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length: 2
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values:
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- {name: REGULAR, value: 0}
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- {name: FCEVENT, value: 1}
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- {name: FRAMESTART, value: 2}
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- name: EN
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shift: 0
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- name: DISPCTRL
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offset: 0x004
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definition_baserefext: .5.2
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fields:
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# MUXE left out and defined manually at the end
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- name: VBLEV
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shift: 18
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length: 3
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values:
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- {name: LEVEL0, value: 0}
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- {name: LEVEL1, value: 1}
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- {name: LEVEL2, value: 2}
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- {name: LEVEL3, value: 3}
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- {name: LEVEL4, value: 4}
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- {name: LEVEL5, value: 5}
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- {name: LEVEL6, value: 6}
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- {name: LEVEL7, value: 7}
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- name: VLCDSEL
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shift: 16
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values:
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- {name: VDD, value: 0}
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- {name: VEXTBOOST, value: 1}
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- name: CONCONF
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shift: 15
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values:
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- {value: 0, name: VLCD}
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- {value: 1, name: GND}
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- name: CONLEV
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shift: 8
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length: 5
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type: uint
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doc: "By this parameter, the voltage V_LCD_OUT is interpolated linearly from 0.5V_LCD to V_LCD."
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- name: WAVE
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shift: 4
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values:
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- {value: 0, name: LOWPOWER}
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- {value: 1, name: NORMAL}
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- name: BIAS
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shift: 2
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length: 2
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values:
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- {value: 0, name: STATIC}
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- {value: 1, name: ONEHALF}
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- {value: 2, name: ONETHIRD}
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- {value: 3, name: ONEFOURTH}
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- name: MUX
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mask: "0x00400003"
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values:
|
||||
- {value: "0x00000000", name: STATIC}
|
||||
- {value: "0x00000001", name: DUPLEX}
|
||||
- {value: "0x00000002", name: TRIPLEX}
|
||||
- {value: "0x00000003", name: QUADRUPLEX}
|
||||
- {value: "0x00400001", name: SEXTAPLEX}
|
||||
- {value: "0x00400003", name: OCTAPLEX}
|
||||
doc: These definitions munge the MUX and the MUXE fields, as they are described in the documentation only together too.
|
||||
- name: SEGEN
|
||||
offset: 0x008
|
||||
definition_baserefext: .5.3
|
||||
# FIXME how do we reperesent this best?
|
||||
- name: BACTRL
|
||||
offset: 0x00c
|
||||
definition_baserefext: .5.4
|
||||
fields:
|
||||
- name: FCTOP
|
||||
shift: 18
|
||||
length: 6
|
||||
type: uint
|
||||
- name: FCPRESC
|
||||
shift: 16
|
||||
length: 2
|
||||
values:
|
||||
- {value: 0, name: DIV1}
|
||||
- {value: 1, name: DIV2}
|
||||
- {value: 2, name: DIV4}
|
||||
- {value: 3, name: DIV8}
|
||||
- name: FCEN
|
||||
shift: 8
|
||||
- name: ALGOSEL
|
||||
shift: 7
|
||||
values:
|
||||
- {value: 0, name: AND}
|
||||
- {value: 1, name: OR}
|
||||
- name: AREGBSC
|
||||
shift: 5
|
||||
length: 2
|
||||
values: &BACTRL_AREGBSC
|
||||
- {value: 0, name: NOSHIFT}
|
||||
- {value: 1, name: SHIFTLEFT}
|
||||
- {value: 2, name: SHIFTRIGHT}
|
||||
- name: AREGASC
|
||||
shift: 3
|
||||
length: 2
|
||||
values: *BACTRL_AREGBSC
|
||||
- name: AEN
|
||||
shift: 2
|
||||
- name: BLANK
|
||||
shift: 1
|
||||
- name: BLINKEN
|
||||
shift: 0
|
||||
- name: STATUS
|
||||
offset: 0x010
|
||||
definition_baserefext: .5.5
|
||||
fields:
|
||||
- name: BLINK
|
||||
shift: 8
|
||||
- name: ASTATE
|
||||
shift: 0
|
||||
length: 4
|
||||
type: uint
|
||||
- name: AREGA
|
||||
offset: 0x014
|
||||
# FIXME: how do we represent this in the header?
|
||||
- name: AREGB
|
||||
offset: 0x018
|
||||
# FIXME: how do we represent this in the header?
|
||||
- name: IF
|
||||
offset: 0x01c
|
||||
definition_baserefext: .5.8
|
||||
fields: I
|
||||
- name: IFS
|
||||
offset: 0x020
|
||||
definition_baserefext: .5.9
|
||||
fields: I
|
||||
- name: IFC
|
||||
offset: 0x024
|
||||
definition_baserefext: .5.10
|
||||
fields: I
|
||||
- name: IEN
|
||||
offset: 0x028
|
||||
definition_baserefext: .5.11
|
||||
fields: I
|
||||
- name: SEGD0L
|
||||
offset: 0x040
|
||||
fields: SEG
|
||||
- name: SEGD1L
|
||||
offset: 0x044
|
||||
fields: SEG
|
||||
- name: SEGD2L
|
||||
offset: 0x048
|
||||
fields: SEG
|
||||
- name: SEGD3L
|
||||
offset: 0x04c
|
||||
fields: SEG
|
||||
- name: FREEZE
|
||||
offset: 0x060
|
||||
definition_baserefext: .5.16
|
||||
fields:
|
||||
- name: REGFREEZE
|
||||
shift: 0
|
||||
values:
|
||||
- {value: 0, name: UPDATE}
|
||||
- {value: 1, name: FREEZE}
|
||||
# FIXME: this seems to be a typical FREEZE register
|
||||
- name: SYNGBUSY
|
||||
offset: 0x064
|
||||
definition_baserefext: .5.17
|
||||
fields:
|
||||
- {name: SEGD7L, shift: 19}
|
||||
- {name: SEGD6L, shift: 18}
|
||||
- {name: SEGD5L, shift: 17}
|
||||
- {name: SEGD4L, shift: 16}
|
||||
- {name: SEGD3L, shift: 7}
|
||||
- {name: SEGD2L, shift: 6}
|
||||
- {name: SEGD1L, shift: 5}
|
||||
- {name: SEGD0L, shift: 4}
|
||||
- {name: AREGB, shift: 3}
|
||||
- {name: AREGA, shift: 2}
|
||||
- {name: BACTRL, shift: 1}
|
||||
- {name: CTRL, shift: 0}
|
||||
- name: SEGD4L
|
||||
offset: 0x0CC
|
||||
fields: SEG
|
||||
- name: SEGD5L
|
||||
offset: 0x0D0
|
||||
fields: SEG
|
||||
- name: SEGD6L
|
||||
offset: 0x0D4
|
||||
fields: SEG
|
||||
- name: SEGD7L
|
||||
offset: 0x0D8
|
||||
fields: SEG
|
||||
Loading…
Reference in New Issue