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lib: More small fixes.

This commit is contained in:
Uwe Hermann 2011-11-16 21:53:27 +01:00
parent 0d25aa3fcd
commit d97c937b8e
5 changed files with 10 additions and 13 deletions
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7
lib/lm3s/vector.c
View File

@ -19,7 +19,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by linker script */
/* Symbols exported by the linker script(s): */
extern unsigned _etext, _data, _edata, _ebss, _stack;
void main(void);
@ -41,7 +41,7 @@ void WEAK sys_tick_handler(void);
__attribute__ ((section(".vectors")))
void (*const vector_table[]) (void) = {
(void*)&_stack,
(void *)&_stack,
reset_handler,
nmi_handler,
hard_fault_handler,
@ -61,7 +61,7 @@ void (*const vector_table[]) (void) = {
void reset_handler(void)
{
volatile unsigned *src, *dest;
asm("MSR msp, %0" : : "r"(&_stack));
__asm__("MSR msp, %0" : : "r"(&_stack));
for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
@ -93,4 +93,3 @@ void null_handler(void)
#pragma weak pend_sv_handler = null_handler
#pragma weak sys_tick_handler = null_handler
/* TODO: Interrupt handler weak aliases */

2
lib/stm32/f1/rcc.c
View File

@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/flash.h>
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 8000000;
u32 rcc_ppre2_frequency = 8000000;

2
lib/stm32/f1/vector.c
View File

@ -19,7 +19,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by linker script */
/* Symbols exported by the linker script(s). */
extern unsigned _etext, _data, _edata, _ebss, _stack;
void main(void);

2
lib/stm32/f2/vector.c
View File

@ -122,7 +122,7 @@ void WEAK hash_rng_isr(void);
__attribute__ ((section(".vectors")))
void (*const vector_table[]) (void) = {
(void*)&_stack,
(void *)&_stack,
reset_handler,
nmi_handler,
hard_fault_handler,

10
lib/stm32/f4/rcc.c
View File

@ -402,16 +402,14 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_set_main_pll_hse(clock->pllm,
clock->plln,
clock->pllp,
clock->pllq);
rcc_set_main_pll_hse(clock->pllm, clock->plln,
clock->pllp, clock->pllq);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Configure flash settings */
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Select PLL as SYSCLK source. */
@ -420,7 +418,7 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
/* Set the peripheral clock frequencies used */
/* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency;
}