Added STM32 DBGMCU register definitions.
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_STM32_DBGMCU_H
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#define LIBOPENCM3_STM32_DBGMCU_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- DBGMCU registers ---------------------------------------------------- */
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#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00)
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#define DBGMCU_CR MMIO32(DBGCMU_BASE + 0x04)
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/* DBGMCU_CR bits */
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#define DBGMCU_CR_SLEEP 0x00000001
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#define DBGMCU_CR_STOP 0x00000002
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#define DBGMCU_CR_STANDBY 0x00000004
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#define DBGMCU_CR_TRACE_IOEN 0x00000020
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#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0
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#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000
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#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040
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#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080
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#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0
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#define DBGMCU_CR_IWDG_STOP 0x00000100
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#define DBGMCU_CR_WWDG_STOP 0x00000200
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#define DBGMCU_CR_TIM1_STOP 0x00000400
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#define DBGMCU_CR_TIM2_STOP 0x00000800
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#define DBGMCU_CR_TIM3_STOP 0x00001000
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#define DBGMCU_CR_TIM4_STOP 0x00002000
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#define DBGMCU_CR_CAN1_STOP 0x00004000
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#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000
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#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000
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#define DBGMCU_CR_TIM8_STOP 0x00020000
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#define DBGMCU_CR_TIM5_STOP 0x00040000
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#define DBGMCU_CR_TIM6_STOP 0x00080000
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#define DBGMCU_CR_TIM7_STOP 0x00100000
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#define DBGMCU_CR_CAN2_STOP 0x00200000
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/* DBGMCU_IDCODE bits */
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#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff
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#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000
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#endif
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