diff --git a/include/libopencm3/gd32/f1x0/rcc.h b/include/libopencm3/gd32/f1x0/rcc.h index 63778317..935d9e18 100644 --- a/include/libopencm3/gd32/f1x0/rcc.h +++ b/include/libopencm3/gd32/f1x0/rcc.h @@ -174,44 +174,39 @@ /** @defgroup rcc_cfgr_adcpre ADCPRE: ADC prescaler * @{ */ -#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 -#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 -#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 -#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 +#define RCC_CFGR_ADCPRE_DIV2 0x0 +#define RCC_CFGR_ADCPRE_DIV4 0x1 +#define RCC_CFGR_ADCPRE_DIV6 0x2 +#define RCC_CFGR_ADCPRE_DIV8 0x3 /**@}*/ -/** @defgroup rcc_cfgr_apb2pre PPRE2: APB high-speed prescaler (APB2) +#define RCC_CFGR_PPRE2_SHIFT 11 +#define RCC_CFGR_PPRE2_MASK 0x7 +#define RCC_CFGR_PPRE1_SHIFT 8 +#define RCC_CFGR_PPRE1_MASK 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling * @{ */ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 -/**@}*/ - -/** @defgroup rcc_cfgr_apb1pre PPRE1: APB low-speed prescaler (APB1) - * @{ - */ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 /**@}*/ /** @defgroup rcc_cfgr_ahbpre HPRE: AHB prescaler * @{ */ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 0x8 +#define RCC_CFGR_HPRE_DIV4 0x9 +#define RCC_CFGR_HPRE_DIV8 0xa +#define RCC_CFGR_HPRE_DIV16 0xb +#define RCC_CFGR_HPRE_DIV64 0xc +#define RCC_CFGR_HPRE_DIV128 0xd +#define RCC_CFGR_HPRE_DIV256 0xe +#define RCC_CFGR_HPRE_DIV512 0xf /**@}*/ /* SWS: System clock switch status */ @@ -227,6 +222,39 @@ #define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 /**@}*/ +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 +#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 +#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 +#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 + +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 + +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 + +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf +/**@}*/ + /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h index 3b066f1a..c3efced0 100644 --- a/include/libopencm3/stm32/f1/rcc.h +++ b/include/libopencm3/stm32/f1/rcc.h @@ -186,34 +186,25 @@ @ingroup STM32F1xx_rcc_defines @{*/ -#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 -#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 -#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 -#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 +#define RCC_CFGR_ADCPRE_DIV2 0x0 +#define RCC_CFGR_ADCPRE_DIV4 0x1 +#define RCC_CFGR_ADCPRE_DIV6 0x2 +#define RCC_CFGR_ADCPRE_DIV8 0x3 /**@}*/ -/* PPRE2: APB high-speed prescaler (APB2) */ -/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 -/**@}*/ - -/* PPRE1: APB low-speed prescaler (APB1) */ -/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 +#define RCC_CFGR_PPRE2_SHIFT 11 +#define RCC_CFGR_PPRE2_MASK 0x7 +#define RCC_CFGR_PPRE1_SHIFT 8 +#define RCC_CFGR_PPRE1_MASK 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling + * @{ + */ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 /**@}*/ /* HPRE: AHB prescaler */ @@ -221,15 +212,15 @@ @ingroup STM32F1xx_rcc_defines @{*/ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 0x8 +#define RCC_CFGR_HPRE_DIV4 0x9 +#define RCC_CFGR_HPRE_DIV8 0xa +#define RCC_CFGR_HPRE_DIV16 0xb +#define RCC_CFGR_HPRE_DIV64 0xc +#define RCC_CFGR_HPRE_DIV128 0xd +#define RCC_CFGR_HPRE_DIV256 0xe +#define RCC_CFGR_HPRE_DIV512 0xf /**@}*/ /* SWS: System clock switch status */ @@ -247,6 +238,40 @@ #define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 /**@}*/ +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 +#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 +#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 +#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 + +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 + +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 + +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf + +/** @}*/ + /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h index 923ac81e..1831feb0 100644 --- a/include/libopencm3/stm32/f2/rcc.h +++ b/include/libopencm3/stm32/f2/rcc.h @@ -142,26 +142,35 @@ #define RCC_CFGR_RTCPRE_SHIFT 16 #define RCC_CFGR_RTCPRE_MASK 0x1f -/* PPRE1/2: APB high-speed prescalers */ #define RCC_CFGR_PPRE2_SHIFT 13 +#define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE1_SHIFT 10 -#define RCC_CFGR_PPRE_DIV_NONE 0x0 -#define RCC_CFGR_PPRE_DIV_2 0x4 -#define RCC_CFGR_PPRE_DIV_4 0x5 -#define RCC_CFGR_PPRE_DIV_8 0x6 -#define RCC_CFGR_PPRE_DIV_16 0x7 +#define RCC_CFGR_PPRE1_MASK 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling + * @{ + */ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 +/**@}*/ -/* HPRE: AHB high-speed prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) -#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) -#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) -#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) -#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) -#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) -#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) -#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) +#define RCC_CFGR_HPRE_MASK 0xf +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale factors +@{*/ +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV512 (0x8 + 7) +/**@}*/ /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 @@ -176,6 +185,28 @@ #define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_PLL 0x2 +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) +/**@}*/ + /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h index c83b2ac6..fd6fe286 100644 --- a/include/libopencm3/stm32/f3/rcc.h +++ b/include/libopencm3/stm32/f3/rcc.h @@ -124,40 +124,35 @@ #define RCC_CFGR_PLLMUL_MUL15 0xD #define RCC_CFGR_PLLMUL_MUL16 0xE -/* PPRE2: APB high-speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_SHIFT 11 #define RCC_CFGR_PPRE2_MASK 0x7 -/* 0XX: HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV_NONE 0x0 - -#define RCC_CFGR_PPRE2_DIV_2 0x4 -#define RCC_CFGR_PPRE2_DIV_4 0x5 -#define RCC_CFGR_PPRE2_DIV_8 0x6 -#define RCC_CFGR_PPRE2_DIV_16 0x7 - -/* PPRE1:APB Low-speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_SHIFT 8 #define RCC_CFGR_PPRE1_MASK 0x7 -/* 0XX: HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV_NONE 0x0 -#define RCC_CFGR_PPRE1_DIV_2 0x4 -#define RCC_CFGR_PPRE1_DIV_4 0x5 -#define RCC_CFGR_PPRE1_DIV_8 0x6 -#define RCC_CFGR_PPRE1_DIV_16 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling + * @{ + */ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 +/**@}*/ -/* HPRE: HLCK prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_MASK 0xf -/* 0XXX: SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 0x8 -#define RCC_CFGR_HPRE_DIV_4 0x9 -#define RCC_CFGR_HPRE_DIV_8 0xA -#define RCC_CFGR_HPRE_DIV_16 0xB -#define RCC_CFGR_HPRE_DIV_64 0xC -#define RCC_CFGR_HPRE_DIV_128 0xD -#define RCC_CFGR_HPRE_DIV_256 0xE -#define RCC_CFGR_HPRE_DIV_512 0xF +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale factors +@{*/ +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 0x8 +#define RCC_CFGR_HPRE_DIV4 0x9 +#define RCC_CFGR_HPRE_DIV8 0xA +#define RCC_CFGR_HPRE_DIV16 0xB +#define RCC_CFGR_HPRE_DIV64 0xC +#define RCC_CFGR_HPRE_DIV128 0xD +#define RCC_CFGR_HPRE_DIV256 0xE +#define RCC_CFGR_HPRE_DIV512 0xF +/**@}*/ /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 @@ -172,6 +167,34 @@ #define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_PLL 0x2 +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_PPRE2_DIV_NONE 0x0 +#define RCC_CFGR_PPRE2_DIV_2 0x4 +#define RCC_CFGR_PPRE2_DIV_4 0x5 +#define RCC_CFGR_PPRE2_DIV_8 0x6 +#define RCC_CFGR_PPRE2_DIV_16 0x7 + +#define RCC_CFGR_PPRE1_DIV_NONE 0x0 +#define RCC_CFGR_PPRE1_DIV_2 0x4 +#define RCC_CFGR_PPRE1_DIV_4 0x5 +#define RCC_CFGR_PPRE1_DIV_8 0x6 +#define RCC_CFGR_PPRE1_DIV_16 0x7 + +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 0x8 +#define RCC_CFGR_HPRE_DIV_4 0x9 +#define RCC_CFGR_HPRE_DIV_8 0xA +#define RCC_CFGR_HPRE_DIV_16 0xB +#define RCC_CFGR_HPRE_DIV_64 0xC +#define RCC_CFGR_HPRE_DIV_128 0xD +#define RCC_CFGR_HPRE_DIV_256 0xE +#define RCC_CFGR_HPRE_DIV_512 0xF +/**@}*/ + /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index 8e39f064..e957b06c 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -206,29 +206,35 @@ #define RCC_CFGR_RTCPRE_SHIFT 16 #define RCC_CFGR_RTCPRE_MASK 0x1f -/* PPRE1/2: APB high-speed prescalers */ #define RCC_CFGR_PPRE2_SHIFT 13 #define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE_DIV_NONE 0x0 -#define RCC_CFGR_PPRE_DIV_2 0x4 -#define RCC_CFGR_PPRE_DIV_4 0x5 -#define RCC_CFGR_PPRE_DIV_8 0x6 -#define RCC_CFGR_PPRE_DIV_16 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling + * @{ + */ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 +/**@}*/ -/* HPRE: AHB high-speed prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) -#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) -#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) -#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) -#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) -#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) -#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) -#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale factors +@{*/ +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV512 (0x8 + 7) +/**@}*/ /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 @@ -244,6 +250,28 @@ #define RCC_CFGR_SW_PLL 0x2 /**@}*/ +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) +/**@}*/ + /** @defgroup rcc_cir_values RCC_CIR values * @ingroup rcc_registers * @brief Clock Interrupt register values diff --git a/include/libopencm3/stm32/f7/rcc.h b/include/libopencm3/stm32/f7/rcc.h index 20ed3a5d..bace1c3a 100644 --- a/include/libopencm3/stm32/f7/rcc.h +++ b/include/libopencm3/stm32/f7/rcc.h @@ -137,29 +137,35 @@ #define RCC_CFGR_RTCPRE_SHIFT 16 #define RCC_CFGR_RTCPRE_MASK 0x1f -/* PPRE1/2: APB high-speed prescalers */ #define RCC_CFGR_PPRE2_SHIFT 13 #define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE_DIV_NONE 0x0 -#define RCC_CFGR_PPRE_DIV_2 0x4 -#define RCC_CFGR_PPRE_DIV_4 0x5 -#define RCC_CFGR_PPRE_DIV_8 0x6 -#define RCC_CFGR_PPRE_DIV_16 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling + * @{ + */ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 +/**@}*/ -/* HPRE: AHB high-speed prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) -#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) -#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) -#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) -#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) -#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) -#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) -#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale factors +@{*/ +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV512 (0x8 + 7) +/**@}*/ /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 @@ -175,6 +181,28 @@ #define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_PLL 0x2 +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) +/**@}*/ + /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index 59194425..287f6b99 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -174,29 +174,20 @@ #define RCC_CFGR_STOPWUCK_MSI (0<<15) #define RCC_CFGR_STOPWUCK_HSI16 (1<<15) -/* PPRE2: APB high-speed prescaler (APB2) */ -/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors -@{*/ -#define RCC_CFGR_PPRE2_NODIV 0x0 -#define RCC_CFGR_PPRE2_DIV2 0x4 -#define RCC_CFGR_PPRE2_DIV4 0x5 -#define RCC_CFGR_PPRE2_DIV8 0x6 -#define RCC_CFGR_PPRE2_DIV16 0x7 +#define RCC_CFGR_PPRE2_SHIFT 11 +#define RCC_CFGR_PPRE2_MASK 0x7 +#define RCC_CFGR_PPRE1_SHIFT 8 +#define RCC_CFGR_PPRE1_MASK 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling + * @{ + */ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 /**@}*/ -#define RCC_CFGR_PPRE2_MASK 0x7 -#define RCC_CFGR_PPRE2_SHIFT 11 - -/* PPRE1: APB low-speed prescaler (APB1) */ -/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors -@{*/ -#define RCC_CFGR_PPRE1_NODIV 0x0 -#define RCC_CFGR_PPRE1_DIV2 0x4 -#define RCC_CFGR_PPRE1_DIV4 0x5 -#define RCC_CFGR_PPRE1_DIV8 0x6 -#define RCC_CFGR_PPRE1_DIV16 0x7 -/**@}*/ -#define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE1_SHIFT 8 /* HPRE: AHB prescaler */ /** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors @@ -230,6 +221,24 @@ #define RCC_CFGR_SW_MASK 0x3 #define RCC_CFGR_SW_SHIFT 0 +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_PPRE2_NODIV 0x0 +#define RCC_CFGR_PPRE2_DIV2 0x4 +#define RCC_CFGR_PPRE2_DIV4 0x5 +#define RCC_CFGR_PPRE2_DIV8 0x6 +#define RCC_CFGR_PPRE2_DIV16 0x7 + +#define RCC_CFGR_PPRE1_NODIV 0x0 +#define RCC_CFGR_PPRE1_DIV2 0x4 +#define RCC_CFGR_PPRE1_DIV4 0x5 +#define RCC_CFGR_PPRE1_DIV8 0x6 +#define RCC_CFGR_PPRE1_DIV16 0x7 +/**@}*/ + /* --- RCC_CIER - Clock interrupt enable register */ #define RCC_CIER_CSSLSE (1 << 7) diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index 6540c6a6..b688a34f 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -164,34 +164,33 @@ #define RCC_CFGR_PLLSRC_HSI_CLK 0x0 #define RCC_CFGR_PLLSRC_HSE_CLK 0x1 -/* PPRE2: APB high-speed prescaler (APB2) */ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 -#define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE2_SHIFT 11 - -/* PPRE1: APB low-speed prescaler (APB1) */ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 -#define RCC_CFGR_PPRE1_MASK 0x7 +#define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE1_SHIFT 8 +#define RCC_CFGR_PPRE1_MASK 0x7 +/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors + * These can be used for both APB1 and APB2 prescaling + * @{ + */ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 +/**@}*/ -/* HPRE: AHB prescaler */ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale factors +@{*/ +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 0x8 +#define RCC_CFGR_HPRE_DIV4 0x9 +#define RCC_CFGR_HPRE_DIV8 0xa +#define RCC_CFGR_HPRE_DIV16 0xb +#define RCC_CFGR_HPRE_DIV64 0xc +#define RCC_CFGR_HPRE_DIV128 0xd +#define RCC_CFGR_HPRE_DIV256 0xe +#define RCC_CFGR_HPRE_DIV512 0xf +/**@}*/ #define RCC_CFGR_HPRE_MASK 0xf #define RCC_CFGR_HPRE_SHIFT 4 @@ -211,6 +210,35 @@ #define RCC_CFGR_SW_MASK 0x3 #define RCC_CFGR_SW_SHIFT 0 +/** Older compatible definitions to ease migration + * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers + * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families + * @{ + */ +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 + +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 + +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf + +/**@}*/ + /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */