stm32h7: Updated pwr and rcc configs to support devices with SMPS.
Worked in nuances for differences between versions of STM32H7 devices, such as handling of ODEN, explicit SCUEN bit, and different VOS mappings. This has been validated on the STM32H7A3 and STM32H743 MCUs.
This commit is contained in:
Brian Viele
Karl Palsson
parent
7b88c2d9d2
commit
c2dbea012b
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@ -154,4 +154,7 @@
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#define TIM3_BASE 0x40000400U
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#define TIM2_BASE 0x40000000U
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/* Debug/Trace Peripherals */
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#define DBGMCU_BASE 0x5C001000U
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#endif
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@ -47,8 +47,12 @@ LGPL License Terms @ref lgpl_license
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/** CPU Power control register 3. */
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#define PWR_CPUCR MMIO32(POWER_CONTROL_BASE + 0x10)
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/** D3 Domain Power Control register. */
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/** D3 Domain Power Control register.
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* Note: Referred to as PWR_SRDCR (SmartRun Domain Control) on LP devices.
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* The VOS bitfield differs between the two implementations (unfortunately).
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*/
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#define PWR_D3CR MMIO32(POWER_CONTROL_BASE + 0x18)
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#define PWR_SRDCR MMIO32(POWER_CONTROL_BASE + 0x18)
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/** Wakeup Domain Power Control register. */
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#define PWR_WKUPCR MMIO32(POWER_CONTROL_BASE + 0x20)
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@ -57,39 +61,133 @@ LGPL License Terms @ref lgpl_license
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/** VOS[15:14]: Regulator voltage scaling output selection */
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#define PWR_CR1_SVOS_SHIFT 14
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#define PWR_CR1_SVOS_MASK (0x3)
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#define PWR_CR1_SVOS_SCALE_3 (0x3)
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#define PWR_CR1_SVOS_SCALE_4 (0x2)
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#define PWR_CR1_SVOS_SCALE_5 (0x1)
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#define PWR_CR1_SVOS_MASK (0x3)
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/** SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */
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#define PWR_CR1_SRDRAMSO BIT27
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/** high-speed interfaces USB and FDCAN memory shut-off in DStop/DStop2 mode */
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#define PWR_CR1_HSITFSO BIT26
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/** GFXMMU and JPEG memory shut-off in DStop/DStop2 mode */
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#define PWR_CR1_GFXSO BIT25
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/** instruction TCM and ETM memory shut-off in DStop/DStop2 mode */
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#define PWR_CR1_ITCMSO BIT24
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/** AHB SRAM2 shut-off in DStop/DStop2 mode */
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#define PWR_CR1_AHBRAM2SO BIT23
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/** AHB SRAM1 shut-off in DStop/DStop2 mode */
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#define PWR_CR1_AHBRAM1SO BIT22
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/** AXI SRAM3 shut-off in DStop/DStop2 mode */
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#define PWR_CR1_AXIRAM3SO BIT21
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/** AXI SRAM2 shut-off in DStop/DStop2 mode */
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#define PWR_CR1_AXIRAM2SO BIT20
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/** AXI SRAM1 shut-off in DStop/DStop2 mode */
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#define PWR_CR1_AXIRAM1SO BIT19
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/** voltage threshold detected by the AVD. */
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#define PWR_CR1_ALS_SHIFT 17
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#define PWR_CR1_ALS_MASK 0x3
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#define PWR_CR1_ALS_1P7V 0x0
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#define PWR_CR1_ALS_2P1V 0x1
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#define PWR_CR1_ALS_2P5V 0x2
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#define PWR_CR1_ALS_2P8V 0x3
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/** peripheral voltage monitor on V DDA enable */
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#define PWR_CR1_AVDEN BIT16
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/** analog voltage ready
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* This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).
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* It must be set by software when the expected V DDA analog supply level is available.
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* The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after
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* setting the AVDEN bit and selecting the supply level to be monitored (ALS bits).
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*/
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#define PWR_CR1_AVD_READY BIT13
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/** analog switch VBoost control
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* This bit enables the booster to guarantee the analog switch AC performance when the V DD
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* supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same
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* switch performance over the full supply voltage range)
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* The V DD supply voltage can be monitored through the PVD and the PLS bits.
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*/
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#define PWR_CR1_BOOSTE BIT12
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/** DBP[8]: Disable backup domain write protection. */
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#define PWR_CR1_DBP (1 << 8)
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#define PWR_CR1_DBP BIT8
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/** CSR1 Register Bits */
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#define PWR_CSR1_MMCVDO BIT17
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#define PWR_CSR1_AVDO BIT16
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#define PWR_CSR1_ACTVOS_SHIFT 14
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#define PWR_CSR1_ACTVOSRDY BIT13
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#define PWR_CSR1_PVDO BIT4
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/** CR2 Register Bits */
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/** temperature level monitoring versus high threshold */
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#define PWR_CR2_TEMPH BIT23
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/** temperature level monitoring versus low threshold */
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#define PWR_CR2_TEMPL BIT22
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/** backup regulator ready */
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#define PWR_CR2_BRRDY BIT16
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/** V BAT and temperature monitoring enable */
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#define PWR_CR2_MONEN BIT4
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/** backup regulator enable */
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#define PWR_CR2_BREN BIT0
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/** CR3 Register Bits */
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#define PWR_CR3_USB33RDY BIT26
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#define PWR_CR3_USBREGEN BIT25
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#define PWR_CR3_USB33DEN BIT24
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/** SMPS step-down converter external supply ready */
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#define PWR_CR3_SMPSEXTRDY BIT16
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/** V BAT charging resistor selection */
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#define PWR_CR3_VBRS BIT9
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/** V BAT charging enable */
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#define PWR_CR3_VBE BIT8
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/** SMPS step-down converter voltage output level selection
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* This setting is used when both the LDO and SMPS step-down converter are enabled with SMPSEN and
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* LDOEN enabled or when SMPSEXTHP is enabled. In this case SMPSLEVEL must be written with
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* a value different than 00 to reach the appropriate voltage, based on VOS or external supply.
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*/
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#define PWR_CR3_SMPSLEVEL_SHIFT 4
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#define PWR_CR3_SMPSLEVEL_MASK 0x3
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#define PWR_CR3_SMPSLEVEL_VOS 0x0
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#define PWR_CR3_SMPSLEVEL_1P8V 0x1
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#define PWR_CR3_SMPSLEVEL_2P5V 0x2
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/** SMPS step-down converter external power delivery selection */
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#define PWR_CR3_SMPSEXTHP BIT3
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#define PWR_CR3_SCUEN BIT2
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/* BIT2 Is overloaded on devices with SMPS as the SMPSEN bit. */
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#define PWR_CR3_SMPSEN BIT2
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#define PWR_CR3_LDOEN BIT1
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#define PWR_CR3_BYPASS BIT0
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/** D3CR Register Bits */
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#define PWR_D3CR_VOS_SHIFT 14
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#define PWR_D3CR_VOSRDY BIT13
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#define PWR_D3CR_VOS_SHIFT 14
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#define PWR_D3CR_VOS_MASK (0x03)
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/** VOS0 is implemented on STM32H72x/3x with simple VOS setting.
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* STM32H742/43/45/47/50/53/55/57 SCALE0 this as SCALE1 + SYSCFG.ODEN */
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#define PWR_D3CR_VOS_SCALE_0 (0x0)
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#define PWR_D3CR_VOS_SCALE_3 (0x1)
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#define PWR_D3CR_VOS_SCALE_2 (0x2)
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#define PWR_D3CR_VOS_SCALE_1 (0x3)
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#define PWR_D3CR_VOS_MASK (0x03)
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/** SRDCR Register Bits */
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#define PWR_SRDCR_VOSRDY BIT13
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#define PWR_SRDCR_VOS_SHIFT 14
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#define PWR_SRDCR_VOS_MASK (0x03)
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#define PWR_SRDCR_VOS_SCALE_3 (0x0)
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#define PWR_SRDCR_VOS_SCALE_2 (0x1)
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#define PWR_SRDCR_VOS_SCALE_1 (0x2)
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#define PWR_SRDCR_VOS_SCALE_0 (0x3)
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enum pwr_sys_mode {
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PWR_SYS_SCU_LDO = 0, /**< STM32H742/43/50/53 has special SCUEN handling, use for LDO. */
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PWR_SYS_SCU_BYPASS, /**< STM32H742/43/50/53 has special SCUEN handling, use for bypass. */
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PWR_SYS_LDO, /**< Devices with SMPS use this to run from LDO only. */
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PWR_SYS_SMPS_DIRECT, /**< Disable LDO, apply SMPS direct to CPU using VOS. */
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PWR_SYS_SMPS_LDO, /**< SMPS supplies internal LDO. */
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PWR_SYS_EXT_SMPS_LDO, /**< SMPS supplies external power, and CPU through LDO. */
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PWR_SYS_EXT_SMPS_LDO_BYP, /**< SMPS supplies external power, bypasses LDO (e.g. external LDO) */
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PWR_SYS_BYPASS /**< Disable all internal power supplies. */
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};
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enum pwr_svos_scale {
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PWR_SVOS_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT,
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@ -98,10 +196,11 @@ enum pwr_svos_scale {
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};
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enum pwr_vos_scale {
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PWR_VOS_SCALE_0 = 0, /* Note: This state requires SYSCFG ODEN set. */
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PWR_VOS_SCALE_1 = (PWR_D3CR_VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT),
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PWR_VOS_SCALE_2 = (PWR_D3CR_VOS_SCALE_2 << PWR_D3CR_VOS_SHIFT),
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PWR_VOS_SCALE_3 = (PWR_D3CR_VOS_SCALE_3 << PWR_D3CR_VOS_SHIFT)
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PWR_VOS_SCALE_UNDEFINED = 0,
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PWR_VOS_SCALE_0,
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PWR_VOS_SCALE_1,
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PWR_VOS_SCALE_2,
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PWR_VOS_SCALE_3,
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};
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BEGIN_DECLS
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@ -109,16 +208,37 @@ BEGIN_DECLS
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/** @defgroup pwr_peripheral_api PWR Peripheral API
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* @ingroup peripheral_apis
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@{*/
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/** Set power subsystem to utilize the LDO for CPU. */
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void pwr_set_mode_ldo(void);
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/** Set the voltage scaling/strength for the internal LDO when in Stop mode.
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/** Specific STM32H742/43/50/53 LDO mode setting.. */
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void pwr_set_mode_scu_ldo(void);
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/** Set power subsystem to utilize the SMPS run through the LDO for CPU.
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* @param[in] supply_external Supply is powering external circuits, enable high power mode.
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* @param[in] smps_level Voltage level from available PWR_CR3_SMPSLEVEL_XXX settings (1.8V/2.5V)
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* @param[in] use_ldo Set this value to true if the internal LDO should be enabled.
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*/
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void pwr_set_mode_smps_ldo(bool supply_external, uint32_t smps_level, bool use_ldo);
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/** Set power system based on "System Supply Configurations" table in reference manual.
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* @param[in] mode Mode mapping to a mode in the system configuration. Note special SCU modes.
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* @param[in] smps_level Optional, only needed if using an EXT_SMPS or SMPS_LDO mode.
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*/
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void pwr_set_mode(enum pwr_sys_mode mode, uint8_t smps_level);
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/** Set power subsystem to bypass all internal supplies. */
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void pwr_set_mode_bypass(void);
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/** Specific STM32H742/43/50/53 Bypsass mode setting.. */
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void pwr_set_mode_scu_bypass(void);
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/** Set the voltage scaling/strength for the internal SMPS/LDO when in Stop mode.
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* @param[in] scale Voltage scale value to set.
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*/
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void pwr_set_svos_scale(enum pwr_svos_scale scale);
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/** Set the voltage scaling/strength for the internal LDO while running.
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/** Set the voltage scaling/strength for the internal SMPS/LDO while running.
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* @param[in] scale Voltage scale value to set.
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*/
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void pwr_set_vos_scale(enum pwr_vos_scale scale);
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@ -462,7 +462,9 @@ struct rcc_pll_config {
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uint8_t ppre3; /**< APB3 Peripheral prescaler note: domain 1. */
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uint8_t ppre4; /**< APB4 Peripheral prescaler note: domain 3. */
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uint8_t flash_waitstates; /**< Latency Value to set for flahs. */
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enum pwr_vos_scale voltage_scale; /**< LDO Voltage scale used for this frequency. */
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enum pwr_vos_scale voltage_scale; /**< LDO/SMPS Voltage scale used for this frequency. */
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enum pwr_sys_mode power_mode; /**< LDO/SMPS configuration for device. */
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uint8_t smps_level; /**< If using SMPS, voltage level to set. */
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};
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#define _REG_BIT(base, bit) (((base) << 5) + (bit))
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@ -30,15 +30,80 @@
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/dbgmcu.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/syscfg.h>
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/* DBGMCU_IDC DEV ID values needed to account for variations between part types. */
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#define DBGMCU_IDCODE_DEV_ID_STM32H74X_5X 0x450
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#define DBGMCU_IDCODE_DEV_ID_STM32H7A3_B3_B0 0x480
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void pwr_set_mode_ldo(void) {
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const uint32_t ldo_mask = (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
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PWR_CR3 = (PWR_CR3 & ~ldo_mask) | (PWR_CR3_SCUEN | PWR_CR3_LDOEN);
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/* Per table in manual for SMPS, mask and set SMPSEN=0 : LDOEN=1 : BYPASS=0. */
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const uint32_t cr3_mask = (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
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PWR_CR3 = (PWR_CR3 & ~cr3_mask) | (PWR_CR3_LDOEN);
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}
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void pwr_set_mode_scu_ldo(void) {
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const uint32_t cr3_mask = (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
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PWR_CR3 = (PWR_CR3 & ~cr3_mask) | (PWR_CR3_SCUEN | PWR_CR3_LDOEN);
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}
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void pwr_set_mode_smps_ldo(bool supply_external, uint32_t smps_level, bool use_ldo) {
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uint32_t cr3_mask, cr3_set;
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cr3_mask = (PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
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cr3_mask |= PWR_CR3_SMPSLEVEL_MASK << PWR_CR3_SMPSLEVEL_SHIFT;
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/* Default, take in unconditional settings, will OR in the rest. */
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cr3_set = PWR_CR3_SMPSEN | (smps_level << PWR_CR3_SMPSLEVEL_SHIFT);
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if (supply_external) {
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cm3_assert(smps_level != PWR_CR3_SMPSLEVEL_VOS); /* Unsupported setting! */
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cr3_set |= PWR_CR3_SMPSEXTHP;
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}
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if (use_ldo) {
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cr3_set |= PWR_CR3_LDOEN;
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}
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PWR_CR3 = (PWR_CR3 & ~cr3_mask) | cr3_set;
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}
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void pwr_set_mode_bypass(void) {
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const uint32_t cr3_mask = (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
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PWR_CR3 = (PWR_CR3 & ~cr3_mask) | PWR_CR3_BYPASS;
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}
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void pwr_set_mode_scu_bypass(void) {
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const uint32_t cr3_mask = (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
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PWR_CR3 = (PWR_CR3 & ~cr3_mask) | (PWR_CR3_SCUEN | PWR_CR3_BYPASS);
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}
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void pwr_set_mode(enum pwr_sys_mode mode, uint8_t smps_level) {
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switch (mode) {
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case PWR_SYS_SCU_LDO:
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pwr_set_mode_scu_ldo();
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break;
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case PWR_SYS_SCU_BYPASS:
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pwr_set_mode_scu_bypass();
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break;
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case PWR_SYS_LDO:
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pwr_set_mode_ldo();
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break;
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case PWR_SYS_SMPS_DIRECT:
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case PWR_SYS_SMPS_LDO:
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pwr_set_mode_smps_ldo(false, PWR_CR3_SMPSLEVEL_VOS, mode == PWR_SYS_SMPS_LDO);
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break;
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case PWR_SYS_EXT_SMPS_LDO:
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case PWR_SYS_EXT_SMPS_LDO_BYP:
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pwr_set_mode_smps_ldo(false, smps_level, mode == PWR_SYS_EXT_SMPS_LDO);
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break;
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case PWR_SYS_BYPASS:
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pwr_set_mode_bypass();
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break;
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}
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/* Wait for power supply status to state ready. */
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while (!(PWR_CSR1 & PWR_CSR1_ACTVOSRDY));
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}
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@ -50,16 +115,49 @@ void pwr_set_svos_scale(enum pwr_svos_scale scale)
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}
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void pwr_set_vos_scale(enum pwr_vos_scale scale) {
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rcc_periph_clock_enable(RCC_SYSCFG); /* Ensure we can access ODEN. */
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uint32_t d3cr_masked = PWR_D3CR & ~(PWR_D3CR_VOS_MASK << PWR_D3CR_VOS_SHIFT);
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static const uint8_t srdcr_vos_values[] = {
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PWR_SRDCR_VOS_SCALE_0,
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PWR_SRDCR_VOS_SCALE_1,
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PWR_SRDCR_VOS_SCALE_2,
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PWR_SRDCR_VOS_SCALE_3,
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};
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static const uint8_t d3cr_vos_values[] = {
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PWR_D3CR_VOS_SCALE_0,
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PWR_D3CR_VOS_SCALE_1,
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PWR_D3CR_VOS_SCALE_2,
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PWR_D3CR_VOS_SCALE_3,
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};
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cm3_assert(scale != PWR_VOS_SCALE_UNDEFINED); /* Make sure this has been set. */
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/* Per the manual, VOS0 is implemented as VOS1 + ODEN. Handle this case. */
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if (scale == PWR_VOS_SCALE_0) {
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PWR_D3CR = d3cr_masked | PWR_VOS_SCALE_1;
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SYSCFG_PWRCR |= SYSCFG_PWRCR_ODEN;
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/* "SmartRun Domain" devices (presently only know of A3/B3/B0) have different mapping.
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* Note: DBGMCU_IDCODE_DEV_ID_STM32H7A3 covers all three of these models.
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*/
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uint32_t devid = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK;
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if (devid == DBGMCU_IDCODE_DEV_ID_STM32H7A3_B3_B0) {
|
||||
const uint32_t srdcr_vos_mask = (PWR_SRDCR_VOS_MASK << PWR_SRDCR_VOS_SHIFT);
|
||||
const uint32_t vos_value = srdcr_vos_values[scale - 1] << PWR_SRDCR_VOS_SHIFT;
|
||||
PWR_SRDCR = (PWR_SRDCR & ~srdcr_vos_mask) | vos_value;
|
||||
} else {
|
||||
SYSCFG_PWRCR &= ~SYSCFG_PWRCR_ODEN;
|
||||
PWR_D3CR = d3cr_masked | scale;
|
||||
/* Get the VOS value for the non-smart domain types. */
|
||||
uint32_t d3cr_vos = (uint32_t)d3cr_vos_values[scale - 1] << PWR_D3CR_VOS_SHIFT;
|
||||
uint32_t d3cr_masked = PWR_D3CR & ~(PWR_D3CR_VOS_MASK << PWR_D3CR_VOS_SHIFT);
|
||||
/* STM32H742/43/45/47/50/53/55/57 have special handling of VOS0, which is to set
|
||||
* VOS1, and also enable the ODEN in the SYSCFG_PWRCR.
|
||||
* Note: Conveniently, all devices with this setup share a devid, so pick one.
|
||||
*/
|
||||
if (devid == DBGMCU_IDCODE_DEV_ID_STM32H74X_5X) {
|
||||
rcc_periph_clock_enable(RCC_SYSCFG); /* Ensure we can access ODEN. */
|
||||
/* Per the manual, VOS0 is implemented as VOS1 + ODEN. Handle this case. */
|
||||
if (scale == PWR_VOS_SCALE_0) {
|
||||
PWR_D3CR = d3cr_masked | (PWR_D3CR_VOS_SCALE_1 << PWR_SRDCR_VOS_SHIFT);
|
||||
SYSCFG_PWRCR |= SYSCFG_PWRCR_ODEN;
|
||||
} else {
|
||||
SYSCFG_PWRCR &= ~SYSCFG_PWRCR_ODEN;
|
||||
PWR_D3CR = d3cr_masked | d3cr_vos;
|
||||
}
|
||||
} else {
|
||||
PWR_D3CR = d3cr_masked | d3cr_vos;
|
||||
}
|
||||
}
|
||||
while (!(PWR_D3CR & PWR_D3CR_VOSRDY));
|
||||
while (!(PWR_D3CR & PWR_D3CR_VOSRDY)); /* VOSRDY bit is same between D3CR and SRDCR. */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -185,8 +185,8 @@ void rcc_clock_setup_pll(const struct rcc_pll_config *config) {
|
|||
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI);
|
||||
RCC_CR = RCC_CR_HSION;
|
||||
|
||||
/* Now that we're safely running on HSI, let's setup the LDO. */
|
||||
pwr_set_mode_ldo();
|
||||
/* Now that we're safely running on HSI, let's setup the power system for scaling. */
|
||||
pwr_set_mode(config->power_mode, config->smps_level);
|
||||
pwr_set_vos_scale(config->voltage_scale);
|
||||
|
||||
/* Set flash waitstates. Enable flash prefetch if we have at least 1WS */
|
||||
|
|
|
|||
Loading…
Reference in New Issue