stm32g4: Implement PWR
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Ben Brewer
Karl Palsson
parent
3afd16b5d9
commit
c26eab2513
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/** @defgroup pwr_defines PWR Defines
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*
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* @ingroup STM32G4xx_defines
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*
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* @brief <b>Defined Constants and Types for the STM32G4xx Power Control</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
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* @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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* @author @htmlonly © @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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*
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* @date 29 July 2020
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
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* Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H
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The order of header inclusion is important. pwr.h includes the device
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specific memorymap.h header before including this header file.*/
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/**@{*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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/* --- PWR registers ------------------------------------------------------- */
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#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)
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#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)
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#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)
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#define PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0C)
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#define PWR_CR5 MMIO32(POWER_CONTROL_BASE + 0x80)
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#define PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)
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#define PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)
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#define PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)
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#define PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)
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#define PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)
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#define PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)
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#define PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)
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#define PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)
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#define PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)
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#define PWR_PORT_G MMIO32(POWER_CONTROL_BASE + 0x50)
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#define PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)
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#define PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)
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/* --- PWR_CR1 values ------------------------------------------------------- */
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#define PWR_CR1_LPR (1 << 14)
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#define PWR_CR1_VOS_SHIFT 9
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#define PWR_CR1_VOS_MASK 0x3
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#define PWR_CR1_VOS_RANGE_1 1
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#define PWR_CR1_VOS_RANGE_2 2
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#define PWR_CR1_DBP (1 << 8)
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#define PWR_CR1_LPMS_SHIFT 0
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#define PWR_CR1_LPMS_MASK 0x07
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#define PWR_CR1_LPMS_STOP_0 0
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#define PWR_CR1_LPMS_STOP_1 1
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#define PWR_CR1_LPMS_STOP_2 2
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#define PWR_CR1_LPMS_STANDBY 3
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#define PWR_CR1_LPMS_SHUTDOWN 4
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/* --- PWR_CR2 values ------------------------------------------------------- */
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#define PWR_CR2_PVMEN2 (1 << 7)
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#define PWR_CR2_PVMEN1 (1 << 6)
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#define PWR_CR2_PLS_SHIFT 1
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#define PWR_CR2_PLS_MASK 0x07
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/** @defgroup pwr_pls PVD level selection
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@ingroup STM32G4_pwr_defines
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@{*/
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#define PWR_CR2_PLS_2V0 0x00
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#define PWR_CR2_PLS_2V2 0x01
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#define PWR_CR2_PLS_2V4 0x02
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#define PWR_CR2_PLS_2V5 0x03
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#define PWR_CR2_PLS_2V6 0x04
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#define PWR_CR2_PLS_2V8 0x05
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#define PWR_CR2_PLS_2V9 0x06
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#define PWR_CR2_PLS_PVD_IN 0x07
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/**@}*/
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#define PWR_CR2_PVDE (1 << 0)
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/* --- PWR_CR3 values ------------------------------------------------------- */
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#define PWR_CR3_EIWUL (1 << 15)
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#define PWR_CR3_UCPD1_DBDIS (1 << 15)
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#define PWR_CR3_UCPD1_STDBY (1 << 15)
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#define PWR_CR3_APC (1 << 10)
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#define PWR_CR3_RRS (1 << 8)
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#define PWR_CR3_EWUP5 (1 << 4)
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#define PWR_CR3_EWUP4 (1 << 3)
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#define PWR_CR3_EWUP3 (1 << 2)
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#define PWR_CR3_EWUP2 (1 << 1)
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#define PWR_CR3_EWUP1 (1 << 0)
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/* --- PWR_CR4 values ------------------------------------------------------- */
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#define PWR_CR4_VBRS (1 << 9)
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#define PWR_CR4_VBE (1 << 8)
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#define PWR_CR4_WP5 (1 << 4)
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#define PWR_CR4_WP4 (1 << 3)
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#define PWR_CR4_WP3 (1 << 2)
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#define PWR_CR4_WP2 (1 << 1)
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#define PWR_CR4_WP1 (1 << 0)
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/* --- PWR_CR4 values ------------------------------------------------------- */
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#define PWR_CR5_R1MODE_SHIFT 8
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#define PWR_CR5_R1MODE_MASK 0x1
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#define PWR_CR5_R1MODE_BOOST 0
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#define PWR_CR5_R1MODE_NORMAL 1
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#define PWR_CR5_R1MODE (PWR_CR5_R1MODE_MASK << PWR_CR5_R1MODE_SHIFT)
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/* --- PWR_SR1 values ------------------------------------------------------- */
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#define PWR_SR1_WUFI (1 << 15)
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#define PWR_SR1_SBF (1 << 8)
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#define PWR_SR1_WUF5 (1 << 4)
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#define PWR_SR1_WUF4 (1 << 3)
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#define PWR_SR1_WUF3 (1 << 2)
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#define PWR_SR1_WUF2 (1 << 1)
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#define PWR_SR1_WUF1 (1 << 0)
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/* --- PWR_SR2 values ------------------------------------------------------- */
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#define PWR_SR2_PVMO2 (1 << 15)
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#define PWR_SR2_PVMO1 (1 << 14)
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#define PWR_SR2_PVDO (1 << 11)
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#define PWR_SR2_VOSF (1 << 10)
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#define PWR_SR2_REGLPF (1 << 9)
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#define PWR_SR2_REGLPS (1 << 8)
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/* --- PWR_SCR values ------------------------------------------------------- */
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#define PWR_SCR_CSBF (1 << 8)
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#define PWR_SCR_CWUF5 (1 << 4)
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#define PWR_SCR_CWUF4 (1 << 3)
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#define PWR_SCR_CWUF3 (1 << 2)
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#define PWR_SCR_CWUF2 (1 << 1)
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#define PWR_SCR_CWUF1 (1 << 0)
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/* --- PWR function prototypes ------------------------------------------- */
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enum pwr_vos_scale {
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PWR_SCALE1 = PWR_CR1_VOS_RANGE_1,
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PWR_SCALE2 = PWR_CR1_VOS_RANGE_2,
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};
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BEGIN_DECLS
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void pwr_set_vos_scale(enum pwr_vos_scale scale);
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void pwr_disable_backup_domain_write_protect(void);
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void pwr_enable_backup_domain_write_protect(void);
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void pwr_set_low_power_mode_selection(uint32_t lpms);
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void pwr_enable_power_voltage_detect(uint32_t pvd_level);
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void pwr_disable_power_voltage_detect(void);
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void pwr_enable_boost(void);
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void pwr_disable_boost(void);
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END_DECLS
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#endif
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/**@}*/
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@ -40,6 +40,8 @@
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# include <libopencm3/stm32/l4/pwr.h>
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#elif defined(STM32G0)
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# include <libopencm3/stm32/g0/pwr.h>
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#elif defined(STM32G4)
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# include <libopencm3/stm32/g4/pwr.h>
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#elif defined(STM32H7)
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# include <libopencm3/stm32/h7/pwr.h>
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#else
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@ -36,6 +36,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS)
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ARFLAGS = rcs
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OBJS += gpio_common_all.o gpio_common_f0234.o
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OBJS += pwr.o
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OBJS += rcc_common_all.o
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VPATH += ../../usb:../:../../cm3:../common
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@ -0,0 +1,121 @@
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/** @defgroup pwr_file PWR peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @brief <b>libopencm3 STM32G4xx Power Control</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
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* @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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* @author @htmlonly © @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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*
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* @date 29 July 2020
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*
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* This library supports the power control system for the
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* STM32G4 series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
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* Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/pwr.h>
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void pwr_set_vos_scale(enum pwr_vos_scale scale)
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{
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uint32_t reg32;
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reg32 = PWR_CR1 & ~(PWR_CR1_VOS_MASK << PWR_CR1_VOS_SHIFT);
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reg32 |= (scale & PWR_CR1_VOS_MASK) << PWR_CR1_VOS_SHIFT;
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PWR_CR1 = reg32;
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}
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/** Disable Backup Domain Write Protection
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*
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* This allows backup domain registers to be changed. These registers are write
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* protected after a reset.
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*/
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void pwr_disable_backup_domain_write_protect(void)
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{
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PWR_CR1 |= PWR_CR1_DBP;
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}
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/** Re-enable Backup Domain Write Protection
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*
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* This protects backup domain registers from inadvertent change.
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*/
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void pwr_enable_backup_domain_write_protect(void)
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{
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PWR_CR1 &= ~PWR_CR1_DBP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Select the low power mode used in deep sleep.
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* @param lpms low power mode @ref pwr_cr1_lpms
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*/
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void pwr_set_low_power_mode_selection(uint32_t lpms)
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{
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uint32_t reg32;
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reg32 = PWR_CR1;
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reg32 &= ~(PWR_CR1_LPMS_MASK << PWR_CR1_LPMS_SHIFT);
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PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable Power Voltage Detector.
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* @param[in] pvd_level Power Voltage Detector Falling Threshold voltage @ref pwr_pls.
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*/
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void pwr_enable_power_voltage_detect(uint32_t pvd_level)
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{
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uint32_t reg32;
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reg32 = PWR_CR2;
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reg32 &= ~(PWR_CR2_PLS_MASK << PWR_CR2_PLS_SHIFT);
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PWR_CR2 = (reg32 | (pvd_level << PWR_CR2_PLS_SHIFT) | PWR_CR2_PVDE);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable Power Voltage Detector.
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*/
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void pwr_disable_power_voltage_detect(void)
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{
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PWR_CR2 &= ~PWR_CR2_PVDE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable Boost Mode.
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*/
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void pwr_enable_boost(void)
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{
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PWR_CR5 &= ~PWR_CR5_R1MODE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable Boost Mode.
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*/
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void pwr_disable_boost(void)
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{
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PWR_CR5 |= PWR_CR5_R1MODE;
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}
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/**@}*/
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