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started csv files for generation of register field stuff

This commit is contained in:
Michael Ossmann 2012-09-26 19:24:32 -06:00 committed by Piotr Esden-Tempski
parent a0624ecd21
commit ae9a6ae4af
4 changed files with 471 additions and 0 deletions
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21
scripts/data/lpc43xx/README Normal file
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These files contain information derived from the LPC43xx data sheet (UM10503).
They are intended to be used by scripts for the generation of header files and
functions.
Each line describes a field within a register. The comma separated values are:
register name (as found in include/lpc43xx/*.h),
bit position,
length in bits,
field name,
description/comment (may be empty if not specified in data sheet),
reset value (may be empty if not specified in data sheet),
access (may be empty if not specified in data sheet)
The access field may consist of any of the following codes:
r: read only
rw: read/write
rwc: read/write one to clear
rwo: read/write once
rws: read/write one to set
w: write only
ws: write one to set

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scripts/data/lpc43xx/creg.csv Normal file
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CREG_CREG0,0,1,EN1KHZ,Enable 1 kHz output,0,rw
CREG_CREG0,1,1,EN32KHZ,Enable 32 kHz output,0,rw
CREG_CREG0,2,1,RESET32KHZ,32 kHz oscillator reset,1,rw
CREG_CREG0,3,1,PD32KHZ,32 kHz power control,1,rw
CREG_CREG0,5,1,USB0PHY,USB0 PHY power control,1,rw
CREG_CREG0,6,2,ALARMCTRL,RTC_ALARM pin output control,0,rw
CREG_CREG0,8,2,BODLVL1,BOD trip level to generate an interrupt,0x3,rw
CREG_CREG0,10,2,BODLVL2,BOD trip level to generate a reset,0x3,rw
CREG_CREG0,12,2,SAMPLECTRL,SAMPLE pin input/output control,0,rw
CREG_CREG0,14,2,WAKEUP0CTRL,WAKEUP0 pin input/output control,0,rw
CREG_CREG0,16,2,WAKEUP1CTRL,WAKEUP1 pin input/output control,0,rw
CREG_M4MEMMAP,12,20,M4MAP,Shadow address when accessing memory at address 0x00000000,0x10400000,rw
CREG_CREG5,6,1,M4TAPSEL,JTAG debug select for M4 core,1,rw
CREG_CREG5,9,1,M0APPTAPSEL,JTAG debug select for M0 co-processor,1,rw
CREG_DMAMUX,0,2,DMAMUXPER0,Select DMA to peripheral connection for DMA peripheral 0,0,rw
CREG_DMAMUX,2,2,DMAMUXPER1,Select DMA to peripheral connection for DMA peripheral 1,0,rw
CREG_DMAMUX,4,2,DMAMUXPER2,Select DMA to peripheral connection for DMA peripheral 2,0,rw
CREG_DMAMUX,6,2,DMAMUXPER3,Select DMA to peripheral connection for DMA peripheral 3,0,rw
CREG_DMAMUX,8,2,DMAMUXPER4,Select DMA to peripheral connection for DMA peripheral 4,0,rw
CREG_DMAMUX,10,2,DMAMUXPER5,Select DMA to peripheral connection for DMA peripheral 5,0,rw
CREG_DMAMUX,12,2,DMAMUXPER6,Select DMA to peripheral connection for DMA peripheral 6,0,rw
CREG_DMAMUX,14,2,DMAMUXPER7,Select DMA to peripheral connection for DMA peripheral 7,0,rw
CREG_DMAMUX,16,2,DMAMUXPER8,Select DMA to peripheral connection for DMA peripheral 8,0,rw
CREG_DMAMUX,18,2,DMAMUXPER9,Select DMA to peripheral connection for DMA peripheral 9,0,rw
CREG_DMAMUX,20,2,DMAMUXPER10,Select DMA to peripheral connection for DMA peripheral 10,0,rw
CREG_DMAMUX,22,2,DMAMUXPER11,Select DMA to peripheral connection for DMA peripheral 11,0,rw
CREG_DMAMUX,24,2,DMAMUXPER12,Select DMA to peripheral connection for DMA peripheral 12,0,rw
CREG_DMAMUX,26,2,DMAMUXPER13,Select DMA to peripheral connection for DMA peripheral 13,0,rw
CREG_DMAMUX,28,2,DMAMUXPER14,Select DMA to peripheral connection for DMA peripheral 14,0,rw
CREG_DMAMUX,30,2,DMAMUXPER15,Select DMA to peripheral connection for DMA peripheral 15,0,rw
CREG_FLASHCFGA,12,4,FLASHTIM,Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access,,rw
CREG_FLASHCFGA,31,1,POW,Flash bank A power control,1,rw
CREG_FLASHCFGB,12,4,FLASHTIM,Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access,,rw
CREG_FLASHCFGB,31,1,POW,Flash bank B power control,1,rw
CREG_ETBCFG,0,1,ETB,Select SRAM interface,1,rw
CREG_CREG6,0,3,ETHMODE,Selects the Ethernet mode. Reset the ethernet after changing the PHY interface,,rw
CREG_CREG6,4,1,CTOUTCTRL,Selects the functionality of the SCT outputs,0,rw
CREG_CREG6,12,1,I2S0_TX_SCK_IN_SEL,I2S0_TX_SCK input select,0,rw
CREG_CREG6,13,1,I2S0_RX_SCK_IN_SEL,I2S0_RX_SCK input select,0,rw
CREG_CREG6,14,1,I2S1_TX_SCK_IN_SEL,I2S1_TX_SCK input select,0,rw
CREG_CREG6,15,1,I2S1_RX_SCK_IN_SEL,I2S1_RX_SCK input select,0,rw
CREG_CREG6,16,1,EMC_CLK_SEL,EMC_CLK divided clock select,0,rw
CREG_M4TXEVENT,0,1,TXEVCLR,Cortex-M4 TXEV event,0,rw
CREG_M0TXEVENT,0,1,TXEVCLR,Cortex-M0 TXEV event,0,rw
CREG_M0APPMEMMAP,12,20,M0APPMAP,Shadow address when accessing memory at address 0x00000000,0x20000000,rw
CREG_USB0FLADJ,0,6,FLTV,Frame length timing value,0x20,rw
CREG_USB1FLADJ,0,6,FLTV,Frame length timing value,0x20,rw
1 CREG_CREG0 0 1 EN1KHZ Enable 1 kHz output 0 rw
2 CREG_CREG0 1 1 EN32KHZ Enable 32 kHz output 0 rw
3 CREG_CREG0 2 1 RESET32KHZ 32 kHz oscillator reset 1 rw
4 CREG_CREG0 3 1 PD32KHZ 32 kHz power control 1 rw
5 CREG_CREG0 5 1 USB0PHY USB0 PHY power control 1 rw
6 CREG_CREG0 6 2 ALARMCTRL RTC_ALARM pin output control 0 rw
7 CREG_CREG0 8 2 BODLVL1 BOD trip level to generate an interrupt 0x3 rw
8 CREG_CREG0 10 2 BODLVL2 BOD trip level to generate a reset 0x3 rw
9 CREG_CREG0 12 2 SAMPLECTRL SAMPLE pin input/output control 0 rw
10 CREG_CREG0 14 2 WAKEUP0CTRL WAKEUP0 pin input/output control 0 rw
11 CREG_CREG0 16 2 WAKEUP1CTRL WAKEUP1 pin input/output control 0 rw
12 CREG_M4MEMMAP 12 20 M4MAP Shadow address when accessing memory at address 0x00000000 0x10400000 rw
13 CREG_CREG5 6 1 M4TAPSEL JTAG debug select for M4 core 1 rw
14 CREG_CREG5 9 1 M0APPTAPSEL JTAG debug select for M0 co-processor 1 rw
15 CREG_DMAMUX 0 2 DMAMUXPER0 Select DMA to peripheral connection for DMA peripheral 0 0 rw
16 CREG_DMAMUX 2 2 DMAMUXPER1 Select DMA to peripheral connection for DMA peripheral 1 0 rw
17 CREG_DMAMUX 4 2 DMAMUXPER2 Select DMA to peripheral connection for DMA peripheral 2 0 rw
18 CREG_DMAMUX 6 2 DMAMUXPER3 Select DMA to peripheral connection for DMA peripheral 3 0 rw
19 CREG_DMAMUX 8 2 DMAMUXPER4 Select DMA to peripheral connection for DMA peripheral 4 0 rw
20 CREG_DMAMUX 10 2 DMAMUXPER5 Select DMA to peripheral connection for DMA peripheral 5 0 rw
21 CREG_DMAMUX 12 2 DMAMUXPER6 Select DMA to peripheral connection for DMA peripheral 6 0 rw
22 CREG_DMAMUX 14 2 DMAMUXPER7 Select DMA to peripheral connection for DMA peripheral 7 0 rw
23 CREG_DMAMUX 16 2 DMAMUXPER8 Select DMA to peripheral connection for DMA peripheral 8 0 rw
24 CREG_DMAMUX 18 2 DMAMUXPER9 Select DMA to peripheral connection for DMA peripheral 9 0 rw
25 CREG_DMAMUX 20 2 DMAMUXPER10 Select DMA to peripheral connection for DMA peripheral 10 0 rw
26 CREG_DMAMUX 22 2 DMAMUXPER11 Select DMA to peripheral connection for DMA peripheral 11 0 rw
27 CREG_DMAMUX 24 2 DMAMUXPER12 Select DMA to peripheral connection for DMA peripheral 12 0 rw
28 CREG_DMAMUX 26 2 DMAMUXPER13 Select DMA to peripheral connection for DMA peripheral 13 0 rw
29 CREG_DMAMUX 28 2 DMAMUXPER14 Select DMA to peripheral connection for DMA peripheral 14 0 rw
30 CREG_DMAMUX 30 2 DMAMUXPER15 Select DMA to peripheral connection for DMA peripheral 15 0 rw
31 CREG_FLASHCFGA 12 4 FLASHTIM Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access rw
32 CREG_FLASHCFGA 31 1 POW Flash bank A power control 1 rw
33 CREG_FLASHCFGB 12 4 FLASHTIM Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access rw
34 CREG_FLASHCFGB 31 1 POW Flash bank B power control 1 rw
35 CREG_ETBCFG 0 1 ETB Select SRAM interface 1 rw
36 CREG_CREG6 0 3 ETHMODE Selects the Ethernet mode. Reset the ethernet after changing the PHY interface rw
37 CREG_CREG6 4 1 CTOUTCTRL Selects the functionality of the SCT outputs 0 rw
38 CREG_CREG6 12 1 I2S0_TX_SCK_IN_SEL I2S0_TX_SCK input select 0 rw
39 CREG_CREG6 13 1 I2S0_RX_SCK_IN_SEL I2S0_RX_SCK input select 0 rw
40 CREG_CREG6 14 1 I2S1_TX_SCK_IN_SEL I2S1_TX_SCK input select 0 rw
41 CREG_CREG6 15 1 I2S1_RX_SCK_IN_SEL I2S1_RX_SCK input select 0 rw
42 CREG_CREG6 16 1 EMC_CLK_SEL EMC_CLK divided clock select 0 rw
43 CREG_M4TXEVENT 0 1 TXEVCLR Cortex-M4 TXEV event 0 rw
44 CREG_M0TXEVENT 0 1 TXEVCLR Cortex-M0 TXEV event 0 rw
45 CREG_M0APPMEMMAP 12 20 M0APPMAP Shadow address when accessing memory at address 0x00000000 0x20000000 rw
46 CREG_USB0FLADJ 0 6 FLTV Frame length timing value 0x20 rw
47 CREG_USB1FLADJ 0 6 FLTV Frame length timing value 0x20 rw

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scripts/data/lpc43xx/rgu.csv Normal file
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RESET_CTRL0,0,1,CORE_RST,Writing a one activates the reset,0,w
RESET_CTRL0,1,1,PERIPH_RST,Writing a one activates the reset,0,w
RESET_CTRL0,2,1,MASTER_RST,Writing a one activates the reset,0,w
RESET_CTRL0,4,1,WWDT_RST,Writing a one to this bit has no effect,0,
RESET_CTRL0,5,1,CREG_RST,Writing a one to this bit has no effect,0,
RESET_CTRL0,8,1,BUS_RST,Writing a one activates the reset,0,w
RESET_CTRL0,9,1,SCU_RST,Writing a one activates the reset,0,w
RESET_CTRL0,13,1,M4_RST,Writing a one activates the reset,0,w
RESET_CTRL0,16,1,LCD_RST,Writing a one activates the reset,0,w
RESET_CTRL0,17,1,USB0_RST,Writing a one activates the reset,0,w
RESET_CTRL0,18,1,USB1_RST,Writing a one activates the reset,0,w
RESET_CTRL0,19,1,DMA_RST,Writing a one activates the reset,0,w
RESET_CTRL0,20,1,SDIO_RST,Writing a one activates the reset,0,w
RESET_CTRL0,21,1,EMC_RST,Writing a one activates the reset,0,w
RESET_CTRL0,22,1,ETHERNET_RST,Writing a one activates the reset,0,w
RESET_CTRL0,25,1,FLASHA_RST,Writing a one activates the reset,0,w
RESET_CTRL0,27,1,EEPROM_RST,Writing a one activates the reset,0,w
RESET_CTRL0,28,1,GPIO_RST,Writing a one activates the reset,0,w
RESET_CTRL0,29,1,FLASHB_RST,Writing a one activates the reset,0,w
RESET_CTRL1,0,1,TIMER0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,1,1,TIMER1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,2,1,TIMER2_RST,Writing a one activates the reset,0,w
RESET_CTRL1,3,1,TIMER3_RST,Writing a one activates the reset,0,w
RESET_CTRL1,4,1,RTIMER_RST,Writing a one activates the reset,0,w
RESET_CTRL1,5,1,SCT_RST,Writing a one activates the reset,0,w
RESET_CTRL1,6,1,MOTOCONPWM_RST,Writing a one activates the reset,0,w
RESET_CTRL1,7,1,QEI_RST,Writing a one activates the reset,0,w
RESET_CTRL1,8,1,ADC0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,9,1,ADC1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,10,1,DAC_RST,Writing a one activates the reset,0,w
RESET_CTRL1,12,1,UART0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,13,1,UART1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,14,1,UART2_RST,Writing a one activates the reset,0,w
RESET_CTRL1,15,1,UART3_RST,Writing a one activates the reset,0,w
RESET_CTRL1,16,1,I2C0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,17,1,I2C1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,18,1,SSP0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,19,1,SSP1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,20,1,I2S_RST,Writing a one activates the reset,0,w
RESET_CTRL1,21,1,SPIFI_RST,Writing a one activates the reset,0,w
RESET_CTRL1,22,1,CAN1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,23,1,CAN0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,24,1,M0APP_RST,Writing a one activates the reset,1,w
RESET_CTRL1,25,1,SGPIO_RST,Writing a one activates the reset,0,w
RESET_CTRL1,26,1,SPI_RST,Writing a one activates the reset,0,w
RESET_STATUS0,0,2,CORE_RST,Status of the CORE_RST reset generator output,0x0,rw
RESET_STATUS0,2,2,PERIPH_RST,Status of the PERIPH_RST reset generator output,0x0,rw
RESET_STATUS0,4,2,MASTER_RST,Status of the MASTER_RST reset generator output,0x1,rw
RESET_STATUS0,8,2,WWDT_RST,Status of the WWDT_RST reset generator output,0x0,rw
RESET_STATUS0,10,2,CREG_RST,Status of the CREG_RST reset generator output,0x0,rw
RESET_STATUS0,16,2,BUS_RST,Status of the BUS_RST reset generator output,0x1,rw
RESET_STATUS0,18,2,SCU_RST,Status of the SCU_RST reset generator output,0x1,rw
RESET_STATUS0,26,2,M4_RST,Status of the M4_RST reset generator output,0x1,rw
RESET_STATUS1,0,2,LCD_RST,Status of the LCD_RST reset generator output,0x1,rw
RESET_STATUS1,2,2,USB0_RST,Status of the USB0_RST reset generator output,0x1,rw
RESET_STATUS1,4,2,USB1_RST,Status of the USB1_RST reset generator output,0x1,rw
RESET_STATUS1,6,2,DMA_RST,Status of the DMA_RST reset generator output,0x1,rw
RESET_STATUS1,8,2,SDIO_RST,Status of the SDIO_RST reset generator output,0x1,rw
RESET_STATUS1,10,2,EMC_RST,Status of the EMC_RST reset generator output,0x1,rw
RESET_STATUS1,12,2,ETHERNET_RST,Status of the ETHERNET_RST reset generator output,0x1,rw
RESET_STATUS1,18,2,FLASHA_RST,Status of the FLASHA_RST reset generator output,0x1,
RESET_STATUS1,22,2,EEPROM_RST,Status of the EEPROM_RST reset generator output,0x1,
RESET_STATUS1,24,2,GPIO_RST,Status of the GPIO_RST reset generator output,0x1,rw
RESET_STATUS1,26,2,FLASHB_RST,Status of the FLASHB_RST reset generator output,0x1,rw
RESET_STATUS2,0,2,TIMER0_RST,Status of the TIMER0_RST reset generator output,0x1,rw
RESET_STATUS2,2,2,TIMER1_RST,Status of the TIMER1_RST reset generator output,0x1,rw
RESET_STATUS2,4,2,TIMER2_RST,Status of the TIMER2_RST reset generator output,0x1,rw
RESET_STATUS2,6,2,TIMER3_RST,Status of the TIMER3_RST reset generator output,0x1,rw
RESET_STATUS2,8,2,RITIMER_RST,Status of the RITIMER_RST reset generator output,0x1,rw
RESET_STATUS2,10,2,SCT_RST,Status of the SCT_RST reset generator output,0x1,rw
RESET_STATUS2,12,2,MOTOCONPWM_RST,Status of the MOTOCONPWM_RST reset generator output,0x1,rw
RESET_STATUS2,14,2,QEI_RST,Status of the QEI_RST reset generator output,0x1,rw
RESET_STATUS2,16,2,ADC0_RST,Status of the ADC0_RST reset generator output,0x1,rw
RESET_STATUS2,18,2,ADC1_RST,Status of the ADC1_RST reset generator output,0x1,rw
RESET_STATUS2,20,2,DAC_RST,Status of the DAC_RST reset generator output,0x1,rw
RESET_STATUS2,24,2,UART0_RST,Status of the UART0_RST reset generator output,0x1,rw
RESET_STATUS2,26,2,UART1_RST,Status of the UART1_RST reset generator output,0x1,rw
RESET_STATUS2,28,2,UART2_RST,Status of the UART2_RST reset generator output,0x1,rw
RESET_STATUS2,30,2,UART3_RST,Status of the UART3_RST reset generator output,0x1,rw
RESET_STATUS3,0,2,I2C0_RST,Status of the I2C0_RST reset generator output,0x1,rw
RESET_STATUS3,2,2,I2C1_RST,Status of the I2C1_RST reset generator output,0x1,rw
RESET_STATUS3,4,2,SSP0_RST,Status of the SSP0_RST reset generator output,0x1,rw
RESET_STATUS3,6,2,SSP1_RST,Status of the SSP1_RST reset generator output,0x1,rw
RESET_STATUS3,8,2,I2S_RST,Status of the I2S_RST reset generator output,0x1,rw
RESET_STATUS3,10,2,SPIFI_RST,Status of the SPIFI_RST reset generator output,0x1,rw
RESET_STATUS3,12,2,CAN1_RST,Status of the CAN1_RST reset generator output,0x1,rw
RESET_STATUS3,14,2,CAN0_RST,Status of the CAN0_RST reset generator output,0x1,rw
RESET_STATUS3,16,2,M0APP_RST,Status of the M0APP_RST reset generator output,0x3,rw
RESET_STATUS3,18,2,SGPIO_RST,Status of the SGPIO_RST reset generator output,0x1,rw
RESET_STATUS3,20,2,SPI_RST,Status of the SPI_RST reset generator output,0x1,rw
RESET_ACTIVE_STATUS0,0,1,CORE_RST,Current status of the CORE_RST,0,r
RESET_ACTIVE_STATUS0,1,1,PERIPH_RST,Current status of the PERIPH_RST,0,r
RESET_ACTIVE_STATUS0,2,1,MASTER_RST,Current status of the MASTER_RST,0,r
RESET_ACTIVE_STATUS0,4,1,WWDT_RST,Current status of the WWDT_RST,0,r
RESET_ACTIVE_STATUS0,5,1,CREG_RST,Current status of the CREG_RST,0,r
RESET_ACTIVE_STATUS0,8,1,BUS_RST,Current status of the BUS_RST,0,r
RESET_ACTIVE_STATUS0,9,1,SCU_RST,Current status of the SCU_RST,0,r
RESET_ACTIVE_STATUS0,13,1,M4_RST,Current status of the M4_RST,0,r
RESET_ACTIVE_STATUS0,16,1,LCD_RST,Current status of the LCD_RST,0,r
RESET_ACTIVE_STATUS0,17,1,USB0_RST,Current status of the USB0_RST,0,r
RESET_ACTIVE_STATUS0,18,1,USB1_RST,Current status of the USB1_RST,0,r
RESET_ACTIVE_STATUS0,19,1,DMA_RST,Current status of the DMA_RST,0,r
RESET_ACTIVE_STATUS0,20,1,SDIO_RST,Current status of the SDIO_RST,0,r
RESET_ACTIVE_STATUS0,21,1,EMC_RST,Current status of the EMC_RST,0,r
RESET_ACTIVE_STATUS0,22,1,ETHERNET_RST,Current status of the ETHERNET_RST,0,r
RESET_ACTIVE_STATUS0,25,1,FLASHA_RST,Current status of the FLASHA_RST,0,r
RESET_ACTIVE_STATUS0,27,1,EEPROM_RST,Current status of the EEPROM_RST,0,r
RESET_ACTIVE_STATUS0,28,1,GPIO_RST,Current status of the GPIO_RST,0,r
RESET_ACTIVE_STATUS0,29,1,FLASHB_RST,Current status of the FLASHB_RST,0,r
RESET_ACTIVE_STATUS1,0,1,TIMER0_RST,Current status of the TIMER0_RST,0,r
RESET_ACTIVE_STATUS1,1,1,TIMER1_RST,Current status of the TIMER1_RST,0,r
RESET_ACTIVE_STATUS1,2,1,TIMER2_RST,Current status of the TIMER2_RST,0,r
RESET_ACTIVE_STATUS1,3,1,TIMER3_RST,Current status of the TIMER3_RST,0,r
RESET_ACTIVE_STATUS1,4,1,RITIMER_RST,Current status of the RITIMER_RST,0,r
RESET_ACTIVE_STATUS1,5,1,SCT_RST,Current status of the SCT_RST,0,r
RESET_ACTIVE_STATUS1,6,1,MOTOCONPWM_RST,Current status of the MOTOCONPWM_RST,0,r
RESET_ACTIVE_STATUS1,7,1,QEI_RST,Current status of the QEI_RST,0,r
RESET_ACTIVE_STATUS1,8,1,ADC0_RST,Current status of the ADC0_RST,0,r
RESET_ACTIVE_STATUS1,9,1,ADC1_RST,Current status of the ADC1_RST,0,r
RESET_ACTIVE_STATUS1,10,1,DAC_RST,Current status of the DAC_RST,0,r
RESET_ACTIVE_STATUS1,12,1,UART0_RST,Current status of the UART0_RST,0,r
RESET_ACTIVE_STATUS1,13,1,UART1_RST,Current status of the UART1_RST,0,r
RESET_ACTIVE_STATUS1,14,1,UART2_RST,Current status of the UART2_RST,0,r
RESET_ACTIVE_STATUS1,15,1,UART3_RST,Current status of the UART3_RST,0,r
RESET_ACTIVE_STATUS1,16,1,I2C0_RST,Current status of the I2C0_RST,0,r
RESET_ACTIVE_STATUS1,17,1,I2C1_RST,Current status of the I2C1_RST,0,r
RESET_ACTIVE_STATUS1,18,1,SSP0_RST,Current status of the SSP0_RST,0,r
RESET_ACTIVE_STATUS1,19,1,SSP1_RST,Current status of the SSP1_RST,0,r
RESET_ACTIVE_STATUS1,20,1,I2S_RST,Current status of the I2S_RST,0,r
RESET_ACTIVE_STATUS1,21,1,SPIFI_RST,Current status of the SPIFI_RST,0,r
RESET_ACTIVE_STATUS1,22,1,CAN1_RST,Current status of the CAN1_RST,0,r
RESET_ACTIVE_STATUS1,23,1,CAN0_RST,Current status of the CAN0_RST,0,r
RESET_ACTIVE_STATUS1,24,1,M0APP_RST,Current status of the M0APP_RST,0,r
RESET_ACTIVE_STATUS1,25,1,SGPIO_RST,Current status of the SGPIO_RST,0,r
RESET_ACTIVE_STATUS1,26,1,SPI_RST,Current status of the SPI_RST,0,r
RESET_EXT_STAT0,0,1,EXT_RESET,Reset activated by external reset from reset pin,0,rw
RESET_EXT_STAT0,4,1,BOD_RESET,Reset activated by BOD reset,0,rw
RESET_EXT_STAT0,5,1,WWDT_RESET,Reset activated by WWDT time-out,0,rw
RESET_EXT_STAT1,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
RESET_EXT_STAT2,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT4,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
RESET_EXT_STAT5,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
RESET_EXT_STAT8,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT9,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT13,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT16,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT17,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT18,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT19,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT20,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT21,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT22,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT25,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT27,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT28,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT29,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT32,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT33,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT34,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT35,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT36,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT37,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT38,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT39,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT40,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT41,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT42,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT44,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT45,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT46,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT47,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT48,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT49,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT50,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT51,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT52,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT53,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT54,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT55,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT56,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,,rw
RESET_EXT_STAT57,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT58,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
1 RESET_CTRL0 0 1 CORE_RST Writing a one activates the reset 0 w
2 RESET_CTRL0 1 1 PERIPH_RST Writing a one activates the reset 0 w
3 RESET_CTRL0 2 1 MASTER_RST Writing a one activates the reset 0 w
4 RESET_CTRL0 4 1 WWDT_RST Writing a one to this bit has no effect 0
5 RESET_CTRL0 5 1 CREG_RST Writing a one to this bit has no effect 0
6 RESET_CTRL0 8 1 BUS_RST Writing a one activates the reset 0 w
7 RESET_CTRL0 9 1 SCU_RST Writing a one activates the reset 0 w
8 RESET_CTRL0 13 1 M4_RST Writing a one activates the reset 0 w
9 RESET_CTRL0 16 1 LCD_RST Writing a one activates the reset 0 w
10 RESET_CTRL0 17 1 USB0_RST Writing a one activates the reset 0 w
11 RESET_CTRL0 18 1 USB1_RST Writing a one activates the reset 0 w
12 RESET_CTRL0 19 1 DMA_RST Writing a one activates the reset 0 w
13 RESET_CTRL0 20 1 SDIO_RST Writing a one activates the reset 0 w
14 RESET_CTRL0 21 1 EMC_RST Writing a one activates the reset 0 w
15 RESET_CTRL0 22 1 ETHERNET_RST Writing a one activates the reset 0 w
16 RESET_CTRL0 25 1 FLASHA_RST Writing a one activates the reset 0 w
17 RESET_CTRL0 27 1 EEPROM_RST Writing a one activates the reset 0 w
18 RESET_CTRL0 28 1 GPIO_RST Writing a one activates the reset 0 w
19 RESET_CTRL0 29 1 FLASHB_RST Writing a one activates the reset 0 w
20 RESET_CTRL1 0 1 TIMER0_RST Writing a one activates the reset 0 w
21 RESET_CTRL1 1 1 TIMER1_RST Writing a one activates the reset 0 w
22 RESET_CTRL1 2 1 TIMER2_RST Writing a one activates the reset 0 w
23 RESET_CTRL1 3 1 TIMER3_RST Writing a one activates the reset 0 w
24 RESET_CTRL1 4 1 RTIMER_RST Writing a one activates the reset 0 w
25 RESET_CTRL1 5 1 SCT_RST Writing a one activates the reset 0 w
26 RESET_CTRL1 6 1 MOTOCONPWM_RST Writing a one activates the reset 0 w
27 RESET_CTRL1 7 1 QEI_RST Writing a one activates the reset 0 w
28 RESET_CTRL1 8 1 ADC0_RST Writing a one activates the reset 0 w
29 RESET_CTRL1 9 1 ADC1_RST Writing a one activates the reset 0 w
30 RESET_CTRL1 10 1 DAC_RST Writing a one activates the reset 0 w
31 RESET_CTRL1 12 1 UART0_RST Writing a one activates the reset 0 w
32 RESET_CTRL1 13 1 UART1_RST Writing a one activates the reset 0 w
33 RESET_CTRL1 14 1 UART2_RST Writing a one activates the reset 0 w
34 RESET_CTRL1 15 1 UART3_RST Writing a one activates the reset 0 w
35 RESET_CTRL1 16 1 I2C0_RST Writing a one activates the reset 0 w
36 RESET_CTRL1 17 1 I2C1_RST Writing a one activates the reset 0 w
37 RESET_CTRL1 18 1 SSP0_RST Writing a one activates the reset 0 w
38 RESET_CTRL1 19 1 SSP1_RST Writing a one activates the reset 0 w
39 RESET_CTRL1 20 1 I2S_RST Writing a one activates the reset 0 w
40 RESET_CTRL1 21 1 SPIFI_RST Writing a one activates the reset 0 w
41 RESET_CTRL1 22 1 CAN1_RST Writing a one activates the reset 0 w
42 RESET_CTRL1 23 1 CAN0_RST Writing a one activates the reset 0 w
43 RESET_CTRL1 24 1 M0APP_RST Writing a one activates the reset 1 w
44 RESET_CTRL1 25 1 SGPIO_RST Writing a one activates the reset 0 w
45 RESET_CTRL1 26 1 SPI_RST Writing a one activates the reset 0 w
46 RESET_STATUS0 0 2 CORE_RST Status of the CORE_RST reset generator output 0x0 rw
47 RESET_STATUS0 2 2 PERIPH_RST Status of the PERIPH_RST reset generator output 0x0 rw
48 RESET_STATUS0 4 2 MASTER_RST Status of the MASTER_RST reset generator output 0x1 rw
49 RESET_STATUS0 8 2 WWDT_RST Status of the WWDT_RST reset generator output 0x0 rw
50 RESET_STATUS0 10 2 CREG_RST Status of the CREG_RST reset generator output 0x0 rw
51 RESET_STATUS0 16 2 BUS_RST Status of the BUS_RST reset generator output 0x1 rw
52 RESET_STATUS0 18 2 SCU_RST Status of the SCU_RST reset generator output 0x1 rw
53 RESET_STATUS0 26 2 M4_RST Status of the M4_RST reset generator output 0x1 rw
54 RESET_STATUS1 0 2 LCD_RST Status of the LCD_RST reset generator output 0x1 rw
55 RESET_STATUS1 2 2 USB0_RST Status of the USB0_RST reset generator output 0x1 rw
56 RESET_STATUS1 4 2 USB1_RST Status of the USB1_RST reset generator output 0x1 rw
57 RESET_STATUS1 6 2 DMA_RST Status of the DMA_RST reset generator output 0x1 rw
58 RESET_STATUS1 8 2 SDIO_RST Status of the SDIO_RST reset generator output 0x1 rw
59 RESET_STATUS1 10 2 EMC_RST Status of the EMC_RST reset generator output 0x1 rw
60 RESET_STATUS1 12 2 ETHERNET_RST Status of the ETHERNET_RST reset generator output 0x1 rw
61 RESET_STATUS1 18 2 FLASHA_RST Status of the FLASHA_RST reset generator output 0x1
62 RESET_STATUS1 22 2 EEPROM_RST Status of the EEPROM_RST reset generator output 0x1
63 RESET_STATUS1 24 2 GPIO_RST Status of the GPIO_RST reset generator output 0x1 rw
64 RESET_STATUS1 26 2 FLASHB_RST Status of the FLASHB_RST reset generator output 0x1 rw
65 RESET_STATUS2 0 2 TIMER0_RST Status of the TIMER0_RST reset generator output 0x1 rw
66 RESET_STATUS2 2 2 TIMER1_RST Status of the TIMER1_RST reset generator output 0x1 rw
67 RESET_STATUS2 4 2 TIMER2_RST Status of the TIMER2_RST reset generator output 0x1 rw
68 RESET_STATUS2 6 2 TIMER3_RST Status of the TIMER3_RST reset generator output 0x1 rw
69 RESET_STATUS2 8 2 RITIMER_RST Status of the RITIMER_RST reset generator output 0x1 rw
70 RESET_STATUS2 10 2 SCT_RST Status of the SCT_RST reset generator output 0x1 rw
71 RESET_STATUS2 12 2 MOTOCONPWM_RST Status of the MOTOCONPWM_RST reset generator output 0x1 rw
72 RESET_STATUS2 14 2 QEI_RST Status of the QEI_RST reset generator output 0x1 rw
73 RESET_STATUS2 16 2 ADC0_RST Status of the ADC0_RST reset generator output 0x1 rw
74 RESET_STATUS2 18 2 ADC1_RST Status of the ADC1_RST reset generator output 0x1 rw
75 RESET_STATUS2 20 2 DAC_RST Status of the DAC_RST reset generator output 0x1 rw
76 RESET_STATUS2 24 2 UART0_RST Status of the UART0_RST reset generator output 0x1 rw
77 RESET_STATUS2 26 2 UART1_RST Status of the UART1_RST reset generator output 0x1 rw
78 RESET_STATUS2 28 2 UART2_RST Status of the UART2_RST reset generator output 0x1 rw
79 RESET_STATUS2 30 2 UART3_RST Status of the UART3_RST reset generator output 0x1 rw
80 RESET_STATUS3 0 2 I2C0_RST Status of the I2C0_RST reset generator output 0x1 rw
81 RESET_STATUS3 2 2 I2C1_RST Status of the I2C1_RST reset generator output 0x1 rw
82 RESET_STATUS3 4 2 SSP0_RST Status of the SSP0_RST reset generator output 0x1 rw
83 RESET_STATUS3 6 2 SSP1_RST Status of the SSP1_RST reset generator output 0x1 rw
84 RESET_STATUS3 8 2 I2S_RST Status of the I2S_RST reset generator output 0x1 rw
85 RESET_STATUS3 10 2 SPIFI_RST Status of the SPIFI_RST reset generator output 0x1 rw
86 RESET_STATUS3 12 2 CAN1_RST Status of the CAN1_RST reset generator output 0x1 rw
87 RESET_STATUS3 14 2 CAN0_RST Status of the CAN0_RST reset generator output 0x1 rw
88 RESET_STATUS3 16 2 M0APP_RST Status of the M0APP_RST reset generator output 0x3 rw
89 RESET_STATUS3 18 2 SGPIO_RST Status of the SGPIO_RST reset generator output 0x1 rw
90 RESET_STATUS3 20 2 SPI_RST Status of the SPI_RST reset generator output 0x1 rw
91 RESET_ACTIVE_STATUS0 0 1 CORE_RST Current status of the CORE_RST 0 r
92 RESET_ACTIVE_STATUS0 1 1 PERIPH_RST Current status of the PERIPH_RST 0 r
93 RESET_ACTIVE_STATUS0 2 1 MASTER_RST Current status of the MASTER_RST 0 r
94 RESET_ACTIVE_STATUS0 4 1 WWDT_RST Current status of the WWDT_RST 0 r
95 RESET_ACTIVE_STATUS0 5 1 CREG_RST Current status of the CREG_RST 0 r
96 RESET_ACTIVE_STATUS0 8 1 BUS_RST Current status of the BUS_RST 0 r
97 RESET_ACTIVE_STATUS0 9 1 SCU_RST Current status of the SCU_RST 0 r
98 RESET_ACTIVE_STATUS0 13 1 M4_RST Current status of the M4_RST 0 r
99 RESET_ACTIVE_STATUS0 16 1 LCD_RST Current status of the LCD_RST 0 r
100 RESET_ACTIVE_STATUS0 17 1 USB0_RST Current status of the USB0_RST 0 r
101 RESET_ACTIVE_STATUS0 18 1 USB1_RST Current status of the USB1_RST 0 r
102 RESET_ACTIVE_STATUS0 19 1 DMA_RST Current status of the DMA_RST 0 r
103 RESET_ACTIVE_STATUS0 20 1 SDIO_RST Current status of the SDIO_RST 0 r
104 RESET_ACTIVE_STATUS0 21 1 EMC_RST Current status of the EMC_RST 0 r
105 RESET_ACTIVE_STATUS0 22 1 ETHERNET_RST Current status of the ETHERNET_RST 0 r
106 RESET_ACTIVE_STATUS0 25 1 FLASHA_RST Current status of the FLASHA_RST 0 r
107 RESET_ACTIVE_STATUS0 27 1 EEPROM_RST Current status of the EEPROM_RST 0 r
108 RESET_ACTIVE_STATUS0 28 1 GPIO_RST Current status of the GPIO_RST 0 r
109 RESET_ACTIVE_STATUS0 29 1 FLASHB_RST Current status of the FLASHB_RST 0 r
110 RESET_ACTIVE_STATUS1 0 1 TIMER0_RST Current status of the TIMER0_RST 0 r
111 RESET_ACTIVE_STATUS1 1 1 TIMER1_RST Current status of the TIMER1_RST 0 r
112 RESET_ACTIVE_STATUS1 2 1 TIMER2_RST Current status of the TIMER2_RST 0 r
113 RESET_ACTIVE_STATUS1 3 1 TIMER3_RST Current status of the TIMER3_RST 0 r
114 RESET_ACTIVE_STATUS1 4 1 RITIMER_RST Current status of the RITIMER_RST 0 r
115 RESET_ACTIVE_STATUS1 5 1 SCT_RST Current status of the SCT_RST 0 r
116 RESET_ACTIVE_STATUS1 6 1 MOTOCONPWM_RST Current status of the MOTOCONPWM_RST 0 r
117 RESET_ACTIVE_STATUS1 7 1 QEI_RST Current status of the QEI_RST 0 r
118 RESET_ACTIVE_STATUS1 8 1 ADC0_RST Current status of the ADC0_RST 0 r
119 RESET_ACTIVE_STATUS1 9 1 ADC1_RST Current status of the ADC1_RST 0 r
120 RESET_ACTIVE_STATUS1 10 1 DAC_RST Current status of the DAC_RST 0 r
121 RESET_ACTIVE_STATUS1 12 1 UART0_RST Current status of the UART0_RST 0 r
122 RESET_ACTIVE_STATUS1 13 1 UART1_RST Current status of the UART1_RST 0 r
123 RESET_ACTIVE_STATUS1 14 1 UART2_RST Current status of the UART2_RST 0 r
124 RESET_ACTIVE_STATUS1 15 1 UART3_RST Current status of the UART3_RST 0 r
125 RESET_ACTIVE_STATUS1 16 1 I2C0_RST Current status of the I2C0_RST 0 r
126 RESET_ACTIVE_STATUS1 17 1 I2C1_RST Current status of the I2C1_RST 0 r
127 RESET_ACTIVE_STATUS1 18 1 SSP0_RST Current status of the SSP0_RST 0 r
128 RESET_ACTIVE_STATUS1 19 1 SSP1_RST Current status of the SSP1_RST 0 r
129 RESET_ACTIVE_STATUS1 20 1 I2S_RST Current status of the I2S_RST 0 r
130 RESET_ACTIVE_STATUS1 21 1 SPIFI_RST Current status of the SPIFI_RST 0 r
131 RESET_ACTIVE_STATUS1 22 1 CAN1_RST Current status of the CAN1_RST 0 r
132 RESET_ACTIVE_STATUS1 23 1 CAN0_RST Current status of the CAN0_RST 0 r
133 RESET_ACTIVE_STATUS1 24 1 M0APP_RST Current status of the M0APP_RST 0 r
134 RESET_ACTIVE_STATUS1 25 1 SGPIO_RST Current status of the SGPIO_RST 0 r
135 RESET_ACTIVE_STATUS1 26 1 SPI_RST Current status of the SPI_RST 0 r
136 RESET_EXT_STAT0 0 1 EXT_RESET Reset activated by external reset from reset pin 0 rw
137 RESET_EXT_STAT0 4 1 BOD_RESET Reset activated by BOD reset 0 rw
138 RESET_EXT_STAT0 5 1 WWDT_RESET Reset activated by WWDT time-out 0 rw
139 RESET_EXT_STAT1 1 1 CORE_RESET Reset activated by CORE_RST output 0 rw
140 RESET_EXT_STAT2 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
141 RESET_EXT_STAT4 1 1 CORE_RESET Reset activated by CORE_RST output 0 rw
142 RESET_EXT_STAT5 1 1 CORE_RESET Reset activated by CORE_RST output 0 rw
143 RESET_EXT_STAT8 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
144 RESET_EXT_STAT9 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
145 RESET_EXT_STAT13 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
146 RESET_EXT_STAT16 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
147 RESET_EXT_STAT17 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
148 RESET_EXT_STAT18 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
149 RESET_EXT_STAT19 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
150 RESET_EXT_STAT20 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
151 RESET_EXT_STAT21 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
152 RESET_EXT_STAT22 3 1 MASTER_RESET Reset activated by MASTER_RST output 0 rw
153 RESET_EXT_STAT25 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
154 RESET_EXT_STAT27 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
155 RESET_EXT_STAT28 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
156 RESET_EXT_STAT29 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
157 RESET_EXT_STAT32 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
158 RESET_EXT_STAT33 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
159 RESET_EXT_STAT34 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
160 RESET_EXT_STAT35 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
161 RESET_EXT_STAT36 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
162 RESET_EXT_STAT37 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
163 RESET_EXT_STAT38 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
164 RESET_EXT_STAT39 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
165 RESET_EXT_STAT40 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
166 RESET_EXT_STAT41 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
167 RESET_EXT_STAT42 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
168 RESET_EXT_STAT44 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
169 RESET_EXT_STAT45 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
170 RESET_EXT_STAT46 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
171 RESET_EXT_STAT47 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
172 RESET_EXT_STAT48 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
173 RESET_EXT_STAT49 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
174 RESET_EXT_STAT50 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
175 RESET_EXT_STAT51 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
176 RESET_EXT_STAT52 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
177 RESET_EXT_STAT53 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
178 RESET_EXT_STAT54 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
179 RESET_EXT_STAT55 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
180 RESET_EXT_STAT56 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output rw
181 RESET_EXT_STAT57 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw
182 RESET_EXT_STAT58 2 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output 0 rw

221
scripts/data/lpc43xx/usb.csv Normal file
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@ -0,0 +1,221 @@
USB0_CAPLENGTH,0,8,CAPLENGTH,Indicates offset to add to the register base address at the beginning of the Operational Register,0x40,r
USB0_CAPLENGTH,8,16,HCIVERSION,BCD encoding of the EHCI revision number supported by this host controller,0x100,r
USB0_HCSPARAMS,0,4,N_PORTS,Number of downstream ports,0x1,r
USB0_HCSPARAMS,4,1,PPC,Port Power Control,0x1,r
USB0_HCSPARAMS,8,4,N_PCC,Number of Ports per Companion Controller,0x0,r
USB0_HCSPARAMS,12,4,N_CC,Number of Companion Controller,0x0,r
USB0_HCSPARAMS,16,1,PI,Port indicators,0x1,r
USB0_HCSPARAMS,20,4,N_PTT,Number of Ports per Transaction Translator,0x0,r
USB0_HCSPARAMS,24,4,N_TT,Number of Transaction Translators,0x0,r
USB0_HCCPARAMS,0,1,ADC,64-bit Addressing Capability,0,r
USB0_HCCPARAMS,1,1,PFL,Programmable Frame List Flag,1,r
USB0_HCCPARAMS,2,1,ASP,Asynchronous Schedule Park Capability,1,r
USB0_HCCPARAMS,4,4,IST,Isochronous Scheduling Threshold,0,r
USB0_HCCPARAMS,8,4,EECP,EHCI Extended Capabilities Pointer,0,r
USB0_DCCPARAMS,0,5,DEN,Device Endpoint Number,0x4,r
USB0_DCCPARAMS,7,1,DC,Device Capable,0x1,r
USB0_DCCPARAMS,8,1,HC,Host Capable,0x1,r
USB0_USBCMD_D,0,1,RS,Run/Stop,0,rw
USB0_USBCMD_D,1,1,RST,Controller reset,0,rw
USB0_USBCMD_D,13,1,SUTW,Setup trip wire,0,rw
USB0_USBCMD_D,14,1,ATDTW,Add dTD trip wire,0,rw
USB0_USBCMD_D,16,8,ITC,Interrupt threshold control,0x8,rw
USB0_USBCMD_H,0,1,RS,Run/Stop,0,rw
USB0_USBCMD_H,1,1,RST,Controller reset,0,rw
USB0_USBCMD_H,2,1,FS0,Bit 0 of the Frame List Size bits,0,
USB0_USBCMD_H,3,1,FS1,Bit 1 of the Frame List Size bits,0,
USB0_USBCMD_H,4,1,PSE,This bit controls whether the host controller skips processing the periodic schedule,0,rw
USB0_USBCMD_H,5,1,ASE,This bit controls whether the host controller skips processing the asynchronous schedule,0,rw
USB0_USBCMD_H,6,1,IAA,This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule,0,rw
USB0_USBCMD_H,8,2,ASP1_0,Asynchronous schedule park mode,0x3,rw
USB0_USBCMD_H,11,1,ASPE,Asynchronous Schedule Park Mode Enable,1,rw
USB0_USBCMD_H,15,1,FS2,Bit 2 of the Frame List Size bits,0,
USB0_USBCMD_H,16,8,ITC,Interrupt threshold control,0x8,rw
USB0_USBSTS_D,0,1,UI,USB interrupt,0,rwc
USB0_USBSTS_D,1,1,UEI,USB error interrupt,0,rwc
USB0_USBSTS_D,2,1,PCI,Port change detect,0,rwc
USB0_USBSTS_D,6,1,URI,USB reset received,0,rwc
USB0_USBSTS_D,7,1,SRI,SOF received,0,rwc
USB0_USBSTS_D,8,1,SLI,DCSuspend,0,rwc
USB0_USBSTS_D,16,1,NAKI,NAK interrupt bit,0,r
USB0_USBSTS_H,0,1,UI,USB interrupt,0,rwc
USB0_USBSTS_H,1,1,UEI,USB error interrupt,0,rwc
USB0_USBSTS_H,2,1,PCI,Port change detect,0,rwc
USB0_USBSTS_H,3,1,FRI,Frame list roll-over,0,rwc
USB0_USBSTS_H,5,1,AAI,Interrupt on async advance,0,rwc
USB0_USBSTS_H,7,1,SRI,SOF received,0,rwc
USB0_USBSTS_H,12,1,HCH,HCHalted,1,r
USB0_USBSTS_H,13,1,RCL,Reclamation,0,r
USB0_USBSTS_H,14,1,PS,Periodic schedule status,0,r
USB0_USBSTS_H,15,1,AS,Asynchronous schedule status,0,
USB0_USBSTS_H,18,1,UAI,USB host asynchronous interrupt (USBHSTASYNCINT),0,rwc
USB0_USBSTS_H,19,1,UPI,USB host periodic interrupt (USBHSTPERINT),0,rwc
USB0_USBINTR_D,0,1,UE,USB interrupt enable,0,rw
USB0_USBINTR_D,1,1,UEE,USB error interrupt enable,0,rw
USB0_USBINTR_D,2,1,PCE,Port change detect enable,0,rw
USB0_USBINTR_D,6,1,URE,USB reset enable,0,rw
USB0_USBINTR_D,7,1,SRE,SOF received enable,0,rw
USB0_USBINTR_D,8,1,SLE,Sleep enable,0,rw
USB0_USBINTR_D,16,1,NAKE,NAK interrupt enable,0,rw
USB0_USBINTR_H,0,1,UE,USB interrupt enable,0,rw
USB0_USBINTR_H,1,1,UEE,USB error interrupt enable,0,rw
USB0_USBINTR_H,2,1,PCE,Port change detect enable,0,rw
USB0_USBINTR_H,3,1,FRE,Frame list rollover enable,0,rw
USB0_USBINTR_H,5,1,AAE,Interrupt on asynchronous advance enable,0,rw
USB0_USBINTR_H,7,1,SRE,SOF received enable,0,
USB0_USBINTR_H,18,1,UAIE,USB host asynchronous interrupt enable,0,rw
USB0_USBINTR_H,19,1,UPIA,USB host periodic interrupt enable,0,rw
USB0_FRINDEX_D,0,3,FRINDEX2_0,Current micro frame number,,r
USB0_FRINDEX_D,3,11,FRINDEX13_3,Current frame number of the last frame transmitted,,r
USB0_FRINDEX_H,0,3,FRINDEX2_0,Current micro frame number,,rw
USB0_FRINDEX_H,3,10,FRINDEX12_3,Frame list current index,,rw
USB0_DEVICEADDR,24,1,USBADRA,Device address advance,0,
USB0_DEVICEADDR,25,7,USBADR,USB device address,0,rw
USB0_PERIODICLISTBASE,12,20,PERBASE31_12,Base Address (Low),,rw
USB0_ENDPOINTLISTADDR,11,21,EPBASE31_11,Endpoint list pointer (low),,rw
USB0_ASYNCLISTADDR,5,27,ASYBASE31_5,Link pointer (Low) LPL,,rw
USB0_TTCTRL,24,7,TTHA,Hub address when FS or LS device are connected directly,,rw
USB0_BURSTSIZE,0,8,RXPBURST,Programmable RX burst length,0x10,rw
USB0_BURSTSIZE,8,8,TXPBURST,Programmable TX burst length,0x10,rw
USB0_TXFILLTUNING,0,8,TXSCHOH,FIFO burst threshold,0x2,rw
USB0_TXFILLTUNING,8,5,TXSCHEATLTH,Scheduler health counter,0x0,rw
USB0_TXFILLTUNING,16,6,TXFIFOTHRES,Scheduler overhead,0x0,rw
USB0_BINTERVAL,0,4,BINT,bInterval value,0x00,rw
USB0_ENDPTNAK,0,6,EPRN,Rx endpoint NAK,0x00,rwc
USB0_ENDPTNAK,16,6,EPTN,Tx endpoint NAK,0x00,rwc
USB0_ENDPTNAKEN,0,6,EPRNE,Rx endpoint NAK enable,0x00,rw
USB0_ENDPTNAKEN,16,6,EPTNE,Tx endpoint NAK,0x00,rw
USB0_PORTSC1_D,0,1,CCS,Current connect status,0,r
USB0_PORTSC1_D,2,1,PE,Port enable,1,r
USB0_PORTSC1_D,3,1,PEC,Port enable/disable change,0,r
USB0_PORTSC1_D,6,1,FPR,Force port resume,0,rw
USB0_PORTSC1_D,7,1,SUSP,Suspend,0,r
USB0_PORTSC1_D,8,1,PR,Port reset,0,r
USB0_PORTSC1_D,9,1,HSP,High-speed status,0,r
USB0_PORTSC1_D,14,2,PIC1_0,Port indicator control,0,rw
USB0_PORTSC1_D,16,4,PTC3_0,Port test control,0,rw
USB0_PORTSC1_D,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
USB0_PORTSC1_D,24,1,PFSC,Port force full speed connect,0,rw
USB0_PORTSC1_D,26,2,PSPD,Port speed,0,r
USB0_PORTSC1_H,0,1,CCS,Current connect status,0,rwc
USB0_PORTSC1_H,1,1,CSC,Connect status change,0,rwc
USB0_PORTSC1_H,2,1,PE,Port enable,0,rw
USB0_PORTSC1_H,3,1,PEC,Port disable/enable change,0,rwc
USB0_PORTSC1_H,4,1,OCA,Over-current active,0,r
USB0_PORTSC1_H,5,1,OCC,Over-current change,0,rwc
USB0_PORTSC1_H,6,1,FPR,Force port resume,0,rw
USB0_PORTSC1_H,7,1,SUSP,Suspend,0,rw
USB0_PORTSC1_H,8,1,PR,Port reset,0,rw
USB0_PORTSC1_H,9,1,HSP,High-speed status,0,r
USB0_PORTSC1_H,10,2,LS,Line status,0x3,r
USB0_PORTSC1_H,12,1,PP,Port power control,0,rw
USB0_PORTSC1_H,14,2,PIC1_0,Port indicator control,0,rw
USB0_PORTSC1_H,16,4,PTC3_0,Port test control,0,rw
USB0_PORTSC1_H,20,1,WKCN,Wake on connect enable (WKCNNT_E),0,rw
USB0_PORTSC1_H,21,1,WKDC,Wake on disconnect enable (WKDSCNNT_E),0,rw
USB0_PORTSC1_H,22,1,WKOC,Wake on over-current enable (WKOC_E),0,rw
USB0_PORTSC1_H,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
USB0_PORTSC1_H,24,1,PFSC,Port force full speed connect,0,rw
USB0_PORTSC1_H,26,2,PSPD,Port speed,0,r
USB0_OTGSC,0,1,VD,VBUS_Discharge,0,rw
USB0_OTGSC,1,1,VC,VBUS_Charge,0,rw
USB0_OTGSC,2,1,HAAR,Hardware assist auto_reset,0,rw
USB0_OTGSC,3,1,OT,OTG termination,0,rw
USB0_OTGSC,4,1,DP,Data pulsing,0,rw
USB0_OTGSC,5,1,IDPU,ID pull-up,1,rw
USB0_OTGSC,6,1,HADP,Hardware assist data pulse,0,rw
USB0_OTGSC,7,1,HABA,Hardware assist B-disconnect to A-connect,0,rw
USB0_OTGSC,8,1,ID,USB ID,0,r
USB0_OTGSC,9,1,AVV,A-VBUS valid,0,r
USB0_OTGSC,10,1,ASV,A-session valid,0,r
USB0_OTGSC,11,1,BSV,B-session valid,0,r
USB0_OTGSC,12,1,BSE,B-session end,0,r
USB0_OTGSC,13,1,MS1T,1 millisecond timer toggle,0,r
USB0_OTGSC,14,1,DPS,Data bus pulsing status,0,r
USB0_OTGSC,16,1,IDIS,USB ID interrupt status,0,rwc
USB0_OTGSC,17,1,AVVIS,A-VBUS valid interrupt status,0,rwc
USB0_OTGSC,18,1,ASVIS,A-Session valid interrupt status,0,rwc
USB0_OTGSC,19,1,BSVIS,B-Session valid interrupt status,0,rwc
USB0_OTGSC,20,1,BSEIS,B-Session end interrupt status,0,rwc
USB0_OTGSC,21,1,MS1S,1 millisecond timer interrupt status,0,rwc
USB0_OTGSC,22,1,DPIS,Data pulse interrupt status,0,rwc
USB0_OTGSC,24,1,IDIE,USB ID interrupt enable,0,rw
USB0_OTGSC,25,1,AVVIE,A-VBUS valid interrupt enable,0,rw
USB0_OTGSC,26,1,ASVIE,A-session valid interrupt enable,0,rw
USB0_OTGSC,27,1,BSVIE,B-session valid interrupt enable,0,rw
USB0_OTGSC,28,1,BSEIE,B-session end interrupt enable,0,rw
USB0_OTGSC,29,1,MS1E,1 millisecond timer interrupt enable,0,rw
USB0_OTGSC,30,1,DPIE,Data pulse interrupt enable,0,rw
USB0_USBMODE_D,0,2,CM1_0,Controller mode,0,rwo
USB0_USBMODE_D,2,1,ES,Endian select,0,rw
USB0_USBMODE_D,3,1,SLOM,Setup Lockout mode,0,rw
USB0_USBMODE_D,4,1,SDIS,Setup Lockout mode,0,rw
USB0_USBMODE_H,0,2,CM,Controller mode,0,rwo
USB0_USBMODE_H,2,1,ES,Endian select,0,rw
USB0_USBMODE_H,4,1,SDIS,Stream disable mode,0,rw
USB0_USBMODE_H,5,1,VBPS,VBUS power select,0,rwo
USB0_ENDPTSETUPSTAT,0,6,ENDPSETUPSTAT,Setup endpoint status for logical endpoints 0 to 5,0,rwc
USB0_ENDPTPRIME,0,6,PERB,Prime endpoint receive buffer for physical OUT endpoints 5 to 0,0,rws
USB0_ENDPTPRIME,16,6,PETB,Prime endpoint transmit buffer for physical IN endpoints 5 to 0,0,rws
USB0_ENDPTFLUSH,0,6,FERB,Flush endpoint receive buffer for physical OUT endpoints 5 to 0,0,rwc
USB0_ENDPTFLUSH,16,6,FETB,Flush endpoint transmit buffer for physical IN endpoints 5 to 0,0,rwc
USB0_ENDPTSTAT,0,6,ERBR,Endpoint receive buffer ready for physical OUT endpoints 5 to 0,0,r
USB0_ENDPTSTAT,16,6,ETBR,Endpoint transmit buffer ready for physical IN endpoints 3 to 0,0,r
USB0_ENDPTCOMPLETE,0,6,ERCE,Endpoint receive complete event for physical OUT endpoints 5 to 0,0,rwc
USB0_ENDPTCOMPLETE,16,6,ETCE,Endpoint transmit complete event for physical IN endpoints 5 to 0,0,rwc
USB0_ENDPTCTRL0,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL0,2,2,RXT1_0,Endpoint type,0,rw
USB0_ENDPTCTRL0,7,1,RXE,Rx endpoint enable,1,r
USB0_ENDPTCTRL0,16,1,TXS,Tx endpoint stall,,rw
USB0_ENDPTCTRL0,18,2,TXT1_0,Endpoint type,0,r
USB0_ENDPTCTRL0,23,1,TXE,Tx endpoint enable,1,r
USB0_ENDPTCTRL1,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL1,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL1,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL1,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL1,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL1,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL1,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL1,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL1,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL1,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL2,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL2,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL2,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL2,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL2,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL2,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL2,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL2,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL2,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL2,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL3,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL3,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL3,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL3,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL3,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL3,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL3,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL3,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL3,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL3,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL4,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL4,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL4,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL4,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL4,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL4,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL4,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL4,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL4,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL4,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL5,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL5,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL5,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL5,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL5,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL5,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL5,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL5,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL5,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL5,23,1,TXE,Tx endpoint enable,0,r
1 USB0_CAPLENGTH 0 8 CAPLENGTH Indicates offset to add to the register base address at the beginning of the Operational Register 0x40 r
2 USB0_CAPLENGTH 8 16 HCIVERSION BCD encoding of the EHCI revision number supported by this host controller 0x100 r
3 USB0_HCSPARAMS 0 4 N_PORTS Number of downstream ports 0x1 r
4 USB0_HCSPARAMS 4 1 PPC Port Power Control 0x1 r
5 USB0_HCSPARAMS 8 4 N_PCC Number of Ports per Companion Controller 0x0 r
6 USB0_HCSPARAMS 12 4 N_CC Number of Companion Controller 0x0 r
7 USB0_HCSPARAMS 16 1 PI Port indicators 0x1 r
8 USB0_HCSPARAMS 20 4 N_PTT Number of Ports per Transaction Translator 0x0 r
9 USB0_HCSPARAMS 24 4 N_TT Number of Transaction Translators 0x0 r
10 USB0_HCCPARAMS 0 1 ADC 64-bit Addressing Capability 0 r
11 USB0_HCCPARAMS 1 1 PFL Programmable Frame List Flag 1 r
12 USB0_HCCPARAMS 2 1 ASP Asynchronous Schedule Park Capability 1 r
13 USB0_HCCPARAMS 4 4 IST Isochronous Scheduling Threshold 0 r
14 USB0_HCCPARAMS 8 4 EECP EHCI Extended Capabilities Pointer 0 r
15 USB0_DCCPARAMS 0 5 DEN Device Endpoint Number 0x4 r
16 USB0_DCCPARAMS 7 1 DC Device Capable 0x1 r
17 USB0_DCCPARAMS 8 1 HC Host Capable 0x1 r
18 USB0_USBCMD_D 0 1 RS Run/Stop 0 rw
19 USB0_USBCMD_D 1 1 RST Controller reset 0 rw
20 USB0_USBCMD_D 13 1 SUTW Setup trip wire 0 rw
21 USB0_USBCMD_D 14 1 ATDTW Add dTD trip wire 0 rw
22 USB0_USBCMD_D 16 8 ITC Interrupt threshold control 0x8 rw
23 USB0_USBCMD_H 0 1 RS Run/Stop 0 rw
24 USB0_USBCMD_H 1 1 RST Controller reset 0 rw
25 USB0_USBCMD_H 2 1 FS0 Bit 0 of the Frame List Size bits 0
26 USB0_USBCMD_H 3 1 FS1 Bit 1 of the Frame List Size bits 0
27 USB0_USBCMD_H 4 1 PSE This bit controls whether the host controller skips processing the periodic schedule 0 rw
28 USB0_USBCMD_H 5 1 ASE This bit controls whether the host controller skips processing the asynchronous schedule 0 rw
29 USB0_USBCMD_H 6 1 IAA This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule 0 rw
30 USB0_USBCMD_H 8 2 ASP1_0 Asynchronous schedule park mode 0x3 rw
31 USB0_USBCMD_H 11 1 ASPE Asynchronous Schedule Park Mode Enable 1 rw
32 USB0_USBCMD_H 15 1 FS2 Bit 2 of the Frame List Size bits 0
33 USB0_USBCMD_H 16 8 ITC Interrupt threshold control 0x8 rw
34 USB0_USBSTS_D 0 1 UI USB interrupt 0 rwc
35 USB0_USBSTS_D 1 1 UEI USB error interrupt 0 rwc
36 USB0_USBSTS_D 2 1 PCI Port change detect 0 rwc
37 USB0_USBSTS_D 6 1 URI USB reset received 0 rwc
38 USB0_USBSTS_D 7 1 SRI SOF received 0 rwc
39 USB0_USBSTS_D 8 1 SLI DCSuspend 0 rwc
40 USB0_USBSTS_D 16 1 NAKI NAK interrupt bit 0 r
41 USB0_USBSTS_H 0 1 UI USB interrupt 0 rwc
42 USB0_USBSTS_H 1 1 UEI USB error interrupt 0 rwc
43 USB0_USBSTS_H 2 1 PCI Port change detect 0 rwc
44 USB0_USBSTS_H 3 1 FRI Frame list roll-over 0 rwc
45 USB0_USBSTS_H 5 1 AAI Interrupt on async advance 0 rwc
46 USB0_USBSTS_H 7 1 SRI SOF received 0 rwc
47 USB0_USBSTS_H 12 1 HCH HCHalted 1 r
48 USB0_USBSTS_H 13 1 RCL Reclamation 0 r
49 USB0_USBSTS_H 14 1 PS Periodic schedule status 0 r
50 USB0_USBSTS_H 15 1 AS Asynchronous schedule status 0
51 USB0_USBSTS_H 18 1 UAI USB host asynchronous interrupt (USBHSTASYNCINT) 0 rwc
52 USB0_USBSTS_H 19 1 UPI USB host periodic interrupt (USBHSTPERINT) 0 rwc
53 USB0_USBINTR_D 0 1 UE USB interrupt enable 0 rw
54 USB0_USBINTR_D 1 1 UEE USB error interrupt enable 0 rw
55 USB0_USBINTR_D 2 1 PCE Port change detect enable 0 rw
56 USB0_USBINTR_D 6 1 URE USB reset enable 0 rw
57 USB0_USBINTR_D 7 1 SRE SOF received enable 0 rw
58 USB0_USBINTR_D 8 1 SLE Sleep enable 0 rw
59 USB0_USBINTR_D 16 1 NAKE NAK interrupt enable 0 rw
60 USB0_USBINTR_H 0 1 UE USB interrupt enable 0 rw
61 USB0_USBINTR_H 1 1 UEE USB error interrupt enable 0 rw
62 USB0_USBINTR_H 2 1 PCE Port change detect enable 0 rw
63 USB0_USBINTR_H 3 1 FRE Frame list rollover enable 0 rw
64 USB0_USBINTR_H 5 1 AAE Interrupt on asynchronous advance enable 0 rw
65 USB0_USBINTR_H 7 1 SRE SOF received enable 0
66 USB0_USBINTR_H 18 1 UAIE USB host asynchronous interrupt enable 0 rw
67 USB0_USBINTR_H 19 1 UPIA USB host periodic interrupt enable 0 rw
68 USB0_FRINDEX_D 0 3 FRINDEX2_0 Current micro frame number r
69 USB0_FRINDEX_D 3 11 FRINDEX13_3 Current frame number of the last frame transmitted r
70 USB0_FRINDEX_H 0 3 FRINDEX2_0 Current micro frame number rw
71 USB0_FRINDEX_H 3 10 FRINDEX12_3 Frame list current index rw
72 USB0_DEVICEADDR 24 1 USBADRA Device address advance 0
73 USB0_DEVICEADDR 25 7 USBADR USB device address 0 rw
74 USB0_PERIODICLISTBASE 12 20 PERBASE31_12 Base Address (Low) rw
75 USB0_ENDPOINTLISTADDR 11 21 EPBASE31_11 Endpoint list pointer (low) rw
76 USB0_ASYNCLISTADDR 5 27 ASYBASE31_5 Link pointer (Low) LPL rw
77 USB0_TTCTRL 24 7 TTHA Hub address when FS or LS device are connected directly rw
78 USB0_BURSTSIZE 0 8 RXPBURST Programmable RX burst length 0x10 rw
79 USB0_BURSTSIZE 8 8 TXPBURST Programmable TX burst length 0x10 rw
80 USB0_TXFILLTUNING 0 8 TXSCHOH FIFO burst threshold 0x2 rw
81 USB0_TXFILLTUNING 8 5 TXSCHEATLTH Scheduler health counter 0x0 rw
82 USB0_TXFILLTUNING 16 6 TXFIFOTHRES Scheduler overhead 0x0 rw
83 USB0_BINTERVAL 0 4 BINT bInterval value 0x00 rw
84 USB0_ENDPTNAK 0 6 EPRN Rx endpoint NAK 0x00 rwc
85 USB0_ENDPTNAK 16 6 EPTN Tx endpoint NAK 0x00 rwc
86 USB0_ENDPTNAKEN 0 6 EPRNE Rx endpoint NAK enable 0x00 rw
87 USB0_ENDPTNAKEN 16 6 EPTNE Tx endpoint NAK 0x00 rw
88 USB0_PORTSC1_D 0 1 CCS Current connect status 0 r
89 USB0_PORTSC1_D 2 1 PE Port enable 1 r
90 USB0_PORTSC1_D 3 1 PEC Port enable/disable change 0 r
91 USB0_PORTSC1_D 6 1 FPR Force port resume 0 rw
92 USB0_PORTSC1_D 7 1 SUSP Suspend 0 r
93 USB0_PORTSC1_D 8 1 PR Port reset 0 r
94 USB0_PORTSC1_D 9 1 HSP High-speed status 0 r
95 USB0_PORTSC1_D 14 2 PIC1_0 Port indicator control 0 rw
96 USB0_PORTSC1_D 16 4 PTC3_0 Port test control 0 rw
97 USB0_PORTSC1_D 23 1 PHCD PHY low power suspend - clock disable (PLPSCD) 0 rw
98 USB0_PORTSC1_D 24 1 PFSC Port force full speed connect 0 rw
99 USB0_PORTSC1_D 26 2 PSPD Port speed 0 r
100 USB0_PORTSC1_H 0 1 CCS Current connect status 0 rwc
101 USB0_PORTSC1_H 1 1 CSC Connect status change 0 rwc
102 USB0_PORTSC1_H 2 1 PE Port enable 0 rw
103 USB0_PORTSC1_H 3 1 PEC Port disable/enable change 0 rwc
104 USB0_PORTSC1_H 4 1 OCA Over-current active 0 r
105 USB0_PORTSC1_H 5 1 OCC Over-current change 0 rwc
106 USB0_PORTSC1_H 6 1 FPR Force port resume 0 rw
107 USB0_PORTSC1_H 7 1 SUSP Suspend 0 rw
108 USB0_PORTSC1_H 8 1 PR Port reset 0 rw
109 USB0_PORTSC1_H 9 1 HSP High-speed status 0 r
110 USB0_PORTSC1_H 10 2 LS Line status 0x3 r
111 USB0_PORTSC1_H 12 1 PP Port power control 0 rw
112 USB0_PORTSC1_H 14 2 PIC1_0 Port indicator control 0 rw
113 USB0_PORTSC1_H 16 4 PTC3_0 Port test control 0 rw
114 USB0_PORTSC1_H 20 1 WKCN Wake on connect enable (WKCNNT_E) 0 rw
115 USB0_PORTSC1_H 21 1 WKDC Wake on disconnect enable (WKDSCNNT_E) 0 rw
116 USB0_PORTSC1_H 22 1 WKOC Wake on over-current enable (WKOC_E) 0 rw
117 USB0_PORTSC1_H 23 1 PHCD PHY low power suspend - clock disable (PLPSCD) 0 rw
118 USB0_PORTSC1_H 24 1 PFSC Port force full speed connect 0 rw
119 USB0_PORTSC1_H 26 2 PSPD Port speed 0 r
120 USB0_OTGSC 0 1 VD VBUS_Discharge 0 rw
121 USB0_OTGSC 1 1 VC VBUS_Charge 0 rw
122 USB0_OTGSC 2 1 HAAR Hardware assist auto_reset 0 rw
123 USB0_OTGSC 3 1 OT OTG termination 0 rw
124 USB0_OTGSC 4 1 DP Data pulsing 0 rw
125 USB0_OTGSC 5 1 IDPU ID pull-up 1 rw
126 USB0_OTGSC 6 1 HADP Hardware assist data pulse 0 rw
127 USB0_OTGSC 7 1 HABA Hardware assist B-disconnect to A-connect 0 rw
128 USB0_OTGSC 8 1 ID USB ID 0 r
129 USB0_OTGSC 9 1 AVV A-VBUS valid 0 r
130 USB0_OTGSC 10 1 ASV A-session valid 0 r
131 USB0_OTGSC 11 1 BSV B-session valid 0 r
132 USB0_OTGSC 12 1 BSE B-session end 0 r
133 USB0_OTGSC 13 1 MS1T 1 millisecond timer toggle 0 r
134 USB0_OTGSC 14 1 DPS Data bus pulsing status 0 r
135 USB0_OTGSC 16 1 IDIS USB ID interrupt status 0 rwc
136 USB0_OTGSC 17 1 AVVIS A-VBUS valid interrupt status 0 rwc
137 USB0_OTGSC 18 1 ASVIS A-Session valid interrupt status 0 rwc
138 USB0_OTGSC 19 1 BSVIS B-Session valid interrupt status 0 rwc
139 USB0_OTGSC 20 1 BSEIS B-Session end interrupt status 0 rwc
140 USB0_OTGSC 21 1 MS1S 1 millisecond timer interrupt status 0 rwc
141 USB0_OTGSC 22 1 DPIS Data pulse interrupt status 0 rwc
142 USB0_OTGSC 24 1 IDIE USB ID interrupt enable 0 rw
143 USB0_OTGSC 25 1 AVVIE A-VBUS valid interrupt enable 0 rw
144 USB0_OTGSC 26 1 ASVIE A-session valid interrupt enable 0 rw
145 USB0_OTGSC 27 1 BSVIE B-session valid interrupt enable 0 rw
146 USB0_OTGSC 28 1 BSEIE B-session end interrupt enable 0 rw
147 USB0_OTGSC 29 1 MS1E 1 millisecond timer interrupt enable 0 rw
148 USB0_OTGSC 30 1 DPIE Data pulse interrupt enable 0 rw
149 USB0_USBMODE_D 0 2 CM1_0 Controller mode 0 rwo
150 USB0_USBMODE_D 2 1 ES Endian select 0 rw
151 USB0_USBMODE_D 3 1 SLOM Setup Lockout mode 0 rw
152 USB0_USBMODE_D 4 1 SDIS Setup Lockout mode 0 rw
153 USB0_USBMODE_H 0 2 CM Controller mode 0 rwo
154 USB0_USBMODE_H 2 1 ES Endian select 0 rw
155 USB0_USBMODE_H 4 1 SDIS Stream disable mode 0 rw
156 USB0_USBMODE_H 5 1 VBPS VBUS power select 0 rwo
157 USB0_ENDPTSETUPSTAT 0 6 ENDPSETUPSTAT Setup endpoint status for logical endpoints 0 to 5 0 rwc
158 USB0_ENDPTPRIME 0 6 PERB Prime endpoint receive buffer for physical OUT endpoints 5 to 0 0 rws
159 USB0_ENDPTPRIME 16 6 PETB Prime endpoint transmit buffer for physical IN endpoints 5 to 0 0 rws
160 USB0_ENDPTFLUSH 0 6 FERB Flush endpoint receive buffer for physical OUT endpoints 5 to 0 0 rwc
161 USB0_ENDPTFLUSH 16 6 FETB Flush endpoint transmit buffer for physical IN endpoints 5 to 0 0 rwc
162 USB0_ENDPTSTAT 0 6 ERBR Endpoint receive buffer ready for physical OUT endpoints 5 to 0 0 r
163 USB0_ENDPTSTAT 16 6 ETBR Endpoint transmit buffer ready for physical IN endpoints 3 to 0 0 r
164 USB0_ENDPTCOMPLETE 0 6 ERCE Endpoint receive complete event for physical OUT endpoints 5 to 0 0 rwc
165 USB0_ENDPTCOMPLETE 16 6 ETCE Endpoint transmit complete event for physical IN endpoints 5 to 0 0 rwc
166 USB0_ENDPTCTRL0 0 1 RXS Rx endpoint stall 0 rw
167 USB0_ENDPTCTRL0 2 2 RXT1_0 Endpoint type 0 rw
168 USB0_ENDPTCTRL0 7 1 RXE Rx endpoint enable 1 r
169 USB0_ENDPTCTRL0 16 1 TXS Tx endpoint stall rw
170 USB0_ENDPTCTRL0 18 2 TXT1_0 Endpoint type 0 r
171 USB0_ENDPTCTRL0 23 1 TXE Tx endpoint enable 1 r
172 USB0_ENDPTCTRL1 0 1 RXS Rx endpoint stall 0 rw
173 USB0_ENDPTCTRL1 2 2 RXT Endpoint type 0 rw
174 USB0_ENDPTCTRL1 5 1 RXI Rx data toggle inhibit 0 rw
175 USB0_ENDPTCTRL1 6 1 RXR Rx data toggle reset 0 ws
176 USB0_ENDPTCTRL1 7 1 RXE Rx endpoint enable 0 rw
177 USB0_ENDPTCTRL1 16 1 TXS Tx endpoint stall 0 rw
178 USB0_ENDPTCTRL1 18 2 TXT1_0 Tx Endpoint type 0 r
179 USB0_ENDPTCTRL1 21 1 TXI Tx data toggle inhibit 0 rw
180 USB0_ENDPTCTRL1 22 1 TXR Tx data toggle reset 1 ws
181 USB0_ENDPTCTRL1 23 1 TXE Tx endpoint enable 0 r
182 USB0_ENDPTCTRL2 0 1 RXS Rx endpoint stall 0 rw
183 USB0_ENDPTCTRL2 2 2 RXT Endpoint type 0 rw
184 USB0_ENDPTCTRL2 5 1 RXI Rx data toggle inhibit 0 rw
185 USB0_ENDPTCTRL2 6 1 RXR Rx data toggle reset 0 ws
186 USB0_ENDPTCTRL2 7 1 RXE Rx endpoint enable 0 rw
187 USB0_ENDPTCTRL2 16 1 TXS Tx endpoint stall 0 rw
188 USB0_ENDPTCTRL2 18 2 TXT1_0 Tx Endpoint type 0 r
189 USB0_ENDPTCTRL2 21 1 TXI Tx data toggle inhibit 0 rw
190 USB0_ENDPTCTRL2 22 1 TXR Tx data toggle reset 1 ws
191 USB0_ENDPTCTRL2 23 1 TXE Tx endpoint enable 0 r
192 USB0_ENDPTCTRL3 0 1 RXS Rx endpoint stall 0 rw
193 USB0_ENDPTCTRL3 2 2 RXT Endpoint type 0 rw
194 USB0_ENDPTCTRL3 5 1 RXI Rx data toggle inhibit 0 rw
195 USB0_ENDPTCTRL3 6 1 RXR Rx data toggle reset 0 ws
196 USB0_ENDPTCTRL3 7 1 RXE Rx endpoint enable 0 rw
197 USB0_ENDPTCTRL3 16 1 TXS Tx endpoint stall 0 rw
198 USB0_ENDPTCTRL3 18 2 TXT1_0 Tx Endpoint type 0 r
199 USB0_ENDPTCTRL3 21 1 TXI Tx data toggle inhibit 0 rw
200 USB0_ENDPTCTRL3 22 1 TXR Tx data toggle reset 1 ws
201 USB0_ENDPTCTRL3 23 1 TXE Tx endpoint enable 0 r
202 USB0_ENDPTCTRL4 0 1 RXS Rx endpoint stall 0 rw
203 USB0_ENDPTCTRL4 2 2 RXT Endpoint type 0 rw
204 USB0_ENDPTCTRL4 5 1 RXI Rx data toggle inhibit 0 rw
205 USB0_ENDPTCTRL4 6 1 RXR Rx data toggle reset 0 ws
206 USB0_ENDPTCTRL4 7 1 RXE Rx endpoint enable 0 rw
207 USB0_ENDPTCTRL4 16 1 TXS Tx endpoint stall 0 rw
208 USB0_ENDPTCTRL4 18 2 TXT1_0 Tx Endpoint type 0 r
209 USB0_ENDPTCTRL4 21 1 TXI Tx data toggle inhibit 0 rw
210 USB0_ENDPTCTRL4 22 1 TXR Tx data toggle reset 1 ws
211 USB0_ENDPTCTRL4 23 1 TXE Tx endpoint enable 0 r
212 USB0_ENDPTCTRL5 0 1 RXS Rx endpoint stall 0 rw
213 USB0_ENDPTCTRL5 2 2 RXT Endpoint type 0 rw
214 USB0_ENDPTCTRL5 5 1 RXI Rx data toggle inhibit 0 rw
215 USB0_ENDPTCTRL5 6 1 RXR Rx data toggle reset 0 ws
216 USB0_ENDPTCTRL5 7 1 RXE Rx endpoint enable 0 rw
217 USB0_ENDPTCTRL5 16 1 TXS Tx endpoint stall 0 rw
218 USB0_ENDPTCTRL5 18 2 TXT1_0 Tx Endpoint type 0 r
219 USB0_ENDPTCTRL5 21 1 TXI Tx data toggle inhibit 0 rw
220 USB0_ENDPTCTRL5 22 1 TXR Tx data toggle reset 1 ws
221 USB0_ENDPTCTRL5 23 1 TXE Tx endpoint enable 0 r