stm32f3: rcc: add hse preconfigurations
Just a single 8Mhz in, 72mhz (max) out, which suits the f3 discovery boards for instance.
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@ -413,11 +413,16 @@ extern uint32_t rcc_apb2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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enum rcc_clock {
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RCC_CLOCK_48MHZ,
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RCC_CLOCK_64MHZ,
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RCC_CLOCK_END
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enum rcc_clock_hsi {
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RCC_CLOCK_HSI_48MHZ,
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RCC_CLOCK_HSI_64MHZ, /* Max from HSI */
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RCC_CLOCK_HSI_END
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};
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enum rcc_clock_hse8 {
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RCC_CLOCK_HSE8_72MHZ,
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RCC_CLOCK_HSE8_END
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};
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struct rcc_clock_scale {
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uint8_t pllsrc;
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@ -434,7 +439,8 @@ struct rcc_clock_scale {
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uint32_t apb2_frequency;
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};
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extern const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END];
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extern const struct rcc_clock_scale rcc_configs[RCC_CLOCK_HSI_END];
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extern const struct rcc_clock_scale rcc_hse8mhz_configs[RCC_CLOCK_HSE8_END];
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enum rcc_osc {
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RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI
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@ -44,7 +44,7 @@ uint32_t rcc_ahb_frequency = 8000000;
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uint32_t rcc_apb1_frequency = 8000000;
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uint32_t rcc_apb2_frequency = 8000000;
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const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
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const struct rcc_clock_scale rcc_hsi_configs[] = {
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{ /* 48MHz */
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.pllmul = RCC_CFGR_PLLMUL_MUL12,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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@ -69,6 +69,22 @@ const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
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}
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};
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const struct rcc_clock_scale rcc_hse8mhz_configs[] = {
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{
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.pllsrc = RCC_CFGR_PLLSRC_HSE_PREDIV,
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.pllmul = RCC_CFGR_PLLMUL_MUL9,
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.plldiv = RCC_CFGR2_PREDIV_NODIV,
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.usbdiv1 = false,
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.flash_waitstates = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.ahb_frequency = 72e6,
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.apb1_frequency = 32e6,
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.apb2_frequency = 72e6,
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}
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};
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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