[Stylecheck] Correct style in the CM3 addition
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BuFran
Piotr Esden-Tempski
parent
8e96592f55
commit
aa9b94ee1d
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@ -1,77 +1,77 @@
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/** @defgroup CM3_cortex_defines Cortex Core Defines
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*
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* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
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*
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* @ingroup CM3_defines
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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/** @defgroup CM3_cortex_defines Cortex Core Defines
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*
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* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
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*
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* @ingroup CM3_defines
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CORTEX_H
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CORTEX_H
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#define LIBOPENCM3_CORTEX_H
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/**@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Enable interrupts
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*
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* Disable the interrupt mask and enable interrupts globally
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*/
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static inline void cm_enable_interrupts(void)
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{
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__asm__("CPSIE I\n");
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}
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*/
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static inline void cm_enable_interrupts(void)
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{
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__asm__("CPSIE I\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Disable interrupts
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*
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* Mask all interrupts globally
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*/
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static inline void cm_disable_interrupts(void)
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{
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__asm__("CPSID I\n");
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*/
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static inline void cm_disable_interrupts(void)
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{
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__asm__("CPSID I\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Enable faults
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*
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* Disable the HardFault mask and enable fault interrupt globally
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*/
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static inline void cm_enable_faults(void)
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{
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__asm__("CPSIE F\n");
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}
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*/
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static inline void cm_enable_faults(void)
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{
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__asm__("CPSIE F\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Disable faults
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*
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* Mask the HardFault interrupt globally
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*/
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static inline void cm_disable_faults(void)
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{
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__asm__("CPSID F\n");
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}
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*/
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static inline void cm_disable_faults(void)
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{
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__asm__("CPSID F\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Check if interrupts are masked
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@ -79,13 +79,13 @@ static inline void cm_disable_faults(void)
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* Checks, if interrupts are masked (disabled).
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*
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* @returns true, if interrupts are disabled.
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*/
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__attribute__(( always_inline ))
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static inline bool cm_is_masked_interrupts(void)
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{
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register uint32_t result;
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__asm__ ("MRS %0, PRIMASK" : "=r" (result) );
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return (result);
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*/
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__attribute__((always_inline))
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static inline bool cm_is_masked_interrupts(void)
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{
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register uint32_t result;
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__asm__ ("MRS %0, PRIMASK" : "=r" (result));
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return result;
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}
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/*---------------------------------------------------------------------------*/
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@ -95,12 +95,12 @@ static inline bool cm_is_masked_interrupts(void)
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*
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* @returns bool true, if HardFault interrupt is disabled.
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*/
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__attribute__(( always_inline ))
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static inline bool cm_is_masked_faults(void)
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{
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register uint32_t result;
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__asm__ ("MRS %0, FAULTMASK" : "=r" (result) );
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return (result);
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__attribute__((always_inline))
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static inline bool cm_is_masked_faults(void)
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{
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register uint32_t result;
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__asm__ ("MRS %0, FAULTMASK" : "=r" (result));
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return result;
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}
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/*---------------------------------------------------------------------------*/
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@ -112,16 +112,16 @@ static inline bool cm_is_masked_faults(void)
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*
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* @param[in] mask bool New state of the interrupt mask
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* @returns bool old state of the interrupt mask
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*/
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__attribute__(( always_inline ))
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static inline bool cm_mask_interrupts(bool mask)
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{
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register bool old;
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*/
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__attribute__((always_inline))
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static inline bool cm_mask_interrupts(bool mask)
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{
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register bool old;
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__asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
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__asm__ __volatile__("" ::: "memory");
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__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
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return old;
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}
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__asm__ __volatile__("" : : : "memory");
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__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
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return old;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Mask HardFault interrupt
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@ -133,23 +133,23 @@ static inline bool cm_mask_interrupts(bool mask)
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* @param[in] mask bool New state of the HardFault interrupt mask
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* @returns bool old state of the HardFault interrupt mask
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*/
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__attribute__(( always_inline ))
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static inline bool cm_mask_faults(bool mask)
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{
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register bool old;
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__attribute__((always_inline))
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static inline bool cm_mask_faults(bool mask)
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{
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register bool old;
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__asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
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__asm__ __volatile__ ("" ::: "memory");
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__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
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return old;
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__asm__ __volatile__ ("" : : : "memory");
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__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
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return old;
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}
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/**@}*/
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/*===========================================================================*/
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/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
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*
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* @brief Atomic operation support
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*
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/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
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*
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* @brief Atomic operation support
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*
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* @ingroup CM3_cortex_defines
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*/
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/**@{*/
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@ -214,7 +214,7 @@ static inline bool __cm_atomic_set(bool* val)
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#define CM_ATOMIC_BLOCK()
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#else /* defined(__DOXYGEN__) */
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#define CM_ATOMIC_BLOCK() \
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for (bool ___CM_SAVER(true), __My = true; __My; __My = false)
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for (bool ___CM_SAVER(true), __my = true; __my; __my = false)
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#endif /* defined(__DOXYGEN__) */
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/*---------------------------------------------------------------------------*/
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@ -241,7 +241,7 @@ static inline bool __cm_atomic_set(bool* val)
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* ...
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*
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* for (int i=0;i < 100; i++) {
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* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
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* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
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* value += 100; // access value as atomic
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* if ((value % 16) == 0) {
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* break; // restore interrupts and break cycle
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@ -258,7 +258,7 @@ static inline bool __cm_atomic_set(bool* val)
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*
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* uint64_t getnextval(void)
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* {
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* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
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* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
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* value = value + 3; // do long atomic operation
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* return value; // interrupts is restored automatically
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* }
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@ -268,10 +268,10 @@ static inline bool __cm_atomic_set(bool* val)
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#define CM_ATOMIC_CONTEXT()
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#else /* defined(__DOXYGEN__) */
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#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true)
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#endif /* defined(__DOXYGEN__) */
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#endif /* defined(__DOXYGEN__) */
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/**@}*/
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#endif
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#endif
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