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[Style] Global style fix run.

This commit is contained in:
Piotr Esden-Tempski 2014-01-03 01:07:30 +01:00
parent 67efedec54
commit a909b5ca9e
25 changed files with 920 additions and 915 deletions
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13
include/libopencm3/cm3/cortex.h
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@ -156,14 +156,17 @@ static inline bool cm_mask_faults(bool mask)
#if !defined(__DOXYGEN__)
/* Do not populate this definition outside */
static inline bool __cm_atomic_set(bool* val)
static inline bool __cm_atomic_set(bool *val)
{
return cm_mask_interrupts(*val);
}
#define __CM_SAVER(state) __val = state, \
#define __CM_SAVER(state) \
do { \
__val = state, \
__save __attribute__((__cleanup__(__cm_atomic_set))) = \
__cm_atomic_set(&__val)
__cm_atomic_set(&__val); \
} while (0)
#endif /* !defined(__DOXYGEN) */
@ -214,7 +217,9 @@ static inline bool __cm_atomic_set(bool* val)
#define CM_ATOMIC_BLOCK()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_BLOCK() \
for (bool ___CM_SAVER(true), __my = true; __my; __my = false)
do { \
for (bool ___CM_SAVER(true), __my = true; __my; __my = false); \
} while (0)
#endif /* defined(__DOXYGEN__) */
/*---------------------------------------------------------------------------*/

2
include/libopencm3/cm3/sync.h
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@ -32,7 +32,7 @@ void __dmb(void);
/* --- Exclusive load and store instructions ------------------------------- */
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
uint32_t __ldrex(volatile uint32_t *addr);
uint32_t __strex(uint32_t val, volatile uint32_t *addr);

1
include/libopencm3/ethernet/mac_stm32fxx7.h
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@ -749,5 +749,4 @@ END_DECLS
/**@}*/
#endif

2
include/libopencm3/lpc43xx/sgpio.h
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@ -684,7 +684,7 @@ typedef struct {
} sgpio_t;
/* Global access to SGPIO structure */
#define SGPIO ((sgpio_t*)SGPIO_PORT_BASE)
#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE)
/**@}*/

2
include/libopencm3/stm32/f1/adc.h
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@ -622,7 +622,7 @@ injected channels.
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */

2
include/libopencm3/stm32/f3/adc.h
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@ -628,7 +628,7 @@
#define ADC_JSQR_JSQ2_LSB 14
#define ADC_JSQR_JSQ1_LSB 8
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 6 + 8))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */

2
include/libopencm3/stm32/f4/adc.h
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@ -587,7 +587,7 @@ injected channels.
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */

2
lib/cm3/nvic.c
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@ -164,7 +164,7 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority)
}
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Active Interrupt
*

4
lib/cm3/scb.c
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@ -22,7 +22,7 @@
#include <libopencm3/cm3/scb.h>
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void scb_reset_core(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
@ -39,7 +39,7 @@ void scb_reset_system(void)
}
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void scb_set_priority_grouping(uint32_t prigroup)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;

4
lib/cm3/vector.c
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@ -44,7 +44,7 @@ vector_table_t vector_table = {
.hard_fault = hard_fault_handler,
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
.memory_manage_fault = mem_manage_handler,
.bus_fault = bus_fault_handler,
.usage_fault = usage_fault_handler,
@ -112,7 +112,7 @@ void null_handler(void)
#pragma weak sys_tick_handler = null_handler
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#pragma weak mem_manage_handler = blocking_handler
#pragma weak bus_fault_handler = blocking_handler
#pragma weak usage_fault_handler = blocking_handler

3
lib/stm32/common/rcc_common_all.c
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@ -93,7 +93,8 @@ void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
*
* @param[in] *reg Unsigned int32. Pointer to a Reset Register
* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed:
* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be
* removed:
* @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
* @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
* @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst

2
lib/stm32/f0/adc.c
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@ -788,7 +788,7 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan)
{
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | \
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) |
ADC_CFGR1_AWDCH_VAL(chan);
ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL;

2
lib/stm32/f0/rcc.c
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@ -250,7 +250,7 @@ void rcc_osc_on(enum rcc_osc osc)
RCC_CSR |= RCC_CSR_LSION;
break;
case PLL:
RCC_CR|=RCC_CR_PLLON;
RCC_CR |= RCC_CR_PLLON;
break;
}
}