usb: stm32fx07 -> usb_dwc_common

The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips.
Rename the files to make this more clear, and easier to use in other
targets.
This commit is contained in:
Sebastian Holzapfel 2018-02-13 08:33:03 +11:00 committed by Karl Palsson
parent 3c855e75d1
commit a2ee90fbfe
10 changed files with 86 additions and 71 deletions

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@ -19,12 +19,12 @@
/*
* This file is intended to be included by either otg_hs.h or otg_fs.h
* Contains common definitions of Command and Status Registers (CSR) and their
* bit definitions.
* It contains register definitions common to chips using DesignWare
* USB OTG controllers, including STM32 and EFM32
*/
#ifndef LIBOPENCM3_OTG_COMMON_H
#define LIBOPENCM3_OTG_COMMON_H
#ifndef LIBOPENCM3_USB_DWC_OTG_COMMON_H
#define LIBOPENCM3_USB_DWC_OTG_COMMON_H
/* Core Global Control and Status Registers */
#define OTG_GOTGCTL 0x000

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@ -18,16 +18,23 @@
*/
/*
* This file covers definitions for the USB OTG FS peripheral.
* This is the USB core included in the F105, F107, F2, F4 devices
* This file covers definitions for DesignWare USB OTG HS peripherals.
*/
#ifndef LIBOPENCM3_OTG_FS_H
#define LIBOPENCM3_OTG_FS_H
#ifndef LIBOPENCM3_USB_DWC_OTG_FS_H
#define LIBOPENCM3_USB_DWC_OTG_FS_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/otg_common.h>
#include <libopencm3/usb/dwc/otg_common.h>
/* Memory map is required for USB_OTG_FS_BASE address */
#if defined(STM32F1) || defined(STM32F2) || defined(STM32F4)
# include <libopencm3/stm32/memorymap.h>
#elif defined(EFM32HG)
# include <libopencm3/efm32/memorymap.h>
#else
# error "device family not supported by dwc/otg_fs."
#endif
/***********************************************************************/

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@ -17,12 +17,22 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_OTG_HS_H
#define LIBOPENCM3_OTG_HS_H
/*
* This file covers definitions for DesignWare USB OTG HS peripherals.
*/
#ifndef LIBOPENCM3_USB_DWC_OTG_HS_H
#define LIBOPENCM3_USB_DWC_OTG_HS_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/otg_common.h>
#include <libopencm3/usb/dwc/otg_common.h>
/* Memory map is required for USB_OTG_HS_BASE address */
#if defined(STM32F2) || defined(STM32F4)
# include <libopencm3/stm32/memorymap.h>
#else
# error "device family not supported by dwc/otg_hs."
#endif
/* OTG_HS specific registers */

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@ -48,7 +48,7 @@ OBJS += crc_common_all.o dac_common_all.o dma_common_l1f013.o \
flash_common_f01.o
OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
OBJS += usb_fx07_common.o usb_f107.o
OBJS += usb_dwc_common.o usb_f107.o
OBJS += st_usbfs_core.o st_usbfs_v1.o
VPATH += ../../usb:../:../../cm3:../common:../../ethernet

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@ -47,7 +47,7 @@ OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
crypto_common_f24.o exti_common_all.o rcc_common_all.o
OBJS += rng_common_v1.o
OBJS += usb.o usb_standard.o usb_control.o usb_fx07_common.o \
OBJS += usb.o usb_standard.o usb_control.o usb_dwc_common.o \
usb_f107.o usb_f207.o usb_msc.o
VPATH += ../../usb:../:../../cm3:../common

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@ -52,7 +52,7 @@ OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
rcc_common_all.o
OBJS += rng_common_v1.o
OBJS += usb.o usb_standard.o usb_control.o usb_fx07_common.o \
OBJS += usb.o usb_standard.o usb_control.o usb_dwc_common.o \
usb_f107.o usb_f207.o usb_msc.o
OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz8051mll.o fmc.o

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@ -19,12 +19,10 @@
#include <string.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/tools.h>
#include <libopencm3/stm32/otg_fs.h>
#include <libopencm3/stm32/otg_hs.h>
#include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/dwc/otg_common.h>
#include "usb_private.h"
#include "usb_fx07_common.h"
#include "usb_dwc_common.h"
/* The FS core and the HS core have the same register layout.
* As the code can be used on both cores, the registers offset is modified
@ -32,12 +30,12 @@
#define dev_base_address (usbd_dev->driver->base_address)
#define REBASE(x) MMIO32((x) + (dev_base_address))
void stm32fx07_set_address(usbd_device *usbd_dev, uint8_t addr)
void dwc_set_address(usbd_device *usbd_dev, uint8_t addr)
{
REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_DCFG_DAD) | (addr << 4);
}
void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
void dwc_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
uint16_t max_size,
void (*callback) (usbd_device *usbd_dev, uint8_t ep))
{
@ -114,7 +112,7 @@ void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
}
}
void stm32fx07_endpoints_reset(usbd_device *usbd_dev)
void dwc_endpoints_reset(usbd_device *usbd_dev)
{
int i;
/* The core resets the endpoints automatically on reset. */
@ -135,7 +133,7 @@ void stm32fx07_endpoints_reset(usbd_device *usbd_dev)
| OTG_GRSTCTL_RXFFLSH;
}
void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
void dwc_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
{
if (addr == 0) {
if (stall) {
@ -164,7 +162,7 @@ void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
}
}
uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
uint8_t dwc_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
{
/* Return non-zero if STALL set. */
if (addr & 0x80) {
@ -176,7 +174,7 @@ uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
}
}
void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
void dwc_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
{
/* It does not make sense to force NAK on IN endpoints. */
if (addr & 0x80) {
@ -192,7 +190,7 @@ void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
}
}
uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
uint16_t dwc_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len)
{
const uint32_t *buf32 = buf;
@ -218,7 +216,7 @@ uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
return len;
}
uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
uint16_t dwc_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
void *buf, uint16_t len)
{
int i;
@ -251,7 +249,7 @@ uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
return len;
}
static void stm32fx07_flush_txfifo(usbd_device *usbd_dev, int ep)
static void dwc_flush_txfifo(usbd_device *usbd_dev, int ep)
{
uint32_t fifo;
/* set IN endpoint NAK */
@ -275,7 +273,7 @@ static void stm32fx07_flush_txfifo(usbd_device *usbd_dev, int ep)
}
}
void stm32fx07_poll(usbd_device *usbd_dev)
void dwc_poll(usbd_device *usbd_dev)
{
/* Read interrupt status register. */
uint32_t intsts = REBASE(OTG_GINTSTS);
@ -338,10 +336,10 @@ void stm32fx07_poll(usbd_device *usbd_dev)
/* SETUP received but there is still something stuck
* in the transmit fifo. Flush it.
*/
stm32fx07_flush_txfifo(usbd_dev, ep);
dwc_flush_txfifo(usbd_dev, ep);
}
/* Save packet size for stm32f107_ep_read_packet(). */
/* Save packet size for dwc_ep_read_packet(). */
usbd_dev->rxbcnt = (rxstsp & OTG_GRXSTSP_BCNT_MASK) >> 4;
if (usbd_dev->user_callback_ctr[ep][type]) {
@ -385,7 +383,7 @@ void stm32fx07_poll(usbd_device *usbd_dev)
}
}
void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected)
void dwc_disconnect(usbd_device *usbd_dev, bool disconnected)
{
if (disconnected) {
REBASE(OTG_DCTL) |= OTG_DCTL_SDIS;

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@ -17,23 +17,23 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __USB_FX07_COMMON_H_
#define __USB_FX07_COMMON_H_
#ifndef __USB_DWC_COMMON_H_
#define __USB_DWC_COMMON_H_
void stm32fx07_set_address(usbd_device *usbd_dev, uint8_t addr);
void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
void dwc_set_address(usbd_device *usbd_dev, uint8_t addr);
void dwc_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
uint16_t max_size,
void (*callback)(usbd_device *usbd_dev, uint8_t ep));
void stm32fx07_endpoints_reset(usbd_device *usbd_dev);
void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
void dwc_endpoints_reset(usbd_device *usbd_dev);
void dwc_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
uint8_t dwc_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
void dwc_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
uint16_t dwc_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len);
uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
uint16_t dwc_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
void *buf, uint16_t len);
void stm32fx07_poll(usbd_device *usbd_dev);
void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected);
void dwc_poll(usbd_device *usbd_dev);
void dwc_disconnect(usbd_device *usbd_dev, bool disconnected);
#endif /* __USB_FX07_COMMON_H_ */
#endif /* __USB_DWC_COMMON_H_ */

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@ -20,11 +20,11 @@
#include <string.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/tools.h>
#include <libopencm3/stm32/otg_fs.h>
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/dwc/otg_fs.h>
#include "usb_private.h"
#include "usb_fx07_common.h"
#include "usb_dwc_common.h"
/* Receive FIFO size in 32-bit words. */
#define RX_FIFO_SIZE 128
@ -35,16 +35,16 @@ static struct _usbd_device usbd_dev;
const struct _usbd_driver stm32f107_usb_driver = {
.init = stm32f107_usbd_init,
.set_address = stm32fx07_set_address,
.ep_setup = stm32fx07_ep_setup,
.ep_reset = stm32fx07_endpoints_reset,
.ep_stall_set = stm32fx07_ep_stall_set,
.ep_stall_get = stm32fx07_ep_stall_get,
.ep_nak_set = stm32fx07_ep_nak_set,
.ep_write_packet = stm32fx07_ep_write_packet,
.ep_read_packet = stm32fx07_ep_read_packet,
.poll = stm32fx07_poll,
.disconnect = stm32fx07_disconnect,
.set_address = dwc_set_address,
.ep_setup = dwc_ep_setup,
.ep_reset = dwc_endpoints_reset,
.ep_stall_set = dwc_ep_stall_set,
.ep_stall_get = dwc_ep_stall_get,
.ep_nak_set = dwc_ep_nak_set,
.ep_write_packet = dwc_ep_write_packet,
.ep_read_packet = dwc_ep_read_packet,
.poll = dwc_poll,
.disconnect = dwc_disconnect,
.base_address = USB_OTG_FS_BASE,
.set_address_before_status = 1,
.rx_fifo_size = RX_FIFO_SIZE,

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@ -20,11 +20,11 @@
#include <string.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/tools.h>
#include <libopencm3/stm32/otg_hs.h>
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/dwc/otg_hs.h>
#include "usb_private.h"
#include "usb_fx07_common.h"
#include "usb_dwc_common.h"
/* Receive FIFO size in 32-bit words. */
#define RX_FIFO_SIZE 512
@ -35,16 +35,16 @@ static struct _usbd_device usbd_dev;
const struct _usbd_driver stm32f207_usb_driver = {
.init = stm32f207_usbd_init,
.set_address = stm32fx07_set_address,
.ep_setup = stm32fx07_ep_setup,
.ep_reset = stm32fx07_endpoints_reset,
.ep_stall_set = stm32fx07_ep_stall_set,
.ep_stall_get = stm32fx07_ep_stall_get,
.ep_nak_set = stm32fx07_ep_nak_set,
.ep_write_packet = stm32fx07_ep_write_packet,
.ep_read_packet = stm32fx07_ep_read_packet,
.poll = stm32fx07_poll,
.disconnect = stm32fx07_disconnect,
.set_address = dwc_set_address,
.ep_setup = dwc_ep_setup,
.ep_reset = dwc_endpoints_reset,
.ep_stall_set = dwc_ep_stall_set,
.ep_stall_get = dwc_ep_stall_get,
.ep_nak_set = dwc_ep_nak_set,
.ep_write_packet = dwc_ep_write_packet,
.ep_read_packet = dwc_ep_read_packet,
.poll = dwc_poll,
.disconnect = dwc_disconnect,
.base_address = USB_OTG_HS_BASE,
.set_address_before_status = 1,
.rx_fifo_size = RX_FIFO_SIZE,