stm32: adc: standardize special channel names
At least temp sensor, vrefint and vbat/vlcd should have consistent names and consistent doxygen. Dropped channel definitions that are the same as the raw number.
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@ -249,25 +249,9 @@
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* @ingroup adc_defines
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* @ingroup adc_defines
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*
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*
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*@{*/
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*@{*/
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#define ADC_CHANNEL0 0x00
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#define ADC_CHANNEL_TEMP 16
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#define ADC_CHANNEL1 0x01
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#define ADC_CHANNEL_VREF 17
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#define ADC_CHANNEL2 0x02
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#define ADC_CHANNEL_VBAT 18
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#define ADC_CHANNEL3 0x03
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#define ADC_CHANNEL4 0x04
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#define ADC_CHANNEL5 0x05
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#define ADC_CHANNEL6 0x06
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#define ADC_CHANNEL7 0x07
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#define ADC_CHANNEL8 0x08
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#define ADC_CHANNEL9 0x09
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#define ADC_CHANNEL10 0x0A
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#define ADC_CHANNEL11 0x0B
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#define ADC_CHANNEL12 0x0C
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#define ADC_CHANNEL13 0x0D
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#define ADC_CHANNEL14 0x0E
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#define ADC_CHANNEL15 0x0F
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#define ADC_CHANNEL_TEMP 0x10
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#define ADC_CHANNEL_VREF 0x11
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#define ADC_CHANNEL_VBAT 0x12
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/**@}*/
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/**@}*/
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/** @defgroup adc_api_opmode ADC Operation Modes
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/** @defgroup adc_api_opmode ADC Operation Modes
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@ -75,10 +75,6 @@ LGPL License Terms @ref lgpl_license
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/* ADC regular data register (ADC_DR) */
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/* ADC regular data register (ADC_DR) */
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#define ADC_DR(block) MMIO32((block) + 0x4c)
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#define ADC_DR(block) MMIO32((block) + 0x4c)
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/* --- ADC Channels ------------------------------------------------------- */
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#define ADC_CHANNEL_TEMP ADC_CHANNEL16
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#define ADC_CHANNEL_VREFINT ADC_CHANNEL17
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/* --- ADC_CR1 values ------------------------------------------------------ */
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/* --- ADC_CR1 values ------------------------------------------------------ */
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@ -397,6 +393,14 @@ and ADC2
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#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
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#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
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/* ADC1 only (dual mode) */
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/* ADC1 only (dual mode) */
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_CHANNEL_TEMP 16
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#define ADC_CHANNEL_VREF 17
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/**@}*/
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/* --- Function prototypes ------------------------------------------------- */
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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BEGIN_DECLS
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@ -865,6 +865,14 @@
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/* Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. */
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/* Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. */
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_CHANNEL_TEMP 16
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#define ADC_CHANNEL_VBAT 17
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#define ADC_CHANNEL_VREF 18
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/**@}*/
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BEGIN_DECLS
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BEGIN_DECLS
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@ -84,11 +84,15 @@ LGPL License Terms @ref lgpl_license
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/* --- ADC Channels ------------------------------------------------------- */
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/* --- ADC Channels ------------------------------------------------------- */
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/* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18! */
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/** @defgroup adc_channel ADC Channel Numbers
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#define ADC_CHANNEL_TEMP_F40 ADC_CHANNEL16
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* @ingroup adc_defines
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#define ADC_CHANNEL_TEMP_F42 ADC_CHANNEL18
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* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18!
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#define ADC_CHANNEL_VREFINT ADC_CHANNEL17
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*@{*/
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#define ADC_CHANNEL_VBAT ADC_CHANNEL18
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#define ADC_CHANNEL_TEMP_F40 16
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#define ADC_CHANNEL_TEMP_F42 18
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#define ADC_CHANNEL_VREF 17
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#define ADC_CHANNEL_VBAT 18
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/**@}*/
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/* --- ADC_SR values ------------------------------------------------------- */
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/* --- ADC_SR values ------------------------------------------------------- */
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@ -91,11 +91,14 @@ LGPL License Terms @ref lgpl_license
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#define ADC_CSR MMIO32(ADC1 + 0x300)
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#define ADC_CSR MMIO32(ADC1 + 0x300)
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#define ADC_CCR MMIO32(ADC1 + 0x304)
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#define ADC_CCR MMIO32(ADC1 + 0x304)
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/** @defgroup adc_channel ADC Channel Numbers
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/* These are _not_ consistent unfortunately! */
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* @ingroup adc_defines
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#define ADC_CHANNEL_TEMP ADC_CHANNEL16
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*
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#define ADC_CHANNEL_VREFINT ADC_CHANNEL17
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*@{*/
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#define ADC_CHANNEL_VBAT ADC_CHANNEL18
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#define ADC_CHANNEL_TEMP ADC_CHANNEL16
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#define ADC_CHANNEL_VREF ADC_CHANNEL17
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#define ADC_CHANNEL_VBAT ADC_CHANNEL18
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/**@}*/
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/* --- ADC_SR values ------------------------------------------------------- */
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/* --- ADC_SR values ------------------------------------------------------- */
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#define ADC_SR_JCNR (1 << 9)
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#define ADC_SR_JCNR (1 << 9)
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