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stm32: adc: standardize special channel names 

At least temp sensor, vrefint and vbat/vlcd should have consistent names and
consistent doxygen.
Dropped channel definitions that are the same as the raw number.
This commit is contained in:
Karl Palsson 2015-11-05 22:55:56 +00:00
parent 50c056f965
commit a22d6a8315
5 changed files with 36 additions and 33 deletions
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22
include/libopencm3/stm32/f0/adc.h
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@ -249,25 +249,9 @@
* @ingroup adc_defines
*
*@{*/
#define ADC_CHANNEL0 0x00
#define ADC_CHANNEL1 0x01
#define ADC_CHANNEL2 0x02
#define ADC_CHANNEL3 0x03
#define ADC_CHANNEL4 0x04
#define ADC_CHANNEL5 0x05
#define ADC_CHANNEL6 0x06
#define ADC_CHANNEL7 0x07
#define ADC_CHANNEL8 0x08
#define ADC_CHANNEL9 0x09
#define ADC_CHANNEL10 0x0A
#define ADC_CHANNEL11 0x0B
#define ADC_CHANNEL12 0x0C
#define ADC_CHANNEL13 0x0D
#define ADC_CHANNEL14 0x0E
#define ADC_CHANNEL15 0x0F
#define ADC_CHANNEL_TEMP 0x10
#define ADC_CHANNEL_VREF 0x11
#define ADC_CHANNEL_VBAT 0x12
#define ADC_CHANNEL_TEMP 16
#define ADC_CHANNEL_VREF 17
#define ADC_CHANNEL_VBAT 18
/**@}*/
/** @defgroup adc_api_opmode ADC Operation Modes

12
include/libopencm3/stm32/f1/adc.h
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@ -75,10 +75,6 @@ LGPL License Terms @ref lgpl_license
/* ADC regular data register (ADC_DR) */
#define ADC_DR(block) MMIO32((block) + 0x4c)
/* --- ADC Channels ------------------------------------------------------- */
#define ADC_CHANNEL_TEMP ADC_CHANNEL16
#define ADC_CHANNEL_VREFINT ADC_CHANNEL17
/* --- ADC_CR1 values ------------------------------------------------------ */
@ -397,6 +393,14 @@ and ADC2
#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
/* ADC1 only (dual mode) */
/** @defgroup adc_channel ADC Channel Numbers
* @ingroup adc_defines
*
*@{*/
#define ADC_CHANNEL_TEMP 16
#define ADC_CHANNEL_VREF 17
/**@}*/
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS

8
include/libopencm3/stm32/f3/adc.h
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@ -865,6 +865,14 @@
/* Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. */
/** @defgroup adc_channel ADC Channel Numbers
* @ingroup adc_defines
*
*@{*/
#define ADC_CHANNEL_TEMP 16
#define ADC_CHANNEL_VBAT 17
#define ADC_CHANNEL_VREF 18
/**@}*/
BEGIN_DECLS

14
include/libopencm3/stm32/f4/adc.h
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@ -84,11 +84,15 @@ LGPL License Terms @ref lgpl_license
/* --- ADC Channels ------------------------------------------------------- */
/* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18! */
#define ADC_CHANNEL_TEMP_F40 ADC_CHANNEL16
#define ADC_CHANNEL_TEMP_F42 ADC_CHANNEL18
#define ADC_CHANNEL_VREFINT ADC_CHANNEL17
#define ADC_CHANNEL_VBAT ADC_CHANNEL18
/** @defgroup adc_channel ADC Channel Numbers
* @ingroup adc_defines
* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18!
*@{*/
#define ADC_CHANNEL_TEMP_F40 16
#define ADC_CHANNEL_TEMP_F42 18
#define ADC_CHANNEL_VREF 17
#define ADC_CHANNEL_VBAT 18
/**@}*/
/* --- ADC_SR values ------------------------------------------------------- */

13
include/libopencm3/stm32/l1/adc.h
View File

@ -91,11 +91,14 @@ LGPL License Terms @ref lgpl_license
#define ADC_CSR MMIO32(ADC1 + 0x300)
#define ADC_CCR MMIO32(ADC1 + 0x304)
/* These are _not_ consistent unfortunately! */
#define ADC_CHANNEL_TEMP ADC_CHANNEL16
#define ADC_CHANNEL_VREFINT ADC_CHANNEL17
#define ADC_CHANNEL_VBAT ADC_CHANNEL18
/** @defgroup adc_channel ADC Channel Numbers
* @ingroup adc_defines
*
*@{*/
#define ADC_CHANNEL_TEMP ADC_CHANNEL16
#define ADC_CHANNEL_VREF ADC_CHANNEL17
#define ADC_CHANNEL_VBAT ADC_CHANNEL18
/**@}*/
/* --- ADC_SR values ------------------------------------------------------- */
#define ADC_SR_JCNR (1 << 9)