[STM32F0:ADC] Add register definitions
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BuFran
Piotr Esden-Tempski
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/* This provides unification of code over STM32F subfamilies */
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(STM32F0)
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# include <libopencm3/stm32/f0/adc.h>
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#elif defined(STM32F1)
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# include <libopencm3/stm32/f1/adc.h>
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#elif defined(STM32F3)
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# include <libopencm3/stm32/f3/adc.h>
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#elif defined(STM32F4)
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# include <libopencm3/stm32/f4/adc.h>
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#else
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# error "stm32 family not defined."
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#endif
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_ADC_H
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#define LIBOPENCM3_ADC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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#define ADC ADC_BASE
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/* ADC Registers ------------------------------------------------------------*/
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/* ADC interrupt and status register */
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#define ADC_ISR(base) MMIO32(base + 0x00)
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#define ADC1_ISR ADC_ISR(ADC)
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/* Interrupt Enable Register */
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#define ADC_IER(base) MMIO32(base + 0x04)
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#define ADC1_IER ADC_IER(ADC)
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/* Control Register */
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#define ADC_CR(base) MMIO32(base + 0x08)
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#define ADC1_CR ADC_CR(ADC)
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/* Configuration Register 1 */
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#define ADC_CFGR1(base) MMIO32(base + 0x0C)
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#define ADC1_CFGR1 ADC_CFGR1(ADC)
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/* Configuration Register 2 */
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#define ADC_CFGR2(base) MMIO32(base + 0x10)
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#define ADC1_CFGR2 ADC_CFGR2(ADC)
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/* Sample Time Register 1 */
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#define ADC_SMPR(base) MMIO32(base + 0x14)
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#define ADC1_SMPR ADC_SMPR(ADC)
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/* Watchdog Threshold Register */
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#define ADC_TR(base) MMIO32(base + 0x20)
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#define ADC1_TR ADC_TR(ADC)
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/* Channel Select Register */
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#define ADC_CHSELR(base) MMIO32(base + 0x28)
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#define ADC1_CHSELR ADC_CHSELR(ADC)
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/* Regular Data Register */
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#define ADC_DR(base) MMIO32(base + 0x40)
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#define ADC1_DR ADC_DR(ADC)
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/* Regular Data Register */
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#define ADC_CCR MMIO32(ADC_BASE + 0x308)
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/* Register values ----------------------------------------------------------*/
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/* ADC_ISR Values -----------------------------------------------------------*/
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#define ADC_ISR_AWD (1 << 7)
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#define ADC_ISR_OVR (1 << 4)
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#define ADC_ISR_EOSEQ (1 << 3)
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#define ADC_ISR_EOC (1 << 2)
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#define ADC_ISR_EOSMP (1 << 1)
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#define ADC_ISR_ADRDY (1 << 0)
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/* ADC_IER Values -----------------------------------------------------------*/
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#define ADC_IER_AWDIE (1 << 7)
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#define ADC_IER_OVRIE (1 << 4)
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#define ADC_IER_EOSEQIE (1 << 3)
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#define ADC_IER_EOCIE (1 << 2)
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#define ADC_IER_EOSMPIE (1 << 1)
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#define ADC_IER_ADRDYIE (1 << 0)
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/* ADC_CR Values ------------------------------------------------------------*/
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#define ADC_CR_ADCAL (1 << 31)
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#define ADC_CR_ADSTP (1 << 4)
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#define ADC_CR_ADSTART (1 << 2)
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#define ADC_CR_ADDIS (1 << 1)
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#define ADC_CR_ADEN (1 << 0)
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/* ADC_CFGR1 Values ---------------------------------------------------------*/
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#define ADC_CFGR1_AWDCH_SHIFT 26
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#define ADC_CFGR1_AWDCH (0x1F << ADC_CFGR1_AWDCH_SHIFT)
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#define ADC_CFGR1_AWDCH_VAL(x) ((x) << ADC_CFGR1_AWDCH_SHIFT)
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#define ADC_CFGR1_AWDEN (1 << 23)
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#define ADC_CFGR1_AWDSGL (1 << 22)
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#define ADC_CFGR1_DISCEN (1 << 16)
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#define ADC_CFGR1_AUTOFF (1 << 15)
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#define ADC_CFGR1_WAIT (1 << 14)
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#define ADC_CFGR1_CONT (1 << 13)
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#define ADC_CFGR1_OVRMOD (1 << 12)
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#define ADC_CFGR1_EXTEN_SHIFT 10
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#define ADC_CFGR1_EXTEN (3 << ADC_CFGR1_EXTEN_SHIFT)
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#define ADC_CFGR1_EXTEN_DISABLE (0 << ADC_CFGR1_EXTEN_SHIFT)
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#define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT)
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#define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT)
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#define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT)
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL (7 << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_ALIGN (1 << 5)
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#define ADC_CFGR1_RES_SHIFT 3
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#define ADC_CFGR1_RES (3 << ADC_CFGR1_RES_SHIFT)
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#define ADC_CFGR1_RES_12_BIT (0 << ADC_CFGR1_RES_SHIFT)
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#define ADC_CFGR1_RES_10_BIT (1 << ADC_CFGR1_RES_SHIFT)
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#define ADC_CFGR1_RES_8_BIT (2 << ADC_CFGR1_RES_SHIFT)
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#define ADC_CFGR1_RES_6_BIT (3 << ADC_CFGR1_RES_SHIFT)
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#define ADC_CFGR1_SCANDIR (1 << 2)
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#define ADC_CFGR1_DMACFG (1 << 1)
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#define ADC_CFGR1_DMAEN (1 << 0)
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/* ADC_CFGR2 Values ---------------------------------------------------------*/
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#define ADC_CFGR2_CKMODE_SHIFT 30
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#define ADC_CFGR2_CKMODE (3 << ADC_CFGR2_CKMODE_SHIFT)
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#define ADC_CFGR2_CKMODE_CK_ADC (0 << ADC_CFGR2_CKMODE_SHIFT)
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#define ADC_CFGR2_CKMODE_PCLK_DIV2 (1 << ADC_CFGR2_CKMODE_SHIFT)
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#define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT)
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/* ADC_SMPR Values ----------------------------------------------------------*/
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#define ADC_SMPR_SMP_SHIFT 0
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#define ADC_SMPR_SMP (7 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_001DOT5 (0 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_007DOT5 (1 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_013DOT5 (2 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_028DOT5 (3 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_041DOT5 (4 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_055DOT5 (5 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_071DOT5 (6 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_239DOT5 (7 << ADC_SMPR_SMP_SHIFT)
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/* ADC_TR Values ------------------------------------------------------------*/
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#define ADC_TR_LT_SHIFT 0
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#define ADC_TR_LT (0xFFF << ADC_TR_LT_SHIFT)
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#define ADC_TR_LT_VAL(x) ((x) << ADC_TR_LT_SHIFT)
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#define ADC_TR_HT_SHIFT 16
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#define ADC_TR_HT (0xFFF << ADC_TR_HT_SHIFT)
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#define ADC_TR_HT_VAL(x) ((x) << ADC_TR_HT_SHIFT)
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/* ADC_CHSELR Values --------------------------------------------------------*/
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#define ADC_CHSELR_CHSEL(x) (1 << (x))
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/* ADC_DR Values ------------------------------------------------------------*/
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#define ADC_DR_DATA 0xFFFF
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/* ADC_CCR Values ------------------------------------------------------------*/
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#define ADC_CCR_VBATEN (1 << 24)
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#define ADC_CCR_TSEN (1 << 23)
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#define ADC_CCR_VREFEN (1 << 22)
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BEGIN_DECLS
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END_DECLS
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#endif
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