Minor whitespace fixes.
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@ -39,11 +39,13 @@
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/* TODO: PID, CID */
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/* --- ITM_STIM values ----------------------------------------------------- */
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/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
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/* Bits 31:1 - RAZ */
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#define ITM_STIM_FIFOREADY (1 << 0)
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/* --- ITM_TER values ------------------------------------------------------ */
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/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
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/* --- ITM_TPR values ------------------------------------------------------ */
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@ -54,6 +56,7 @@
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*/
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/* --- ITM_TCR values ------------------------------------------------------ */
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/* Bits 31:24 - Reserved */
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#define ITM_TCR_BUSY (1 << 23)
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#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
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@ -70,5 +73,4 @@
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#define ITM_TCR_TSENA (1 << 1)
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#define ITM_TCR_ITMENA (1 << 0)
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#endif
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@ -48,6 +48,7 @@
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/* TODO: PID, CID */
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/* --- TPIU_SSPSR values --------------------------------------------------- */
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/*
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* bit[N] == 0, trace port width of (N+1) not supported
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* bit[N] == 1, trace port width of (N+1) supported
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@ -57,22 +58,26 @@
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#define TPIU_SSPSR_WORD (1 << 3)
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/* --- TPIU_SSPSR values --------------------------------------------------- */
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/* Same format as TPIU_SSPSR, except only one is set */
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#define TPIU_CSPSR_BYTE (1 << 0)
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#define TPIU_CSPSR_HALFWORD (1 << 1)
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#define TPIU_CSPSR_WORD (1 << 3)
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/* --- TPIU_ACPR values ---------------------------------------------------- */
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/* Bits 31:16 - Reserved */
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/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
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/* --- TPIU_SPPR values ---------------------------------------------------- */
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/* Bits 31:2 - Reserved */
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#define TPIU_SPPR_SYNC (0x0)
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#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
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#define TPIU_SPPR_ASYNC_NRZ (0x2)
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/* --- TPIU_FFSR values ---------------------------------------------------- */
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/* Bits 31:4 - Reserved */
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#define TPIU_FFSR_FTNONSTOP (1 << 3)
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#define TPIU_FFSR_TCPRESENT (1 << 2)
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@ -80,6 +85,7 @@
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#define TPIU_FFSR_FLINPROG (1 << 0)
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/* --- TPIU_FFCR values ---------------------------------------------------- */
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/* Bits 31:9 - Reserved */
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#define TPIU_FFCR_TRIGIN (1 << 8)
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/* Bits 7:2 - Reserved */
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