unified nvic.c
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/** @defgroup STM32F_nvic_file NVIC
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@ingroup STM32F_files
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@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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@author @htmlonly © @endhtmlonly 2012 Fergus Noble <fergusnoble@gmail.com>
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@date 18 August 2012
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The STM32F series provides up to 68 maskable user interrupts for the STM32F10x
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series, and 87 for the STM32F2xx and STM32F4xx series.
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The NVIC registers are defined by the ARM standards but the STM32F series have some
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additional limitations
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@see Cortex-M3 Devices Generic User Guide
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@see STM32F10xxx Cortex-M3 programming manual
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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@ -40,10 +18,32 @@ LGPL License Terms @ref lgpl_license
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @defgroup CM3_nvic_file NVIC
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@ingroup CM3_files
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@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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@author @htmlonly © @endhtmlonly 2012 Fergus Noble <fergusnoble@gmail.com>
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@date 18 August 2012
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Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults,
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systicks etc.) and varying numbers of implementation defined interrupts
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(typically peripherial interrupts and DMA).
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@see Cortex-M3 Devices Generic User Guide
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@see STM32F10xxx Cortex-M3 programming manual
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LGPL License Terms @ref lgpl_license
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*/
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/**@{*/
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/scs.h>
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/*-----------------------------------------------------------------------------*/
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/** @brief NVIC Enable Interrupt
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@ -153,7 +153,18 @@ Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping.
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void nvic_set_priority(u8 irqn, u8 priority)
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{
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NVIC_IPR(irqn) = priority;
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/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
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* negative interrupt numbers assigned to the system interrupts. better
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* handling would mean signed integers. */
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if(irqn>=NVIC_IRQ_COUNT)
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{
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/* Cortex-M system interrupts */
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SCS_SHPR( (irqn&0xF)-4 ) = priority;
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}else
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{
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/* Device specific interrupts */
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NVIC_IPR(irqn) = priority;
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}
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}
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/*-----------------------------------------------------------------------------*/
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NVIC_STIR |= irqn;
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}
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/**@}*/
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@ -1,76 +0,0 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/scs.h>
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#include <libopencm3/lpc43xx/nvic.h>
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void nvic_enable_irq(u8 irqn)
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{
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NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
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}
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void nvic_disable_irq(u8 irqn)
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{
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NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
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}
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u8 nvic_get_pending_irq(u8 irqn)
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{
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return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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void nvic_set_pending_irq(u8 irqn)
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{
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NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
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}
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void nvic_clear_pending_irq(u8 irqn)
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{
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NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
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}
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u8 nvic_get_active_irq(u8 irqn)
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{
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return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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u8 nvic_get_irq_enabled(u8 irqn)
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{
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return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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void nvic_set_priority(u8 irqn, u8 priority)
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{
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if(irqn>NVIC_M4_QEI_IRQ)
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{
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/* Cortex-M system interrupts */
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SCS_SHPR( (irqn&0xF)-4 ) = priority;
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}else
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{
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/* Device specific interrupts */
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NVIC_IPR(irqn) = priority;
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}
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}
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void nvic_generate_software_interrupt(u8 irqn)
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{
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if (irqn <= 239)
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NVIC_STIR |= irqn;
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}
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