Finish RCC definitions => Working example!
This commit is contained in:
Karl Palsson
parent
8318384cf1
commit
9aed64a19d
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@ -29,7 +29,7 @@ void gpio_setup(void)
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{
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/* Enable GPIOB clock. */
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/* Manually: */
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RCC_AHBENR |= RCC_AHBENR_IOPBEN;
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RCC_AHBENR |= RCC_AHBENR_GPIOBEN;
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/* Using API functions: */
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//rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPBEN);
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@ -63,7 +63,7 @@ int main(void)
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// __asm__("nop");
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/* Using API function gpio_toggle(): */
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gpio_toggle(PORT_LED, PORT_LED); /* LED on/off */
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gpio_toggle(PORT_LED, PIN_LED); /* LED on/off */
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for (i = 0; i < 1000000; i++) /* Wait a bit. */
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__asm__("nop");
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}
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@ -219,27 +219,19 @@ LGPL License Terms @ref lgpl_license
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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TODO : up to here
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#define RCC_APB1RSTR_COMPRST (1 << 31)
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#define RCC_APB1RSTR_DACRST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_BKPRST (1 << 27)
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#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
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#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
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#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */
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#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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#define RCC_APB1RSTR_UART5RST (1 << 20)
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#define RCC_APB1RSTR_UART4RST (1 << 19)
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#define RCC_APB1RSTR_USART3RST (1 << 18)
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#define RCC_APB1RSTR_USART2RST (1 << 17)
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#define RCC_APB1RSTR_SPI3RST (1 << 15)
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#define RCC_APB1RSTR_SPI2RST (1 << 14)
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#define RCC_APB1RSTR_WWDGRST (1 << 11)
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#define RCC_APB1RSTR_LCDRST (1 << 9)
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#define RCC_APB1RSTR_TIM7RST (1 << 5)
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#define RCC_APB1RSTR_TIM6RST (1 << 4)
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#define RCC_APB1RSTR_TIM5RST (1 << 3)
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#define RCC_APB1RSTR_TIM4RST (1 << 2)
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#define RCC_APB1RSTR_TIM3RST (1 << 1)
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#define RCC_APB1RSTR_TIM2RST (1 << 0)
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@ -250,17 +242,15 @@ TODO : up to here
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@ingroup STM32L1xx_rcc_defines
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@{*/
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#define RCC_AHBENR_ETHMACENRX (1 << 16)
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#define RCC_AHBENR_ETHMACENTX (1 << 15)
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#define RCC_AHBENR_ETHMACEN (1 << 14)
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#define RCC_AHBENR_OTGFSEN (1 << 12)
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#define RCC_AHBENR_SDIOEN (1 << 10)
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#define RCC_AHBENR_FSMCEN (1 << 8)
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#define RCC_AHBENR_CRCEN (1 << 6)
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#define RCC_AHBENR_FLITFEN (1 << 4)
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#define RCC_AHBENR_SRAMEN (1 << 2)
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#define RCC_AHBENR_DMA2EN (1 << 1)
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#define RCC_AHBENR_DMA1EN (1 << 0)
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#define RCC_AHBENR_DMA1EN (1 << 24)
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#define RCC_AHBENR_FLITFEN (1 << 15)
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#define RCC_AHBENR_CRCEN (1 << 12)
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#define RCC_AHBENR_GPIOHEN (1 << 5)
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#define RCC_AHBENR_GPIOEEN (1 << 4)
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#define RCC_AHBENR_GPIODEN (1 << 3)
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#define RCC_AHBENR_GPIOCEN (1 << 2)
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#define RCC_AHBENR_GPIOBEN (1 << 1)
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#define RCC_AHBENR_GPIOAEN (1 << 0)
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/*@}*/
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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@ -269,21 +259,13 @@ TODO : up to here
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@ingroup STM32L1xx_rcc_defines
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@{*/
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#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
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#define RCC_APB2ENR_USART1EN (1 << 14)
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#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
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#define RCC_APB2ENR_SPI1EN (1 << 12)
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#define RCC_APB2ENR_TIM1EN (1 << 11)
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#define RCC_APB2ENR_ADC2EN (1 << 10)
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#define RCC_APB2ENR_ADC1EN (1 << 9)
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#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */
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#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */
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#define RCC_APB2ENR_IOPEEN (1 << 6)
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#define RCC_APB2ENR_IOPDEN (1 << 5)
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#define RCC_APB2ENR_IOPCEN (1 << 4)
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#define RCC_APB2ENR_IOPBEN (1 << 3)
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#define RCC_APB2ENR_IOPAEN (1 << 2)
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#define RCC_APB2ENR_AFIOEN (1 << 0)
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#define RCC_APB2ENR_TIM11EN (1 << 4)
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#define RCC_APB2ENR_TIM10EN (1 << 3)
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#define RCC_APB2ENR_TIM9EN (1 << 2)
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#define RCC_APB2ENR_SYSCFGEN (1 << 0)
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/*@}*/
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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@ -292,38 +274,61 @@ TODO : up to here
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@ingroup STM32L1xx_rcc_defines
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@{*/
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#define RCC_APB1ENR_COMPEN (1 << 31)
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#define RCC_APB1ENR_DACEN (1 << 29)
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#define RCC_APB1ENR_PWREN (1 << 28)
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#define RCC_APB1ENR_BKPEN (1 << 27)
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#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
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#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
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#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */
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#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
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#define RCC_APB1ENR_USBEN (1 << 23)
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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#define RCC_APB1ENR_I2C1EN (1 << 21)
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#define RCC_APB1ENR_UART5EN (1 << 20)
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#define RCC_APB1ENR_UART4EN (1 << 19)
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#define RCC_APB1ENR_USART3EN (1 << 18)
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#define RCC_APB1ENR_USART2EN (1 << 17)
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#define RCC_APB1ENR_SPI3EN (1 << 15)
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#define RCC_APB1ENR_SPI2EN (1 << 14)
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#define RCC_APB1ENR_WWDGEN (1 << 11)
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#define RCC_APB1ENR_LCDEN (1 << 9)
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#define RCC_APB1ENR_TIM7EN (1 << 5)
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#define RCC_APB1ENR_TIM6EN (1 << 4)
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#define RCC_APB1ENR_TIM5EN (1 << 3)
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#define RCC_APB1ENR_TIM4EN (1 << 2)
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#define RCC_APB1ENR_TIM3EN (1 << 1)
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#define RCC_APB1ENR_TIM2EN (1 << 0)
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/*@}*/
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/* --- RCC_BDCR values ----------------------------------------------------- */
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/* --- RCC_AHBLPENR -------------------------------------------------------- */
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#define RCC_AHBLPENR_DMA1LPEN (1 << 24)
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#define RCC_AHBLPENR_SRAMLPEN (1 << 16)
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#define RCC_AHBLPENR_FLITFLPEN (1 << 15)
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#define RCC_AHBLPENR_CRCLPEN (1 << 12)
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#define RCC_AHBLPENR_GPIOHLPEN (1 << 5)
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#define RCC_AHBLPENR_GPIOELPEN (1 << 4)
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#define RCC_AHBLPENR_GPIODLPEN (1 << 3)
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#define RCC_AHBLPENR_GPIOCLPEN (1 << 2)
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#define RCC_AHBLPENR_GPIOBLPEN (1 << 1)
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#define RCC_AHBLPENR_GPIOALPEN (1 << 0)
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#define RCC_APB2LPENR_USART1LPEN (1 << 14)
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#define RCC_APB2LPENR_SPI1LPEN (1 << 12)
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#define RCC_APB2LPENR_ADC1LPEN (1 << 9)
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#define RCC_APB2LPENR_TIM11LPEN (1 << 4)
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#define RCC_APB2LPENR_TIM10LPEN (1 << 3)
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#define RCC_APB2LPENR_TIM9LPEN (1 << 2)
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#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0)
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#define RCC_APB1LPENR_COMPLPEN (1 << 31)
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#define RCC_APB1LPENR_DACLPEN (1 << 29)
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#define RCC_APB1LPENR_PWRLPEN (1 << 28)
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#define RCC_APB1LPENR_USBLPEN (1 << 23)
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#define RCC_APB1LPENR_I2C2LPEN (1 << 22)
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#define RCC_APB1LPENR_I2C1LPEN (1 << 21)
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#define RCC_APB1LPENR_USART3LPEN (1 << 18)
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#define RCC_APB1LPENR_USART2LPEN (1 << 17)
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#define RCC_APB1LPENR_SPI2LPEN (1 << 14)
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#define RCC_APB1LPENR_WWDGLPEN (1 << 11)
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#define RCC_APB1LPENR_LCDLPEN (1 << 9)
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#define RCC_APB1LPENR_TIM7LPEN (1 << 5)
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#define RCC_APB1LPENR_TIM6LPEN (1 << 4)
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#define RCC_APB1LPENR_TIM4LPEN (1 << 2)
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#define RCC_APB1LPENR_TIM3LPEN (1 << 1)
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#define RCC_APB1LPENR_TIM2LPEN (1 << 0)
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#define RCC_BDCR_BDRST (1 << 16)
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#define RCC_BDCR_RTCEN (1 << 15)
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/* RCC_BDCR[9:8]: RTCSEL */
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#define RCC_BDCR_LSEBYP (1 << 2)
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#define RCC_BDCR_LSERDY (1 << 1)
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#define RCC_BDCR_LSEON (1 << 0)
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/* --- RCC_CSR values ------------------------------------------------------ */
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@ -333,72 +338,17 @@ TODO : up to here
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#define RCC_CSR_SFTRSTF (1 << 28)
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#define RCC_CSR_PORRSTF (1 << 27)
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#define RCC_CSR_PINRSTF (1 << 26)
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#define RCC_CSR_OBLRSTF (1 << 25)
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#define RCC_CSR_RMVF (1 << 24)
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#define RCC_CSR_RTCRST (1 << 23)
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#define RCC_CSR_RTCEN (1 << 22)
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/* RTCSEL[1:0] */
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#define RCC_CSR_LSEBYP (1 << 10)
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#define RCC_CSR_LSERDY (1 << 9)
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#define RCC_CSR_LSEON (1 << 8)
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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/* --- RCC_AHBRSTR values -------------------------------------------------- */
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#define RCC_AHBRSTR_ETHMACRST (1 << 14)
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#define RCC_AHBRSTR_OTGFSRST (1 << 12)
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/* --- RCC_CFGR2 values ---------------------------------------------------- */
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/* I2S3SRC: I2S3 clock source */
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#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0
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#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1
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/* I2S2SRC: I2S2 clock source */
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#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0
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#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1
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/* PREDIV1SRC: PREDIV1 entry clock source */
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#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0
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#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1
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#define RCC_CFGR2_PLL2MUL (1 << 0)
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#define RCC_CFGR2_PREDIV2 (1 << 0)
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#define RCC_CFGR2_PREDIV1 (1 << 0)
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/* PLL3MUL: PLL3 multiplication factor */
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf
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/* PLL2MUL: PLL2 multiplication factor */
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
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/* PREDIV2: PREDIV2 division factor */
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#define RCC_CFGR2_PREDIV2_NODIV 0x0
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#define RCC_CFGR2_PREDIV2_DIV2 0x1
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#define RCC_CFGR2_PREDIV2_DIV3 0x2
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#define RCC_CFGR2_PREDIV2_DIV4 0x3
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#define RCC_CFGR2_PREDIV2_DIV5 0x4
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#define RCC_CFGR2_PREDIV2_DIV6 0x5
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#define RCC_CFGR2_PREDIV2_DIV7 0x6
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#define RCC_CFGR2_PREDIV2_DIV8 0x7
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#define RCC_CFGR2_PREDIV2_DIV9 0x8
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#define RCC_CFGR2_PREDIV2_DIV10 0x9
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#define RCC_CFGR2_PREDIV2_DIV11 0xa
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#define RCC_CFGR2_PREDIV2_DIV12 0xb
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#define RCC_CFGR2_PREDIV2_DIV13 0xc
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#define RCC_CFGR2_PREDIV2_DIV14 0xd
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#define RCC_CFGR2_PREDIV2_DIV15 0xe
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#define RCC_CFGR2_PREDIV2_DIV16 0xf
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/* --- Variable definitions ------------------------------------------------ */
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extern u32 rcc_ppre1_frequency;
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@ -407,9 +357,10 @@ extern u32 rcc_ppre2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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PLL, HSE, HSI, LSE, LSI
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PLL, HSE, HSI, MSI, LSE, LSI
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} osc_t;
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#if FINISHED == 0
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void rcc_osc_ready_int_clear(osc_t osc);
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void rcc_osc_ready_int_enable(osc_t osc);
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void rcc_osc_ready_int_disable(osc_t osc);
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@ -449,5 +400,6 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
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void rcc_backupdomain_reset(void);
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#endif
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#endif
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