Fix compile by using the correct variable name.
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ab8cec181c
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944456fde1
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@ -25,7 +25,7 @@
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/* --- USART registers ----------------------------------------------------- */
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/* Status register (USARTx_SR) */
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#define USART_SR(usart) MMIO32(usart_base + 0x00)
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#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
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#define USART1_SR USART_SR(USART1_BASE)
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#define USART2_SR USART_SR(USART2_BASE)
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#define USART3_SR USART_SR(USART3_BASE)
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@ -33,7 +33,7 @@
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#define UART5_SR USART_SR(UART5_BASE)
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/* Data register (USARTx_DR) */
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#define USART_DR(usart) MMIO32(usart_base + 0x04)
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#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
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#define USART1_DR USART_DR(USART1_BASE)
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#define USART2_DR USART_DR(USART2_BASE)
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#define USART3_DR USART_DR(USART3_BASE)
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@ -41,7 +41,7 @@
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#define UART5_DR USART_DR(UART5_BASE)
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/* Baud rate register (USARTx_BRR) */
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#define USART_BRR(usart) MMIO32(usart_base + 0x08)
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#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
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#define USART1_BRR USART_BRR(USART1_BASE)
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#define USART2_BRR USART_BRR(USART2_BASE)
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#define USART3_BRR USART_BRR(USART3_BASE)
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@ -49,7 +49,7 @@
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#define UART5_BRR USART_BRR(UART5_BASE)
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/* Control register 1 (USARTx_CR1) */
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#define USART_CR1(usart) MMIO32(usart_base + 0x0c)
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#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
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#define USART1_CR1 USART_CR1(USART1_BASE)
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#define USART2_CR1 USART_CR1(USART2_BASE)
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#define USART3_CR1 USART_CR1(USART3_BASE)
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@ -57,7 +57,7 @@
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#define UART5_CR1 USART_CR1(UART5_BASE)
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/* Control register 2 (USARTx_CR2) */
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#define USART_CR2(usart) MMIO32(usart_base + 0x10)
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#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
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#define USART1_CR2 USART_CR2(USART1_BASE)
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#define USART2_CR2 USART_CR2(USART2_BASE)
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#define USART3_CR2 USART_CR2(USART3_BASE)
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@ -65,7 +65,7 @@
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#define UART5_CR2 USART_CR2(UART5_BASE)
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/* Control register 3 (USARTx_CR3) */
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#define USART_CR3(usart) MMIO32(usart_base + 0x14)
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#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
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#define USART1_CR3 USART_CR3(USART1_BASE)
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#define USART2_CR3 USART_CR3(USART2_BASE)
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#define USART3_CR3 USART_CR3(USART3_BASE)
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@ -73,7 +73,7 @@
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#define UART5_CR3 USART_CR3(UART5_BASE)
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/* Guard time and prescaler register (USARTx_GTPR) */
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#define USART_GTPR(usart) MMIO32(usart_base + 0x18)
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#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
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#define USART1_GTPR USART_GTPR(USART1_BASE)
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#define USART2_GTPR USART_GTPR(USART2_BASE)
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#define USART3_GTPR USART_GTPR(USART3_BASE)
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