STM32F0: Turn on PLL clock source when asked to

The STM32F05xxx/06xxx manual describes on p.98 (Sec 7.4.1) the RCC_CR
register, on which it says that bit 24 is the PLLON bit which has to be
enabled before using the PLL. This causes the PLL to be enabled with
rcc_osc_on(PLL).

lib/stm32/f0/rcc.c

@@ -250,7 +250,7 @@ void rcc_osc_on(enum rcc_osc osc)
 		RCC_CSR |= RCC_CSR_LSION;
 		break;
 	case PLL:
-		/* don't do anything */
+		RCC_CR|=RCC_CR_PLLON; 
 		break;
 	}
 }