lm4f: timers: add basic register definitions
Add the timers to the memory map and the basic registers at least.
This commit is contained in:
Karl Palsson
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08c76f25ec
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824beaa472
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@ -50,6 +50,20 @@
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#define GPIOP_BASE (0x40065000U)
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#define GPIOQ_BASE (0x40066000U)
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#define TIMER0_BASE (0x40030000U)
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#define TIMER1_BASE (0x40031000U)
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#define TIMER2_BASE (0x40032000U)
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#define TIMER3_BASE (0x40033000U)
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#define TIMER4_BASE (0x40034000U)
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#define TIMER5_BASE (0x40035000U)
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#define WTIMER0 (0x40036000U)
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#define WTIMER1 (0x40037000U)
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#define WTIMER2 (0x4004C000U)
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#define WTIMER3 (0x4004D000U)
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#define WTIMER4 (0x4004E000U)
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#define WTIMER5 (0x4004F000U)
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#define UART0_BASE (0x4000C000U)
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#define UART1_BASE (0x4000D000U)
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#define UART2_BASE (0x4000E000U)
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@ -0,0 +1,99 @@
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/** @defgroup timer_defines General Purpose Timers
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*
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* @brief <b>Defined Constants and Types for the LM4F General Purpose Timers</b>
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*
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* @ingroup LM4Fxx_defines
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright 2018 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lm4f/memorymap.h>
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/**@{*/
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/** @defgroup timer_registers GP Timer registers
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* Unless otherwise specified, these registers are RW
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*@{*/
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/** Configuration */
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#define GPTMCFG(tim_base) MMIO32((tim_base) + 0)
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/** Timer A mode */
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#define GPTMTAMR(tim_base) MMIO32((tim_base) + 0x4)
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/** Timer B mode */
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#define GPTMTBMR(tim_base) MMIO32((tim_base) + 0x8)
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/** Control */
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#define GPTMCTL(tim_base) MMIO32((tim_base) + 0xc)
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/** Synchronize */
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#define GPTMSYNC(tim_base) MMIO32((tim_base) + 0x10)
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/** Interrupt mask */
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#define GPTMIMR(tim_base) MMIO32((tim_base) + 0x18)
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/** Raw interrupt status (RO) */
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#define GPTMRIS(tim_base) MMIO32((tim_base) + 0x1c)
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/** Masked interrupt status (RO) */
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#define GPTMMIS(tim_base) MMIO32((tim_base) + 0x20)
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/** Interrupt clear (W1C) */
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#define GPTMICR(tim_base) MMIO32((tim_base) + 0x24)
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/** Timer A Interval load */
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#define GPTMTAILR(tim_base) MMIO32((tim_base) + 0x28)
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/** Timer B Interval load */
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#define GPTMTBILR(tim_base) MMIO32((tim_base) + 0x2c)
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/** Timer A match */
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#define GPTMTAMATCHR(tim_base) MMIO32((tim_base) + 0x30)
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/** Timer B match */
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#define GPTMTBMATCHR(tim_base) MMIO32((tim_base) + 0x34)
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/** Timer A prescale */
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#define GPTMTAPR(tim_base) MMIO32((tim_base) + 0x38)
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/** Timer B prescale */
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#define GPTMTBPR(tim_base) MMIO32((tim_base) + 0x3c)
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/** Timer A prescale match */
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#define GPTMTAPMR(tim_base) MMIO32((tim_base) + 0x40)
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/** Timer A prescale match */
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#define GPTMTBPMR(tim_base) MMIO32((tim_base) + 0x44)
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/* Timer A (RO) */
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#define GPTMTAR(tim_base) MMIO32((tim_base) + 0x48)
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/* Timer B (RO) */
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#define GPTMTBR(tim_base) MMIO32((tim_base) + 0x4c)
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/* Timer A value */
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#define GPTMTAV(tim_base) MMIO32((tim_base) + 0x50)
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/* Timer B value */
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#define GPTMTBV(tim_base) MMIO32((tim_base) + 0x54)
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/** RTC Predivide (RO) */
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#define GPTMRTCPD(tim_base) MMIO32((tim_base) + 0x58)
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/** Timer A prescale snapshot (RO) */
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#define GPTMTAPS(tim_base) MMIO32((tim_base) + 0x5c)
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/** Timer B prescale snapshot (RO) */
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#define GPTMTBPS(tim_base) MMIO32((tim_base) + 0x60)
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/** Timer A prescale value (RO) */
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#define GPTMTAPV(tim_base) MMIO32((tim_base) + 0x64)
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/** Timer B prescale value (RO) */
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#define GPTMTBPV(tim_base) MMIO32((tim_base) + 0x68)
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/** Peripheral properties (RO) */
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#define GPTMPP(tim_base) MMIO32((tim_base) + 0xfc0)
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/**@}*/
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/**@}*/
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