stm32f3: include CAN
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@ -59,7 +59,7 @@
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5C00)
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#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define BX_CAN_BASE (PERIPH_BASE_APB1 + 0x6400)
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#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
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/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved */
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/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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@ -218,7 +218,7 @@
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#define RCC_APB1RSTR_DAC1RST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_DAC2RST (1 << 26)
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#define RCC_APB1RSTR_CANRST (1 << 25)
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#define RCC_APB1RSTR_CAN1RST (1 << 25)
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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@ -41,6 +41,8 @@ LGPL License Terms @ref lgpl_license
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# include <libopencm3/stm32/f1/rcc.h>
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#elif defined(STM32F2)
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# include <libopencm3/stm32/f2/rcc.h>
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#elif defined(STM32F3)
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# include <libopencm3/stm32/f3/rcc.h>
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#elif defined(STM32F4)
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# include <libopencm3/stm32/f4/rcc.h>
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#else
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@ -75,8 +77,10 @@ void can_reset(uint32_t canport)
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
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} else {
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#if defined(BX_CAN2_BASE)
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
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#endif
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}
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}
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@ -36,7 +36,7 @@ TGT_CFLAGS += $(DEBUG_FLAGS)
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ARFLAGS = rcs
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OBJS = rcc.o adc.o i2c.o usart.o dma.o flash.o desig.o
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OBJS = rcc.o adc.o can.o i2c.o usart.o dma.o flash.o desig.o
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OBJS += gpio_common_all.o gpio_common_f0234.o \
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dac_common_all.o crc_common_all.o \
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