[STM32F0:CEC] Add register definitions
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/* This provides unification of code over STM32F subfamilies */
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(STM32F0)
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# include <libopencm3/stm32/f0/cec.h>
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#else
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# error "stm32 family not defined."
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#endif
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CEC_H
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#define LIBOPENCM3_CEC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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#define CEC CEC_BASE
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/* CEC Registers ------------------------------------------------------------*/
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#define CEC_CR MMIO32(CEC_BASE + 0x00)
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#define CEC_CFGR MMIO32(CEC_BASE + 0x04)
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#define CEC_TXDR MMIO32(CEC_BASE + 0x08)
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#define CEC_RXDR MMIO32(CEC_BASE + 0x0c)
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#define CEC_ISR MMIO32(CEC_BASE + 0x10)
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#define CEC_IER MMIO32(CEC_BASE + 0x14)
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/* Register values ----------------------------------------------------------*/
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/* CEC_CR Values ------------------------------------------------------------*/
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#define CEC_CR_TXEOM (1 << 2)
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#define CEC_CR_TXSOM (1 << 1)
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#define CEC_CR_CECEN (1 << 0)
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/* CEC_CFGR Values ----------------------------------------------------------*/
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#define CEC_CFGR_LSTN (1 << 31)
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#define CEC_CFGR_OAR_SHIFT 16
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#define CEC_CFGR_OAR (0x3FFF << CEC_CFGR_OAR_SHIFT)
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#define CEC_CFGR_SFTOPT (1 << 8)
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#define CEC_CFGR_BRDNOGEN (1 << 7)
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#define CEC_CFGR_LBPEGEN (1 << 6)
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#define CEC_CFGR_BREGEN (1 << 5)
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#define CEC_CFGR_BRESTP (1 << 4)
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#define CEC_CFGR_RXTOL (1 << 3)
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#define CEC_CFGR_SFT_SHIFT 0
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#define CEC_CFGR_SFT (7 >> CEC_CFGR_SFT_SHIFT)
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/* CEC_ISR Values -----------------------------------------------------------*/
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#define CEC_ISR_TXACKE (1 << 12)
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#define CEC_ISR_TXERR (1 << 11)
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#define CEC_ISR_TXUDR (1 << 10)
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#define CEC_ISR_TXEND (1 << 9)
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#define CEC_ISR_TXBR (1 << 8)
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#define CEC_ISR_ARBLST (1 << 7)
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#define CEC_ISR_RXACKE (1 << 6)
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#define CEC_ISR_LBPE (1 << 5)
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#define CEC_ISR_SBPE (1 << 4)
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#define CEC_ISR_BRE (1 << 3)
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#define CEC_ISR_RXOVR (1 << 2)
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#define CEC_ISR_RXEND (1 << 1)
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#define CEC_ISR_RXBR (1 << 0)
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/* CEC_IER Values -----------------------------------------------------------*/
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#define CEC_IER_TXACKIE (1 << 12)
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#define CEC_IER_TXERRIE (1 << 11)
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#define CEC_IER_TXUDRIE (1 << 10)
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#define CEC_IER_TXENDIE (1 << 9)
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#define CEC_IER_TXBRIE (1 << 8)
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#define CEC_IER_ARBLSTIE (1 << 7)
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#define CEC_IER_RXACKIE (1 << 6)
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#define CEC_IER_LBPEIE (1 << 5)
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#define CEC_IER_SBPEIE (1 << 4)
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#define CEC_IER_BREIE (1 << 3)
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#define CEC_IER_RXOVRIE (1 << 2)
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#define CEC_IER_RXENDIE (1 << 1)
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#define CEC_IER_RXBRIE (1 << 0)
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BEGIN_DECLS
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END_DECLS
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#endif
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