stm32: adc_common_v2: Make EXTSEL and ALIGN definitions per chip
STM32G4 uses v2 ADC but has EXTSEL and ALIGN fields modified, rather than making a v3 ADC for these minor changes, the definitions have been moved to the chip specific headers, so that the common code can work for G4 onwards.
This commit is contained in:
Ben Brewer
Karl Palsson
parent
b84bf6e244
commit
7219b32902
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@ -150,9 +150,6 @@ specific memorymap.h header before including this header file.*/
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#define ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10)
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/**@}*/
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/** ALIGN: Data alignment */
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#define ADC_CFGR1_ALIGN (1 << 5)
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#define ADC_CFGR1_RES_MASK (0x3 << 3)
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/** @defgroup adc_cfgr1_res RES: Data resolution
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@{*/
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@ -143,11 +143,6 @@ specific memorymap.h header before including this header file.*/
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#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT)
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#define ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)
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/* EXTSEL[3:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/* ADC_SQRx Values: Regular Sequence ordering------------------------------- */
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#define ADC_SQR1_L_SHIFT 0
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@ -58,11 +58,6 @@ specific memorymap.h header before including this header file.*/
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/** Auto off mode */
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#define ADC_CFGR1_AUTOFF (1 << 15)
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT)
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/** EXTSEL[2:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/** SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) */
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#define ADC_CFGR1_SCANDIR (1 << 2)
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/**@}*/
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@ -71,6 +71,16 @@
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/* Register values */
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/*****************************************************************************/
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/* ADC_CFGR1 Values ---------------------------------------------------------*/
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/** ALIGN: Data alignment */
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#define ADC_CFGR1_ALIGN (1 << 5)
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/* EXTSEL[2:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/* ADC_CFGR2 Values ---------------------------------------------------------*/
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#define ADC_CFGR2_CKMODE_SHIFT 30
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@ -209,6 +209,16 @@
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#define ADC_CR_ADVREGEN_DISABLE (0x2 << 28)
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#define ADC_CR_ADVREGEN_MASK (0x3 << 28)
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/* ADC_CFGR1 Values ---------------------------------------------------------*/
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/** ALIGN: Data alignment */
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#define ADC_CFGR1_ALIGN (1 << 5)
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/* EXTSEL[2:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/****************************************************************************/
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/* ADC_SMPRx ADC Sample Time Selection for Channels */
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/** @defgroup adc_sample ADC Sample Time Selection values
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@ -121,6 +121,14 @@
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/** @addtogroup adc_cfgr1
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@{*/
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/** ALIGN: Data alignment */
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#define ADC_CFGR1_ALIGN (1 << 5)
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/* EXTSEL[2:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/** CHSELRMOD: Mode Selection of the ADC_CHSELR register */
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#define ADC_CFGR1_CHSELRMOD (1 << 21)
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@ -57,6 +57,16 @@
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#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4)
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/* Register values */
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/* ADC_CFGR1 Values ---------------------------------------------------------*/
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/** ALIGN: Data alignment */
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#define ADC_CFGR1_ALIGN (1 << 5)
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/* EXTSEL[2:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/* ADC_CFGR2 Values ---------------------------------------------------------*/
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#define ADC_CFGR2_CKMODE_SHIFT 30
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@ -62,6 +62,16 @@
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/* ADVREGEN: Voltage regulator enable bit */
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#define ADC_CR_ADVREGEN (1 << 28)
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/* ADC_CFGR1 Values ---------------------------------------------------------*/
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/** ALIGN: Data alignment */
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#define ADC_CFGR1_ALIGN (1 << 5)
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/* EXTSEL[2:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/****************************************************************************/
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/* ADC_SMPRx ADC Sample Time Selection for Channels */
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