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stm32f3: adc-v2: extract sample time settings 

adc-v2 "multi" needs per channel sampling time settings.  adc-v2 "single" only
sets the sampling time for all channels.
This commit is contained in:
Karl Palsson 2016-03-03 22:52:09 +00:00
parent 697c975dde
commit 7210522d5c
3 changed files with 86 additions and 58 deletions
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85
lib/stm32/common/adc_common_v2_multi.c Normal file
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@ -0,0 +1,85 @@
/** @addtogroup adc_file
@author @htmlonly © @endhtmlonly
2016 Karl Palsson <karlp@tweak.net.au>
This provides the "multi" extensions to the "v2" ADC peripheral. This is those
devices that support injected channels and per channel sampling times.
At the time of writing, this is the STM32F30x and the STM32L4x
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2016 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/adc.h>
/** @brief ADC Set the Sample Time for a Single Channel
*
* The sampling time can be selected in ADC clock cycles, exact values
* depend on the device.
*
* @param[in] adc ADC block register address base @ref adc_reg_base
* @param[in] channel ADC Channel integer @ref adc_channel
* @param[in] time Sampling time selection from @ref adc_sample
*/
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
{
uint32_t reg32;
if (channel < 10) {
reg32 = ADC_SMPR1(adc);
reg32 &= ~(0x7 << (channel * 3));
reg32 |= (time << (channel * 3));
ADC_SMPR1(adc) = reg32;
} else {
reg32 = ADC_SMPR2(adc);
reg32 &= ~(0x7 << ((channel - 10) * 3));
reg32 |= (time << ((channel - 10) * 3));
ADC_SMPR2(adc) = reg32;
}
}
/** @brief ADC Set the Sample Time for All Channels
*
* The sampling time can be selected in ADC clock cycles, exact values
* depend on the device.
*
* @param[in] adc ADC block register address base @ref adc_reg_base
* @param[in] time Sampling time selection from @ref adc_sample
*/
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
{
uint8_t i;
uint32_t reg32 = 0;
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
}
ADC_SMPR1(adc) = reg32;
for (i = 10; i <= 17; i++) {
reg32 |= (time << ((i - 10) * 3));
}
ADC_SMPR2(adc) = reg32;
}

2
lib/stm32/f3/Makefile
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@ -43,7 +43,7 @@ OBJS += gpio_common_all.o gpio_common_f0234.o \
iwdg_common_all.o spi_common_all.o dma_common_l1f013.o\
timer_common_all.o timer_common_f234.o flash_common_f234.o \
flash.o exti_common_all.o rcc_common_all.o spi_common_f03.o
OBJS += adc_common_v2.o
OBJS += adc_common_v2.o adc_common_v2_multi.o
OBJS += usb.o usb_control.o usb_standard.o
OBJS += st_usbfs_core.o st_usbfs_v1.o

57
lib/stm32/f3/adc.c
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@ -449,63 +449,6 @@ void adc_start_conversion_injected(uint32_t adc)
while (ADC_CR(adc) & ADC_CR_JADSTART);
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for a Single Channel
*
* The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] channel Unsigned int8. ADC Channel integer 0..18 or from
* @ref adc_channel
* @param[in] time Unsigned int8. Sampling time selection from
* @ref adc_sample_rg
*/
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
{
uint32_t reg32;
if (channel < 10) {
reg32 = ADC_SMPR2(adc);
reg32 &= ~(0x7 << (channel * 3));
reg32 |= (time << (channel * 3));
ADC_SMPR2(adc) = reg32;
} else {
reg32 = ADC_SMPR1(adc);
reg32 &= ~(0x7 << ((channel - 10) * 3));
reg32 |= (time << ((channel - 10) * 3));
ADC_SMPR1(adc) = reg32;
}
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for All Channels
*
* The sampling time can be selected in ADC clock cycles from 1.5 to 239.5,
* same for all channels.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] time Unsigned int8. Sampling time selection from
* @ref adc_sample_rg
*/
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
{
uint8_t i;
uint32_t reg32 = 0;
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
}
ADC_SMPR2(adc) = reg32;
for (i = 10; i <= 17; i++) {
reg32 |= (time << ((i - 10) * 3));
}
ADC_SMPR1(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Upper Threshold