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cm3: nvic: use separate documentation to avoid warnings on cm0 

Squelches some doxygen warnings, and makes the generated docs "right"
for each arch
This commit is contained in:
Karl Palsson 2020-01-28 22:30:39 +00:00
parent 26d6f8f77e
commit 6f25d51be6
1 changed files with 10 additions and 10 deletions
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20
lib/cm3/nvic.c
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@ -128,27 +128,27 @@ uint8_t nvic_get_irq_enabled(uint8_t irqn)
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
/*---------------------------------------------------------------------------*/
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/** @brief NVIC Set Interrupt Priority
*
* CM3, CM4:
*
* There are 16 priority levels only, given by the upper four bits of the
* priority byte, as required by ARM standards. The priority levels are
* interpreted according to the pre-emptive priority grouping set in the
* SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done
* in @ref scb_set_priority_grouping.
*
* CM0:
* in @ref scb_set_priority_grouping,
* @param[in] irqn Interrupt number @ref CM3_nvic_defines_irqs
* @param[in] priority Interrupt priority (0 ... 255 in steps of 16)
*/
#else
/** NVIC Set Interrupt Priority.
*
* There are 4 priority levels only, given by the upper two bits of the
* priority byte, as required by ARM standards. No grouping available.
*
* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
* @param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of
* 16)
* @param[in] irqn Interrupt number @ref CM3_nvic_defines_irqs
* @param[in] priority Interrupt priority (0 ... 255 in steps of 16)
*/
#endif
void nvic_set_priority(uint8_t irqn, uint8_t priority)
{
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the