[ETH/PHY] Add support for LAN87XX family of PHYs
This commit is contained in:
Frantisek Burian
Karl Palsson
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/** @defgroup ethernet_phy_lan87xx_defines PHY LAN8710 Defines
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*
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* @brief <b>Defined Constants and Types for the Ethernet PHY LAN87xx chips</b>
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*
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* @ingroup ETH
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2014 Frantisek Burian <BuFran@seznam.cz>
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*
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* @date 6 February 2014
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PHY_LAN87XX_H
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#define LIBOPENCM3_PHY_LAN87XX_H
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#include <libopencm3/ethernet/phy.h>
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/**@{*/
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/*
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* Architecture availability:
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*
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* A stands for LAN8700
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* B stands for LAN8710A
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* C stands for LAN8720A
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* D stands for LAN8740A
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* E stands for LAN8741A
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* F stands for LAN8742A
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*/
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/*****************************************************************************/
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/* Register definitions */
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/*****************************************************************************/
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#define LAN87XX_BCR 0x00 /* ABCDEF */
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#define LAN87XX_BSR 0x01 /* ABCDEF */
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#define LAN87XX_PID1 0x02 /* ABCDEF */
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#define LAN87XX_PID2 0x03 /* ABCDEF */
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#define LAN87XX_ANA 0x04 /* ABCDEF */
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#define LAN87XX_ANLPA 0x05 /* ABCDEF */
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#define LAN87XX_ANE 0x06 /* ABCDEF */
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#define LAN87XX_ANNPTX 0x07 /* ---DEF */
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#define LAN87XX_ANNPRX 0x08 /* ---DEF */
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#define LAN87XX_MMDACR 0x0D /* ---DEF */
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#define LAN87XX_MMDADR 0x0E /* ---DEF */
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#define LAN87XX_REVISION 0x10 /* A----- */
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#define LAN87XX_EDPDNLP 0x10 /* ---DEF */
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#define LAN87XX_MCS 0x11 /* ABCDEF */
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#define LAN87XX_SM 0x12 /* ABCDEF */
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#define LAN87XX_TDRDCR 0x18 /* ---D-F */
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#define LAN87XX_TDRCSR 0x19 /* ---D-F */
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#define LAN87XX_ERRCNT 0x1A /* -BCDEF */
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#define LAN87XX_CSR 0x1B /* ABCDEF */
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#define LAN87XX_CBLN 0x1C /* ---D-F */
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#define LAN87XX_ISR 0x1D /* ABCDEF */
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#define LAN87XX_IMR 0x1E /* ABCDEF */
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#define LAN87XX_SCSR 0x1F /* ABCDEF */
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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/* LAN87XX_BCR --------------------------------------------------------------*/
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/* LAN87XX_BSR --------------------------------------------------------------*/
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/* LAN87XX_PID1 -------------------------------------------------------------*/
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/* LAN87XX_PID2 -------------------------------------------------------------*/
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/* LAN87XX_ANA --------------------------------------------------------------*/
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/* LAN87XX_ANLPA ------------------------------------------------------------*/
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/* LAN87XX_ANE --------------------------------------------------------------*/
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/* LAN87XX_ANNPTX -----------------------------------------------------------*/
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/* LAN87XX_ANNPRX -----------------------------------------------------------*/
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/* LAN87XX_MMDACR -----------------------------------------------------------*/
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/* the MMD provides register access into bare PHY chip. MMD provides its own
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* register address space, completely different between devices.
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* It should be implemented later.
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*/
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#define LAN87XX_MMDACR_FUNC_SHIFT 14 /* ---DEF */
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#define LAN87XX_MMDACR_FUNC (3 << LAN87XX_MMDACR_FUNC_SHIFT)
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#define LAN87XX_MMDACR_FUNC_ADDRESS (0 << LAN87XX_MMDACR_FUNC_SHIFT)
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#define LAN87XX_MMDACR_FUNC_DATA (1 << LAN87XX_MMDACR_FUNC_SHIFT)
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#define LAN87XX_MMDACR_DEVAD (31 << 0) /* ---DEF */
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#define LAN87XX_MMDACR_DEVAD_PCS (3 << 0) /* ---DEF */
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#define LAN87XX_MMDACR_DEVAD_ANN (7 << 0) /* ---DE- */
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#define LAN87XX_MMDACR_DEVAD_VENDOR (30 << 0) /* ---DE- */
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/* LAN87XX_MMDADR -----------------------------------------------------------*/
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/* LAN87XX_REVISION ---------------------------------------------------------*/
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/* note this register is valid only on original LAN8700 */
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/* LAN87XX_EDPDNLP ----------------------------------------------------------*/
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/* note this register is valid only on newer than original LAN8700 */
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#define LAN87XX_EDPDNLP_TXEN (1 << 15) /* ---DEF */
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#define LAN87XX_EDPDNLP_TXTIM_SHIFT 13 /* ---DEF */
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#define LAN87XX_EDPDNLP_TXTIM (3<<LAN87XX_EDPDNLP_TXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_TXTIM_1024MS (0<<LAN87XX_EDPDNLP_TXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_TXTIM_0768MS (1<<LAN87XX_EDPDNLP_TXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_TXTIM_0512MS (2<<LAN87XX_EDPDNLP_TXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_TXTIM_0256MS (3<<LAN87XX_EDPDNLP_TXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_RXWAKEEN (1 << 12) /* ---DEF */
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#define LAN87XX_EDPDNLP_RXTIM_SHIFT 10 /* ---DEF */
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#define LAN87XX_EDPDNLP_RXTIM (3<<LAN87XX_EDPDNLP_RXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_RXTIM_0064MS (0<<LAN87XX_EDPDNLP_RXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_RXTIM_0256MS (1<<LAN87XX_EDPDNLP_RXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_RXTIM_0512MS (2<<LAN87XX_EDPDNLP_RXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_RXTIM_1024MS (3<<LAN87XX_EDPDNLP_RXTIM_SHIFT)
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#define LAN87XX_EDPDNLP_EXTCROSSOVER (1 << 1) /* ---DEF */
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#define LAN87XX_EDPDNLP_EXTMANCROSSOVER (1 << 0) /* ---DEF */
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/* LAN87XX_MCS --------------------------------------------------------------*/
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#define LAN87XX_MCS_EDPWRDOWN (1 << 13) /* ABCDEF */
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#define LAN87XX_MCS_LOWSQEN (1 << 11) /* A----- */
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#define LAN87XX_MCS_MDPREBP (1 << 10) /* A----- */
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#define LAN87XX_MCS_FARLOOPBACK (1 << 9) /* ABCDEF */
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#define LAN87XX_MCS_ALTINT (1 << 6) /* ABCDEF */
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#define LAN87XX_MCS_PHYADBP (1 << 3) /* A----- */
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#define LAN87XX_MCS_FORCELINK (1 << 2) /* A----- */
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#define LAN87XX_MCS_ENERGYON (1 << 1) /* ABCDEF */
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/* LAN87XX_SM ---------------------------------------------------------------*/
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/* @LAN8720A: Should write as 1 (only RMII supported) */
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/* @LAN8742A: Don't care bit on LAN8742A (only RMII supported) */
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#define LAN87XX_SM_MIIMODE (1 << 14) /* ABCDE- */
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#define LAN87XX_SM_MIIMODE_MII (0 << 14) /* ABCDE- */
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#define LAN87XX_SM_MIIMODE_RMII (1 << 14) /* ABCDE- */
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#define LAN87XX_SM_MODE_SHIFT 5 /* ABCDEF */
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#define LAN87XX_SM_MODE (7 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_10HD (0 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_10FD (1 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_100HD (2 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_100FD (3 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_100HD_AN (4 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_REPEATER (5 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_POWERDOWN (6 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_MODE_ALL (7 << LAN87XX_SM_MODE_SHIFT)
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#define LAN87XX_SM_PHYAD (0x1F << 0) /* ABCDEF */
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/* LAN87XX_TDRDCR -----------------------------------------------------------*/
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/*this register is applicable only on @LAN8740A and @LAN8742A */
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#define LAN87XX_TDRDCR_DELAY (15 << 0) /* ---D-F */
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#define LAN87XX_TDRDCR_DELAY (15 << 0) /* ---D-F */
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#define LAN87XX_TDRDCR_LBCR_SHIFT 12 /* ---D-F */
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#define LAN87XX_TDRDCR_LBCR (7 << LAN87XX_TDRDCR_LBCR_SHIFT)
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#define LAN87XX_TDRDCR_LPAT_SHIFT 6 /* ---D-F */
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#define LAN87XX_TDRDCR_LPAT (7 << LAN87XX_TDRDCR_LPAT_SHIFT)
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#define LAN87XX_TDRDCR_HPAT_SHIFT 0 /* ---D-F */
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#define LAN87XX_TDRDCR_HPAT (7 << LAN87XX_TDRDCR_HPAT_SHIFT)
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/* LAN87XX_TDRCSR -----------------------------------------------------------*/
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/*this register is applicable only on @LAN8740A and @LAN8742A */
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#define LAN87XX_TDRCSR_ENABLE (1 << 15) /* ---D-F */
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#define LAN87XX_TDRCSR_ADFILTER (1 << 14) /* ---D-F */
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#define LAN87XX_TDRCSR_COND_SHIFT 9 /* ---D-F */
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#define LAN87XX_TDRCSR_COND_DEFAULT (0 << LAN87XX_TDRCSR_COND_SHIFT)
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#define LAN87XX_TDRCSR_COND_SHORTED (1 << LAN87XX_TDRCSR_COND_SHIFT)
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#define LAN87XX_TDRCSR_COND_OPEN (2 << LAN87XX_TDRCSR_COND_SHIFT)
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#define LAN87XX_TDRCSR_COND_MATCH (3 << LAN87XX_TDRCSR_COND_SHIFT)
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#define LAN87XX_TDRCSR_STATUS (1 << 8) /* ---D-F */
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/* note for @LAN8742A the coefficients to meters are in table in DS page 55 */
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/* note for @LAN8740A the coefficients to meters are in table in DS page 58 */
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#define LAN87XX_TDRCSR_LENGTH (15 << 0) /* ---D-F */
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/* LAN87XX_ERRCNT -----------------------------------------------------------*/
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/* 16bit register not applicable for old @LAN8700 */
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/* LAN87XX_CSR --------------------------------------------------------------*/
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#define LAN87XX_CSR_AMDIXCTRL (1 << 15) /* ABCDEF */
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#define LAN87XX_CSR_CH_SELECT (1 << 13) /* ABCDEF */
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#define LAN87XX_CSR_SQEOFF (1 << 11) /* ABCDEF */
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#define LAN87XX_CSR_XPOL (1 << 4) /* ABCDEF */
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/* LAN87XX_CBLN --------------------------------------------------------------*/
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/* register applicable only on @LAN8740A and LAN8742A */
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#define LAN87XX_CBLN_CBLN_SHIFT 12 /* ---D-F */
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#define LAN87XX_CBLN_CBLN (15 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_006M (4 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_017M (5 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_027M (6 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_038M (7 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_049M (8 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_059M (9 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_070M (10 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_081M (11 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_091M (12 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_102M (13 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_113M (14 << LAN87XX_CBLN_CBLN_SHIFT)
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#define LAN87XX_CBLN_CBLN_123M (15 << LAN87XX_CBLN_CBLN_SHIFT)
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/* LAN87XX_ISR --------------------------------------------------------------*/
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#define LAN87XX_ISR_WOLF (1 << 8) /* ---D-F */
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#define LAN87XX_ISR_ENERGYONF (1 << 7) /* ABCDEF */
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#define LAN87XX_ISR_ANCOMPF (1 << 6) /* ABCDEF */
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#define LAN87XX_ISR_RFAULTF (1 << 5) /* ABCDEF */
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#define LAN87XX_ISR_LINKDOWNF (1 << 4) /* ABCDEF */
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#define LAN87XX_ISR_ANLPACKF (1 << 3) /* ABCDEF */
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#define LAN87XX_ISR_PDFAULTF (1 << 2) /* ABCDEF */
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#define LAN87XX_ISR_ANPAGEF (1 << 1) /* ABCDEF */
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/* LAN8710_IMR --------------------------------------------------------------*/
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#define LAN87XX_IMR_WOLE (1 << 8) /* ---D-F */
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#define LAN87XX_IMR_ENERGYONE (1 << 7) /* ABCDEF */
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#define LAN87XX_IMR_ANCOMPE (1 << 6) /* ABCDEF */
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#define LAN87XX_IMR_RFAULTE (1 << 5) /* ABCDEF */
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#define LAN87XX_IMR_LINKDOWNE (1 << 4) /* ABCDEF */
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#define LAN87XX_IMR_ANLPACKE (1 << 3) /* ABCDEF */
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#define LAN87XX_IMR_PDFAULTE (1 << 2) /* ABCDEF */
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#define LAN87XX_IMR_ANPAGEE (1 << 1) /* ABCDEF */
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/* LAN8710_SCSR -------------------------------------------------------------*/
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#define LAN87XX_SCSR_AUTODONE (1 << 12) /* ABCDEF */
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#define LAN87XX_SCSR_GPO2 (1 << 9) /* A----- */
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#define LAN87XX_SCSR_GPO1 (1 << 8) /* A----- */
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#define LAN87XX_SCSR_GPO0 (1 << 7) /* A----- */
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/* @LAN8742A: should write as 1 */
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/* @LAN8720A: should write as 1 */
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#define LAN87XX_SCSR_ENABLE4B5B (1 << 6) /* AB-DE- */
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#define LAN87XX_SCSR_SPEED_SHIFT 2 /* ABCDEF */
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#define LAN87XX_SCSR_SPEED (7 << LAN87XX_SCSR_SPEED_SHIFT)
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#define LAN87XX_SCSR_SPEED_10HD (1 << LAN87XX_SCSR_SPEED_SHIFT)
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#define LAN87XX_SCSR_SPEED_100HD (2 << LAN87XX_SCSR_SPEED_SHIFT)
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#define LAN87XX_SCSR_SPEED_10FD (5 << LAN87XX_SCSR_SPEED_SHIFT)
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#define LAN87XX_SCSR_SPEED_100FD (6 << LAN87XX_SCSR_SPEED_SHIFT)
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#define LAN87XX_SCSR_NOSCRAMBLE (1 << 0) /* A----- */
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/*****************************************************************************/
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/* API definitions */
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/*****************************************************************************/
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/*****************************************************************************/
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/* API Functions */
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/*****************************************************************************/
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/**@}*/
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#endif /* LIBOPENCM3_PHY_LAN87XX_H__ */
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