From 61f2cb3f993c0f00504e46be48de8c535c9408b4 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 30 Nov 2012 13:13:41 +1030 Subject: [PATCH] Move STM32F1 DMA files to respective common directories This sets the stage for adding DMA to STM32F3xx (when added) and STM32L1xx as the controller appears to be identical in these. --- doc/stm32f1/Doxyfile | 12 +- .../libopencm3/stm32/common/dma_common_f13.h | 388 ++++++++++++++++ include/libopencm3/stm32/f1/dma.h | 372 +-------------- lib/stm32/common/dma_common_f13.c | 433 ++++++++++++++++++ lib/stm32/f1/Makefile | 4 +- lib/stm32/f1/dma.c | 424 +---------------- 6 files changed, 839 insertions(+), 794 deletions(-) create mode 100644 include/libopencm3/stm32/common/dma_common_f13.h create mode 100644 lib/stm32/common/dma_common_f13.c diff --git a/doc/stm32f1/Doxyfile b/doc/stm32f1/Doxyfile index ae83259c..914db661 100644 --- a/doc/stm32f1/Doxyfile +++ b/doc/stm32f1/Doxyfile @@ -16,18 +16,18 @@ WARN_LOGFILE = doxygen_stm32f1.log INPUT = ../../include/libopencm3/license.dox \ - ../../include/libopencm3/stm32/f1 \ - ../../include/libopencm3/stm32/common/gpio_common_all.h + ../../include/libopencm3/stm32/f1 \ + ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f1 \ - ../../lib/stm32/common/gpio_common_all.c + ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f1/usb.h \ - ../../include/libopencm3/stm32/f1/usb_desc.h + ../../include/libopencm3/stm32/f1/usb_desc.h -EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c +EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c -LAYOUT_FILE = DoxygenLayout_stm32f1.xml +LAYOUT_FILE = DoxygenLayout_stm32f1.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html diff --git a/include/libopencm3/stm32/common/dma_common_f13.h b/include/libopencm3/stm32/common/dma_common_f13.h new file mode 100644 index 00000000..964bdf1a --- /dev/null +++ b/include/libopencm3/stm32/common/dma_common_f13.h @@ -0,0 +1,388 @@ +/** @addtogroup dma_defines */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_DMA_COMMON_F13_H +#define LIBOPENCM3_DMA_COMMON_F13_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA register base adresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* --- DMA registers ------------------------------------------------------- */ + +/* DMA interrupt status register (DMAx_ISR) */ +#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA1_ISR DMA_ISR(DMA1) +#define DMA2_ISR DMA_ISR(DMA2) + +/* DMA interrupt flag clear register (DMAx_IFCR) */ +#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) +#define DMA1_IFCR DMA_IFCR(DMA1) +#define DMA2_IFCR DMA_IFCR(DMA2) + +/* DMA channel configuration register (DMAx_CCRy) */ +#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CCR(channel) DMA_CCR(DMA1, channel) +#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1) +#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2) +#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3) +#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4) +#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5) +#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6) +#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7) + +#define DMA2_CCR(channel) DMA_CCR(DMA2, channel) +#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1) +#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2) +#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3) +#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4) +#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) + +/* DMA number of data register (DMAx_CNDTRy) */ +#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) +#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1) +#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2) +#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3) +#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4) +#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5) +#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6) +#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7) + +#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel) +#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1) +#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2) +#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3) +#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4) +#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) + +/* DMA peripheral address register (DMAx_CPARy) */ +#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) +#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1) +#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2) +#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3) +#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4) +#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5) +#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6) +#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7) + +#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel) +#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1) +#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2) +#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3) +#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4) +#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5) + +/* DMA memory address register (DMAx_CMARy) */ + +#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) +#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1) +#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2) +#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3) +#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4) +#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5) +#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6) +#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7) + +#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel) +#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1) +#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2) +#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3) +#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4) +#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5) + +/* --- DMA_ISR values ------------------------------------------------------ */ + +/* --- DMA Interrupt Flag offset values ------------------------------------- */ +/* These are based on every interrupt flag and flag clear being at the same relative location */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag group. +@ingroup dma_defines + +@{*/ +/** Transfer Error Interrupt Flag */ +#define DMA_TEIF (1 << 3) +/** Half Transfer Interrupt Flag */ +#define DMA_HTIF (1 << 2) +/** Transfer Complete Interrupt Flag */ +#define DMA_TCIF (1 << 1) +/** Global Interrupt Flag */ +#define DMA_GIF (1 << 0) +/**@}*/ + +/* Offset within interrupt status register to start of channel interrupt flag field */ +#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) +#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF) +#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel) + +/* TEIF: Transfer error interrupt flag */ +#define DMA_ISR_TEIF_BIT DMA_ISR_TEIF +#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) +#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) +#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3) +#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4) +#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5) +#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6) +#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) + +/* HTIF: Half transfer interrupt flag */ +#define DMA_ISR_HTIF_BIT DMA_HTIF +#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) +#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) +#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3) +#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4) +#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5) +#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6) +#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) + +/* TCIF: Transfer complete interrupt flag */ +#define DMA_ISR_TCIF_BIT DMA_TCIF +#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) +#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) +#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3) +#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4) +#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5) +#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6) +#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) + +/* GIF: Global interrupt flag */ +#define DMA_ISR_GIF_BIT DMA_GIF +#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) +#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) +#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3) +#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4) +#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5) +#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6) +#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7) + +/* --- DMA_IFCR values ----------------------------------------------------- */ + +/* CTEIF: Transfer error clear */ +#define DMA_IFCR_CTEIF_BIT DMA_TEIF +#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3) +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4) +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5) +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6) +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) + +/* CHTIF: Half transfer clear */ +#define DMA_IFCR_CHTIF_BIT DMA_HTIF +#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3) +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4) +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5) +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6) +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) + +/* CTCIF: Transfer complete clear */ +#define DMA_IFCR_CTCIF_BIT DMA_TCIF +#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3) +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4) +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5) +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6) +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) + +/* CGIF: Global interrupt clear */ +#define DMA_IFCR_CGIF_BIT DMA_GIF +#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3) +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4) +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5) +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6) +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) + +/* Clear interrupts mask */ +#define DMA_IFCR_CIF_BIT 0xF +#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) +#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) +#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3) +#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4) +#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5) +#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6) +#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7) + +/* --- DMA_CCRx generic values --------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +/** @defgroup dma_ch_pri DMA Channel Priority Levels +@ingroup dma_defines + +@{*/ +#define DMA_CCR_PL_LOW (0x0 << 12) +#define DMA_CCR_PL_MEDIUM (0x1 << 12) +#define DMA_CCR_PL_HIGH (0x2 << 12) +#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) +/**@}*/ +#define DMA_CCR_PL_MASK (0x3 << 12) +#define DMA_CCR_PL_SHIFT 12 + +/* MSIZE[11:10]: Memory size */ +/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width +@ingroup dma_defines + +@{*/ +#define DMA_CCR_MSIZE_8BIT (0x0 << 10) +#define DMA_CCR_MSIZE_16BIT (0x1 << 10) +#define DMA_CCR_MSIZE_32BIT (0x2 << 10) +/**@}*/ +#define DMA_CCR_MSIZE_MASK (0x3 << 10) +#define DMA_CCR_MSIZE_SHIFT 10 + +/* PSIZE[9:8]: Peripheral size */ +/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width +@ingroup dma_defines + +@{*/ +#define DMA_CCR_PSIZE_8BIT (0x0 << 8) +#define DMA_CCR_PSIZE_16BIT (0x1 << 8) +#define DMA_CCR_PSIZE_32BIT (0x2 << 8) +/**@}*/ +#define DMA_CCR_PSIZE_MASK (0x3 << 8) +#define DMA_CCR_PSIZE_SHIFT 8 + +/* MINC: Memory increment mode */ +#define DMA_CCR_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR_EN (1 << 0) + +/* --- DMA_CNDTRx values --------------------------------------------------- */ + +/* NDT[15:0]: Number of data to transfer */ + +/* --- DMA_CPARx values ---------------------------------------------------- */ + +/* PA[31:0]: Peripheral address */ + +/* --- DMA_CMARx values ---------------------------------------------------- */ + +/* MA[31:0]: Memory address */ + +/* --- Generic values ------------------------------------------------------ */ + +/** @defgroup dma_ch DMA Channel Number +@ingroup dma_defines + +@{*/ +#define DMA_CHANNEL1 1 +#define DMA_CHANNEL2 2 +#define DMA_CHANNEL3 3 +#define DMA_CHANNEL4 4 +#define DMA_CHANNEL5 5 +#define DMA_CHANNEL6 6 +#define DMA_CHANNEL7 7 +/**@}*/ + +/* --- function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dma_channel_reset(u32 dma, u8 channel); +void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts); +bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts); +void dma_enable_mem2mem_mode(u32 dma, u8 channel); +void dma_set_priority(u32 dma, u8 channel, u32 prio); +void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size); +void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size); +void dma_enable_memory_increment_mode(u32 dma, u8 channel); +void dma_disable_memory_increment_mode(u32 dma, u8 channel); +void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); +void dma_disable_peripheral_increment_mode(u32 dma, u8 channel); +void dma_enable_circular_mode(u32 dma, u8 channel); +void dma_set_read_from_peripheral(u32 dma, u8 channel); +void dma_set_read_from_memory(u32 dma, u8 channel); +void dma_enable_transfer_error_interrupt(u32 dma, u8 channel); +void dma_disable_transfer_error_interrupt(u32 dma, u8 channel); +void dma_enable_half_transfer_interrupt(u32 dma, u8 channel); +void dma_disable_half_transfer_interrupt(u32 dma, u8 channel); +void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel); +void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel); +void dma_enable_channel(u32 dma, u8 channel); +void dma_disable_channel(u32 dma, u8 channel); +void dma_set_peripheral_address(u32 dma, u8 channel, u32 address); +void dma_set_memory_address(u32 dma, u8 channel, u32 address); +void dma_set_number_of_data(u32 dma, u8 channel, u16 number); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h index 6257394c..4af8f435 100644 --- a/include/libopencm3/stm32/f1/dma.h +++ b/include/libopencm3/stm32/f1/dma.h @@ -7,17 +7,16 @@ @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies -@date 18 August 2012 +@date 30 November 2012 LGPL License Terms @ref lgpl_license */ + /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Piotr Esden-Tempski - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -32,372 +31,11 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -/**@{*/ - #ifndef LIBOPENCM3_DMA_H #define LIBOPENCM3_DMA_H -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* DMA register base adresses (for convenience) */ -#define DMA1 DMA1_BASE -#define DMA2 DMA2_BASE - -/* --- DMA registers ------------------------------------------------------- */ - -/* DMA interrupt status register (DMAx_ISR) */ -#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) -#define DMA1_ISR DMA_ISR(DMA1) -#define DMA2_ISR DMA_ISR(DMA2) - -/* DMA interrupt flag clear register (DMAx_IFCR) */ -#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) -#define DMA1_IFCR DMA_IFCR(DMA1) -#define DMA2_IFCR DMA_IFCR(DMA2) - -/* DMA channel configuration register (DMAx_CCRy) */ -#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CCR(channel) DMA_CCR(DMA1, channel) -#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1) -#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2) -#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3) -#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4) -#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5) -#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6) -#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7) - -#define DMA2_CCR(channel) DMA_CCR(DMA2, channel) -#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1) -#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2) -#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3) -#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4) -#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) - -/* DMA number of data register (DMAx_CNDTRy) */ -#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) -#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1) -#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2) -#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3) -#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4) -#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5) -#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6) -#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7) - -#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel) -#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1) -#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2) -#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3) -#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4) -#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) - -/* DMA peripheral address register (DMAx_CPARy) */ -#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) -#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1) -#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2) -#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3) -#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4) -#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5) -#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6) -#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7) - -#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel) -#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1) -#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2) -#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3) -#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4) -#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5) - -/* DMA memory address register (DMAx_CMARy) */ - -#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) -#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1) -#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2) -#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3) -#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4) -#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5) -#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6) -#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7) - -#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel) -#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1) -#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2) -#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3) -#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4) -#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5) - -/* --- DMA_ISR values ------------------------------------------------------ */ - -/* --- DMA Interrupt Flag offset values ------------------------------------- */ -/* These are based on every interrupt flag and flag clear being at the same relative location */ -/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group. -@ingroup STM32F1xx_dma_defines - -@{*/ -/** Transfer Error Interrupt Flag */ -#define DMA_TEIF (1 << 3) -/** Half Transfer Interrupt Flag */ -#define DMA_HTIF (1 << 2) -/** Transfer Complete Interrupt Flag */ -#define DMA_TCIF (1 << 1) -/** Global Interrupt Flag */ -#define DMA_GIF (1 << 0) -/**@}*/ - -/* Offset within interrupt status register to start of stream interrupt flag field */ -#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) -#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF) -#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel) - -/* TEIF: Transfer error interrupt flag */ -#define DMA_ISR_TEIF_BIT DMA_ISR_TEIF -#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) -#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) -#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3) -#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4) -#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5) -#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6) -#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) - -/* HTIF: Half transfer interrupt flag */ -#define DMA_ISR_HTIF_BIT DMA_HTIF -#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) -#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) -#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3) -#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4) -#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5) -#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6) -#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) - -/* TCIF: Transfer complete interrupt flag */ -#define DMA_ISR_TCIF_BIT DMA_TCIF -#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) -#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) -#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3) -#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4) -#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5) -#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6) -#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) - -/* GIF: Global interrupt flag */ -#define DMA_ISR_GIF_BIT DMA_GIF -#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) -#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) -#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3) -#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4) -#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5) -#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6) -#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7) - -/* --- DMA_IFCR values ----------------------------------------------------- */ - -/* CTEIF: Transfer error clear */ -#define DMA_IFCR_CTEIF_BIT DMA_TEIF -#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) -#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) -#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3) -#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4) -#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5) -#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6) -#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) - -/* CHTIF: Half transfer clear */ -#define DMA_IFCR_CHTIF_BIT DMA_HTIF -#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) -#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) -#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3) -#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4) -#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5) -#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6) -#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) - -/* CTCIF: Transfer complete clear */ -#define DMA_IFCR_CTCIF_BIT DMA_TCIF -#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) -#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) -#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3) -#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4) -#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5) -#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6) -#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) - -/* CGIF: Global interrupt clear */ -#define DMA_IFCR_CGIF_BIT DMA_GIF -#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) -#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) -#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3) -#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4) -#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5) -#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6) -#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) - -/* Clear interrupts mask */ -#define DMA_IFCR_CIF_BIT 0xF -#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) -#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) -#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3) -#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4) -#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5) -#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6) -#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7) - -/* --- DMA_CCRx generic values --------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -/** @defgroup dma_ch_pri DMA Channel Priority Levels -@ingroup STM32F1xx_dma_defines - -@{*/ -#define DMA_CCR_PL_LOW (0x0 << 12) -#define DMA_CCR_PL_MEDIUM (0x1 << 12) -#define DMA_CCR_PL_HIGH (0x2 << 12) -#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) -/**@}*/ -#define DMA_CCR_PL_MASK (0x3 << 12) -#define DMA_CCR_PL_SHIFT 12 - -/* MSIZE[11:10]: Memory size */ -/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width -@ingroup STM32F1xx_dma_defines - -@{*/ -#define DMA_CCR_MSIZE_8BIT (0x0 << 10) -#define DMA_CCR_MSIZE_16BIT (0x1 << 10) -#define DMA_CCR_MSIZE_32BIT (0x2 << 10) -/**@}*/ -#define DMA_CCR_MSIZE_MASK (0x3 << 10) -#define DMA_CCR_MSIZE_SHIFT 10 - -/* PSIZE[9:8]: Peripheral size */ -/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width -@ingroup STM32F1xx_dma_defines - -@{*/ -#define DMA_CCR_PSIZE_8BIT (0x0 << 8) -#define DMA_CCR_PSIZE_16BIT (0x1 << 8) -#define DMA_CCR_PSIZE_32BIT (0x2 << 8) -/**@}*/ -#define DMA_CCR_PSIZE_MASK (0x3 << 8) -#define DMA_CCR_PSIZE_SHIFT 8 - -/* MINC: Memory increment mode */ -#define DMA_CCR_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR_EN (1 << 0) - -/* --- DMA_CNDTRx values --------------------------------------------------- */ - -/* NDT[15:0]: Number of data to transfer */ - -/* --- DMA_CPARx values ---------------------------------------------------- */ - -/* PA[31:0]: Peripheral address */ - -/* --- DMA_CMARx values ---------------------------------------------------- */ - -/* MA[31:0]: Memory address */ - -/* --- Generic values ------------------------------------------------------ */ - -/** @defgroup dma_ch DMA Channel Number -@ingroup STM32F1xx_dma_defines - -@{*/ -#define DMA_CHANNEL1 1 -#define DMA_CHANNEL2 2 -#define DMA_CHANNEL3 3 -#define DMA_CHANNEL4 4 -#define DMA_CHANNEL5 5 -#define DMA_CHANNEL6 6 -#define DMA_CHANNEL7 7 -/**@}*/ - -/* --- function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void dma_channel_reset(u32 dma, u8 channel); -void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts); -bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts); -void dma_enable_mem2mem_mode(u32 dma, u8 channel); -void dma_set_priority(u32 dma, u8 channel, u32 prio); -void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size); -void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size); -void dma_enable_memory_increment_mode(u32 dma, u8 channel); -void dma_disable_memory_increment_mode(u32 dma, u8 channel); -void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); -void dma_disable_peripheral_increment_mode(u32 dma, u8 channel); -void dma_enable_circular_mode(u32 dma, u8 channel); -void dma_set_read_from_peripheral(u32 dma, u8 channel); -void dma_set_read_from_memory(u32 dma, u8 channel); -void dma_enable_transfer_error_interrupt(u32 dma, u8 channel); -void dma_disable_transfer_error_interrupt(u32 dma, u8 channel); -void dma_enable_half_transfer_interrupt(u32 dma, u8 channel); -void dma_disable_half_transfer_interrupt(u32 dma, u8 channel); -void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel); -void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel); -void dma_enable_channel(u32 dma, u8 channel); -void dma_disable_channel(u32 dma, u8 channel); -void dma_set_peripheral_address(u32 dma, u8 channel, u32 address); -void dma_set_memory_address(u32 dma, u8 channel, u32 address); -void dma_set_number_of_data(u32 dma, u8 channel, u16 number); -void dma_clear_flag(u32 dma, u32 flag); - -END_DECLS +#include +#include #endif -/**@}*/ diff --git a/lib/stm32/common/dma_common_f13.c b/lib/stm32/common/dma_common_f13.c new file mode 100644 index 00000000..0a708aa6 --- /dev/null +++ b/lib/stm32/common/dma_common_f13.c @@ -0,0 +1,433 @@ +/** @addtogroup dma_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +This library supports the DMA Control System in the STM32 series of ARM Cortex +Microcontrollers by ST Microelectronics. + +Up to two DMA controllers are supported. 12 DMA channels are allocated 7 to +the first DMA controller and 5 to the second. Each channel is connected to +between 3 and 6 hardware peripheral DMA signals in a logical OR arrangement. + +DMA transfers can be configured to occur between peripheral and memory in +any combination including memory to memory. Circular mode transfers are +also supported in transfers involving a peripheral. An arbiter is provided +to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit +words. + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Reset + +The channel is disabled and configuration registers are cleared. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_channel_reset(u32 dma, u8 channel) +{ + /* Disable channel. */ + DMA_CCR(dma, channel) &= ~DMA_CCR_EN; + /* Reset config bits. */ + DMA_CCR(dma, channel) = 0; + /* Reset data transfer number. */ + DMA_CNDTR(dma, channel) = 0; + /* Reset peripheral address. */ + DMA_CPAR(dma, channel) = 0; + /* Reset memory address. */ + DMA_CMAR(dma, channel) = 0; + /* Reset interrupt flags. */ + DMA_IFCR(dma) |= DMA_IFCR_CIF(channel); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Clear Interrupt Flag + +The interrupt flag for the channel is cleared. More than one interrupt for the +same channel may be cleared by using the logical OR of the interrupt flags. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: @ref dma_ch +@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset +*/ + +void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts) +{ +/* Get offset to interrupt flag location in channel field */ + u32 flags = (interrupts << DMA_FLAG_OFFSET(channel)); + DMA_IFCR(dma) = flags; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Read Interrupt Flag + +The interrupt flag for the channel is returned. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: @ref dma_ch +@param[in] interrupt unsigned int32. Interrupt number: @ref dma_ch +@returns bool interrupt flag is set. +*/ + +bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt) +{ +/* get offset to interrupt flag location in channel field. */ + u32 flag = (interrupt << DMA_FLAG_OFFSET(channel)); + return ((DMA_ISR(dma) & flag) > 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Memory to Memory Transfers + +Memory to memory transfers do not require a trigger to activate each transfer. +Transfers begin immediately the channel has been enabled, and proceed without +intervention. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_mem2mem_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM; + DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Set Priority + +Channel Priority has four levels: low to very high. This has precedence over the +hardware priority. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] prio unsigned int32. Priority level @ref dma_ch_pri. +*/ + +void dma_set_priority(u32 dma, u8 channel, u32 prio) +{ + DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK); + DMA_CCR(dma, channel) |= prio; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Set Memory Word Width + +Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for +alignment information if the source and destination widths do not match. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth. +*/ + +void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size) +{ + + DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK); + DMA_CCR(dma, channel) |= mem_size; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Set Peripheral Word Width + +Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for +alignment information if the source and destination widths do not match, or +if the peripheral does not support byte or half-word writes. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth. +*/ + +void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size) +{ + DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK); + DMA_CCR(dma, channel) |= peripheral_size; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Memory Increment after Transfer + +Following each transfer the current memory address is incremented by +1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The +value held by the base memory address register is unchanged. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_memory_increment_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_MINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Memory Increment after Transfer + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_disable_memory_increment_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_MINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Peripheral Increment after Transfer + +Following each transfer the current peripheral address is incremented by +1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The +value held by the base peripheral address register is unchanged. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_peripheral_increment_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_PINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Peripheral Increment after Transfer + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_disable_peripheral_increment_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_PINC; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Memory Circular Mode + +After the number of bytes/words to be transferred has been completed, the +original transfer block size, memory and peripheral base addresses are +reloaded and the process repeats. + +@note This cannot be used with memory to memory mode, which is explictly +disabled here. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_circular_mode(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_CIRC; + DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Transfers from a Peripheral + +The data direction is set to read from a peripheral. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_set_read_from_peripheral(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_DIR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Transfers from Memory + +The data direction is set to read from memory. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_set_read_from_memory(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_DIR; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Interrupt on Transfer Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_transfer_error_interrupt(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_TEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Interrupt on Transfer Error + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_disable_transfer_error_interrupt(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Interrupt on Transfer Half Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_half_transfer_interrupt(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_HTIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Interrupt on Transfer Half Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_disable_half_transfer_interrupt(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable Interrupt on Transfer Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_TCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable Interrupt on Transfer Complete + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Enable + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_enable_channel(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) |= DMA_CCR_EN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Disable + +@note The DMA channel registers retain their values when the channel is disabled. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +*/ + +void dma_disable_channel(u32 dma, u8 channel) +{ + DMA_CCR(dma, channel) &= ~DMA_CCR_EN; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Set the Peripheral Address + +Set the address of the peripheral register to or from which data is to be transferred. +Refer to the documentation for the specific peripheral. + +@note The DMA channel must be disabled before setting this address. This function +has no effect if the channel is enabled. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] address unsigned int32. Peripheral Address. +*/ + +void dma_set_peripheral_address(u32 dma, u8 channel, u32 address) +{ + if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) + DMA_CPAR(dma, channel) = (u32) address; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Set the Base Memory Address + +@note The DMA channel must be disabled before setting this address. This function +has no effect if the channel is enabled. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] address unsigned int32. Memory Initial Address. +*/ + +void dma_set_memory_address(u32 dma, u8 channel, u32 address) +{ + if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) + DMA_CMAR(dma, channel) = (u32) address; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DMA Channel Set the Transfer Block Size + +@note The DMA channel must be disabled before setting this count value. The count +is not changed if the channel is enabled. + +@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 +@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] number unsigned int16. Number of data words to transfer (65535 maximum). +*/ + +void dma_set_number_of_data(u32 dma, u8 channel, u16 number) +{ + DMA_CNDTR(dma, channel) = number; +} +/**@}*/ + diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 25725542..b236c725 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -24,7 +24,7 @@ PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ - -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -mcpu=cortex-m3 -msoft-float -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs @@ -33,7 +33,7 @@ OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \ usb_fx07_common.o \ - gpio_common_all.o + gpio_common_all.o dma_common_f13.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/dma.c b/lib/stm32/f1/dma.c index 1f06c114..f22baef4 100644 --- a/lib/stm32/f1/dma.c +++ b/lib/stm32/f1/dma.c @@ -1,35 +1,14 @@ -/** @defgroup STM32F1xx-dma-file DMA +/** @defgroup dma_file DMA @ingroup STM32F1xx -@brief libopencm3 STM32F1xx DMA Controller +@brief libopencm3 STM32F1xx DMA -@version 1.0.0 +*/ -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 18 August 2012 - -This library supports the DMA Control System in the STM32 series of ARM Cortex -Microcontrollers by ST Microelectronics. - -Up to two DMA controllers are supported. 12 DMA channels are allocated 7 to -the first DMA controller and 5 to the second. Each channel is connected to -between 3 and 6 hardware peripheral DMA signals in a logical OR arrangement. - -DMA transfers can be configured to occur between peripheral and memory in -any combination including memory to memory. Circular mode transfers are -also supported in transfers involving a peripheral. An arbiter is provided -to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit -words. - -LGPL License Terms @ref lgpl_license - */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Thomas Otto - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -44,399 +23,6 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -/**@{*/ - -#include - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Reset - -The channel is disabled and configuration registers are cleared. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_channel_reset(u32 dma, u8 channel) -{ - /* Disable channel. */ - DMA_CCR(dma, channel) &= ~DMA_CCR_EN; - /* Reset config bits. */ - DMA_CCR(dma, channel) = 0; - /* Reset data transfer number. */ - DMA_CNDTR(dma, channel) = 0; - /* Reset peripheral address. */ - DMA_CPAR(dma, channel) = 0; - /* Reset memory address. */ - DMA_CMAR(dma, channel) = 0; - /* Reset interrupt flags. */ - DMA_IFCR(dma) |= DMA_IFCR_CIF(channel); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Clear Interrupt Flag - -The interrupt flag for the channel is cleared. More than one interrupt for the -same channel may be cleared by using the logical OR of the interrupt flags. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: @ref dma_ch -@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset -*/ - -void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts) -{ -/* Get offset to interrupt flag location in channel field */ - u32 flags = (interrupts << DMA_FLAG_OFFSET(channel)); - DMA_IFCR(dma) = flags; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Read Interrupt Flag - -The interrupt flag for the channel is returned. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: @ref dma_ch -@param[in] interrupt unsigned int32. Interrupt number: @ref dma_ch -@returns bool interrupt flag is set. -*/ - -bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt) -{ -/* get offset to interrupt flag location in channel field. */ - u32 flag = (interrupt << DMA_FLAG_OFFSET(channel)); - return ((DMA_ISR(dma) & flag) > 0); -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Memory to Memory Transfers - -Memory to memory transfers do not require a trigger to activate each transfer. -Transfers begin immediately the channel has been enabled, and proceed without -intervention. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_mem2mem_mode(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM; - DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Set Priority - -Channel Priority has four levels: low to very high. This has precedence over the -hardware priority. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] prio unsigned int32. Priority level @ref dma_ch_pri. -*/ - -void dma_set_priority(u32 dma, u8 channel, u32 prio) -{ - DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK); - DMA_CCR(dma, channel) |= prio; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Set Memory Word Width - -Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for -alignment information if the source and destination widths do not match. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth. -*/ - -void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size) -{ - - DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK); - DMA_CCR(dma, channel) |= mem_size; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Set Peripheral Word Width - -Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for -alignment information if the source and destination widths do not match, or -if the peripheral does not support byte or half-word writes. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth. -*/ - -void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size) -{ - DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK); - DMA_CCR(dma, channel) |= peripheral_size; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Memory Increment after Transfer - -Following each transfer the current memory address is incremented by -1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The -value held by the base memory address register is unchanged. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_memory_increment_mode(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_MINC; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Disable Memory Increment after Transfer - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_disable_memory_increment_mode(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) &= ~DMA_CCR_MINC; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Peripheral Increment after Transfer - -Following each transfer the current peripheral address is incremented by -1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The -value held by the base peripheral address register is unchanged. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_peripheral_increment_mode(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_PINC; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Disable Peripheral Increment after Transfer - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_disable_peripheral_increment_mode(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) &= ~DMA_CCR_PINC; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Memory Circular Mode - -After the number of bytes/words to be transferred has been completed, the -original transfer block size, memory and peripheral base addresses are -reloaded and the process repeats. - -@note This cannot be used with memory to memory mode, which is explictly -disabled here. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_circular_mode(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_CIRC; - DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Transfers from a Peripheral - -The data direction is set to read from a peripheral. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_set_read_from_peripheral(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) &= ~DMA_CCR_DIR; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Transfers from Memory - -The data direction is set to read from memory. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_set_read_from_memory(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_DIR; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Interrupt on Transfer Error - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_transfer_error_interrupt(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_TEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Disable Interrupt on Transfer Error - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_disable_transfer_error_interrupt(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Interrupt on Transfer Half Complete - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_half_transfer_interrupt(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_HTIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Disable Interrupt on Transfer Half Complete - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_disable_half_transfer_interrupt(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable Interrupt on Transfer Complete - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_TCIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Disable Interrupt on Transfer Complete - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Enable - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_enable_channel(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) |= DMA_CCR_EN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Disable - -@note The DMA channel registers retain their values when the channel is disabled. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -*/ - -void dma_disable_channel(u32 dma, u8 channel) -{ - DMA_CCR(dma, channel) &= ~DMA_CCR_EN; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Set the Peripheral Address - -Set the address of the peripheral register to or from which data is to be transferred. -Refer to the documentation for the specific peripheral. - -@note The DMA channel must be disabled before setting this address. This function -has no effect if the channel is enabled. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] address unsigned int32. Peripheral Address. -*/ - -void dma_set_peripheral_address(u32 dma, u8 channel, u32 address) -{ - if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) - DMA_CPAR(dma, channel) = (u32) address; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Set the Base Memory Address - -@note The DMA channel must be disabled before setting this address. This function -has no effect if the channel is enabled. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] address unsigned int32. Memory Initial Address. -*/ - -void dma_set_memory_address(u32 dma, u8 channel, u32 address) -{ - if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) - DMA_CMAR(dma, channel) = (u32) address; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DMA Channel Set the Transfer Block Size - -@note The DMA channel must be disabled before setting this count value. The count -is not changed if the channel is enabled. - -@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 -@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] number unsigned int16. Number of data words to transfer (65535 maximum). -*/ - -void dma_set_number_of_data(u32 dma, u8 channel, u16 number) -{ - DMA_CNDTR(dma, channel) = number; -} - -void dma_clear_flag(u32 dma, u32 flag) -{ - DMA_ISR(dma) &= ~flag; -} -/**@}*/ +#include +#include