Added CAN bit definitions.
This commit is contained in:
Piotr Esden-Tempski
parent
77fbe48a5e
commit
618912e45f
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@ -139,4 +139,472 @@
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#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
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#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
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/* --- CAN_MCR values ------------------------------------------------------ */
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/* 31:17 Reserved, forced by hardware to 0 */
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/* DBF: Debug freeze */
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#define CAN_MCR_DBF (1 << 16)
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/* RESET: bxCAN software master reset */
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#define CAN_MCR_RESET (1 << 15)
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/* 14:8 Reserved, forced by hardware to 0 */
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/* TTCM: Time triggered communication mode */
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#define CAN_MCR_TTCM (1 << 7)
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/* ABOM: Automatic bus-off management */
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#define CAN_MCR_ABOM (1 << 6)
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/* AWUM: Automatic wakeup mode */
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#define CAN_MCR_AWUM (1 << 5)
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/* NART: No automatic retransmission */
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#define CAN_MCR_NART (1 << 4)
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/* RFLM: Receive FIFO locked mode */
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#define CAN_MCR_RFLM (1 << 3)
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/* TXFP: Transmit FIFO priority */
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#define CAN_MCR_TXFP (1 << 2)
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/* SLEEP: Sleep mode request */
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#define CAN_MCR_SLEEP (1 << 1)
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/* INRQ: Initialization request */
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#define CAN_MCR_INRQ (1 << 0)
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/* --- CAN_MSR values ------------------------------------------------------ */
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/* 31:12 Reserved, forced by hardware to 0 */
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/* RX: CAN Rx signal */
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#define CAN_MSR_RX (1 << 11)
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/* SAMP: Last sample point */
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#define CAN_MSR_SAMP (1 << 10)
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/* RXM: Receive mode */
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#define CAN_MSR_RXM (1 << 9)
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/* TXM: Transmit mode */
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#define CAN_MSR_TXM (1 << 8)
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/* 7:5 Reserved, forced by hardware to 0 */
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/* SLAKI: Sleep acknowledge interrupt */
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#define CAN_MSR_SLAKI (1 << 4)
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/* WKUI: Wakeup interrupt */
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#define CAN_MSR_WKUI (1 << 3)
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/* ERRI: Error interrupt */
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#define CAN_MSR_ERRI (1 << 2)
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/* SLAK: Sleep acknowledge */
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#define CAN_MSR_SLAK (1 << 1)
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/* INAK: Initialization acknowledge */
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#define CAN_MSR_INAK (1 << 0)
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/* --- CAN_TSR values ------------------------------------------------------ */
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/* LOW2: Lowest priority flag for mailbox 2 */
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#define CAN_MSR_LOW2 (1 << 31)
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/* LOW1: Lowest priority flag for mailbox 1 */
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#define CAN_MSR_LOW1 (1 << 30)
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/* LOW0: Lowest priority flag for mailbox 0 */
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#define CAN_MSR_LOW0 (1 << 29)
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/* TME2: Transmit mailbox 2 empty */
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#define CAN_MSR_TME2 (1 << 28)
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/* TME1: Transmit mailbox 1 empty */
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#define CAN_MSR_TME1 (1 << 27)
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/* TME0: Transmit mailbox 0 empty */
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#define CAN_MSR_TME0 (1 << 26)
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/* CODE[1:0]: Mailbox code */
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#define CAN_MSR_CODE_MASK (0x3 << 24)
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/* ABRQ2: Abort request for mailbox 2 */
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#define CAN_MSR_TABRQ2 (1 << 23)
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/* 22:20 Reserved, forced by hardware to 0 */
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/* TERR2: Transmission error for mailbox 2 */
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#define CAN_MSR_TERR2 (1 << 19)
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/* ALST2: Arbitration lost for mailbox 2 */
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#define CAN_MSR_ALST2 (1 << 18)
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/* TXOK2: Transmission OK for mailbox 2 */
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#define CAN_MSR_TXOK2 (1 << 17)
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/* RQCP2: Request completed mailbox 2 */
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#define CAN_MSR_RQCP2 (1 << 16)
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/* ABRQ1: Abort request for mailbox 1 */
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#define CAN_MSR_ABRQ1 (1 << 15)
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/* 14:12 Reserved, forced by hardware to 0 */
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/* TERR1: Transmission error for mailbox 1 */
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#define CAN_MSR_TERR1 (1 << 11)
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/* ALST1: Arbitration lost for mailbox 1 */
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#define CAN_MSR_ALST1 (1 << 10)
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/* TXOK1: Transmission OK for mailbox 1 */
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#define CAN_MSR_TXOK1 (1 << 9)
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/* RQCP1: Request completed mailbox 1 */
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#define CAN_MSR_RQCP1 (1 << 8)
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/* ABRQ0: Abort request for mailbox 0 */
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#define CAN_MSR_ABRQ0 (1 << 7)
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/* 6:4 Reserved, forced by hardware to 0 */
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/* TERR0: Transmission error for mailbox 0 */
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#define CAN_MSR_TERR0 (1 << 3)
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/* ALST0: Arbitration lost for mailbox 0 */
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#define CAN_MSR_ALST0 (1 << 2)
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/* TXOK0: Transmission OK for mailbox 0 */
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#define CAN_MSR_TXOK0 (1 << 1)
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/* RQCP0: Request completed mailbox 0 */
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#define CAN_MSR_RQCP0 (1 << 0)
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/* --- CAN_RF0R values ----------------------------------------------------- */
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/* 31:6 Reserved, forced by hardware to 0 */
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/* RFOM0: Release FIFO 0 output mailbox */
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#define CAN_RF0R_RFOM0 (1 << 5)
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/* FOVR0: FIFO 0 overrun */
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#define CAN_RF0R_FAVR0 (1 << 4)
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/* FULL0: FIFO 0 full */
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#define CAN_RF0R_FULL0 (1 << 3)
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/* 2 Reserved, forced by hardware to 0 */
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/* FMP0[1:0]: FIFO 0 message pending */
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#define CAN_RF0R_FMP0_MASK (0x3 << 0)
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/* --- CAN_RF1R values ----------------------------------------------------- */
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/* 31:6 Reserved, forced by hardware to 0 */
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/* RFOM1: Release FIFO 1 output mailbox */
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#define CAN_RF1R_RFOM1 (1 << 5)
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/* FOVR1: FIFO 1 overrun */
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#define CAN_RF1R_FAVR1 (1 << 4)
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/* FULL1: FIFO 1 full */
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#define CAN_RF1R_FULL1 (1 << 3)
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/* 2 Reserved, forced by hardware to 0 */
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/* FMP1[1:0]: FIFO 1 message pending */
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#define CAN_RF1R_FMP1_MASK (0x3 << 0)
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/* --- CAN_IER values ------------------------------------------------------ */
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/* 32:18 Reserved, forced by hardware to 0 */
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/* SLKIE: Sleep interrupt enable */
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#define CAN_IER_SLKIE (1 << 17)
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/* WKUIE: Wakeup interrupt enable */
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#define CAN_IER_WKUIE (1 << 16)
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/* ERRIE: Error interrupt enable */
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#define CAN_IER_ERRIE (1 << 15)
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/* 14:12 Reserved, forced by hardware to 0 */
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/* LECIE: Last error code interrupt enable */
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#define CAN_IER_LECIE (1 << 11)
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/* BOFIE: Bus-off interrupt enable */
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#define CAN_IER_BOFIE (1 << 10)
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/* EPVIE: Error passive interrupt enable */
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#define CAN_IER_EPVIE (1 << 9)
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/* EWGIE: Error warning interrupt enable */
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#define CAN_IER_EWGIE (1 << 8)
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/* 7 Reserved, forced by hardware to 0 */
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/* FOVIE1: FIFO overrun interrupt enable */
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#define CAN_IER_FOVIE1 (1 << 6)
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/* FFIE1: FIFO full interrupt enable */
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#define CAN_IER_FFIE1 (1 << 5)
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/* FMPIE1: FIFO message pending interrupt enable */
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#define CAN_IER_FMPIE1 (1 << 4)
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/* FOVIE0: FIFO overrun interrupt enable */
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#define CAN_IER_FOVIE0 (1 << 3)
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/* FFIE0: FIFO full interrupt enable */
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#define CAN_IER_FFIE0 (1 << 2)
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/* FMPIE0: FIFO message pending interrupt enable */
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#define CAN_IER_FMPIE0 (1 << 1)
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/* TMEIE: Transmit mailbox empty interrupt enable */
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#define CAN_IER_TMEIE (1 << 0)
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/* --- CAN_ESR values ------------------------------------------------------ */
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/* REC[7:0]: Receive error counter */
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#define CAN_ESR_REC_MASK (0xF << 24)
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/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
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#define CAN_ESR_TEC_MASK (0xF << 16)
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/* 15:7 Reserved, forced by hardware to 0 */
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/* LEC[2:0]: Last error code */
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#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
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#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
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#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
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#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
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#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
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#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
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#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
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#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
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#define CAN_ESR_LEC_MASK (0x7 << 4)
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/* 3 Reserved, forced by hardware to 0 */
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/* BOFF: Bus-off flag */
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#define CAN_ESR_BOFF (1 << 2)
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/* EPVF: Error passive flag */
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#define CAN_ESR_EPVF (1 << 1)
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/* EWGF: Error warning flag */
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#define CAN_ESR_EWGF (1 << 0)
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/* --- CAN_BTR values ------------------------------------------------------ */
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/* SILM: Silent mode (debug) */
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#define CAN_BTR_SILM (1 << 31)
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/* LBKM: Loop back mode (debug) */
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#define CAN_BTR_LBKM (1 << 30)
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/* 29:26 Reserved, forced by hardware to 0 */
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/* SJW[1:0]: Resynchronization jump width */
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#define CAN_BTR_SJW_1TQ (0x0 << 24)
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#define CAN_BTR_SJW_2TQ (0x1 << 24)
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#define CAN_BTR_SJW_3TQ (0x2 << 24)
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#define CAN_BTR_SJW_4TQ (0x3 << 24)
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#define CAN_BTR_SJW_MASK (0x3 << 24)
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/* 23 Reserved, forced by hardware to 0 */
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/* TS2[2:0]: Time segment 2 */
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#define CAN_BTR_TS2_1TQ (0x0 << 20)
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#define CAN_BTR_TS2_2TQ (0x1 << 20)
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#define CAN_BTR_TS2_3TQ (0x2 << 20)
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#define CAN_BTR_TS2_4TQ (0x3 << 20)
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#define CAN_BTR_TS2_5TQ (0x4 << 20)
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#define CAN_BTR_TS2_6TQ (0x5 << 20)
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#define CAN_BTR_TS2_7TQ (0x6 << 20)
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#define CAN_BTR_TS2_8TQ (0x7 << 20)
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#define CAN_BTR_TS2_MASK (0x7 << 20)
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/* TS1[3:0]: Time segment 1 */
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#define CAN_BTR_TS1_1TQ (0x0 << 16)
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#define CAN_BTR_TS1_2TQ (0x1 << 16)
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#define CAN_BTR_TS1_3TQ (0x2 << 16)
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#define CAN_BTR_TS1_4TQ (0x3 << 16)
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#define CAN_BTR_TS1_5TQ (0x4 << 16)
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#define CAN_BTR_TS1_6TQ (0x5 << 16)
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#define CAN_BTR_TS1_7TQ (0x6 << 16)
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#define CAN_BTR_TS1_8TQ (0x7 << 16)
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#define CAN_BTR_TS1_9TQ (0x8 << 16)
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#define CAN_BTR_TS1_10TQ (0x9 << 16)
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#define CAN_BTR_TS1_11TQ (0xA << 16)
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#define CAN_BTR_TS1_12TQ (0xB << 16)
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#define CAN_BTR_TS1_13TQ (0xC << 16)
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#define CAN_BTR_TS1_14TQ (0xD << 16)
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#define CAN_BTR_TS1_15TQ (0xE << 16)
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#define CAN_BTR_TS1_16TQ (0xF << 16)
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#define CAN_BTR_TS1_MASK (0xF << 16)
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/* 15:10 Reserved, forced by hardware to 0 */
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/* BRP[9:0]: Baud rate prescaler */
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#define CAN_BTR_BRP_MASK (0x1FF << 0)
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/* --- CAN_TIxR values ------------------------------------------------------ */
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/* STID[10:0]: Standard identifier */
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#define CAN_TIxR_STID_MASK (0x3FF << 21)
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#define CAN_TIxR_STID_SHIFT 21
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/* EXID[15:0]: Extended identifier */
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#define CAN_TIxR_STID_MASK (0x1FFFFFF << 3)
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#define CAN_TIxR_STID_SHIFT 3
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/* IDE: Identifier extension */
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#define CAN_TIxR_IDE (1 << 2)
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/* RTR: Remote transmission request */
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#define CAN_TIxR_RTR (1 << 1)
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/* TXRQ: Transmit mailbox request */
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#define CAN_TIxR_TXRQ (1 << 0)
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/* --- CAN_TDTxR values ----------------------------------------------------- */
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/* TIME[15:0]: Message time stamp */
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#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
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#define CAN_TDTxR_TIME_SHIFT 15
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/* 15:6 Reserved, forced by hardware to 0 */
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/* TGT: Transmit global time */
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#define CAN_TDTxR_TGT (1 << 5)
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/* 7:4 Reserved, forced by hardware to 0 */
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/* DLC[3:0]: Data length code */
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#define CAN_TDTxR_DLC_MASK (0xF << 0)
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#define CAN_TDTxR_DLC_SHIFT 0
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/* --- CAN_TDLxR values ----------------------------------------------------- */
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/* DATA3[7:0]: Data byte 3 */
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/* DATA2[7:0]: Data byte 2 */
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/* DATA1[7:0]: Data byte 1 */
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/* DATA0[7:0]: Data byte 0 */
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/* --- CAN_TDHxR values ----------------------------------------------------- */
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/* DATA7[7:0]: Data byte 7 */
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/* DATA6[7:0]: Data byte 6 */
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/* DATA5[7:0]: Data byte 5 */
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/* DATA4[7:0]: Data byte 4 */
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/* --- CAN_RIxR values ------------------------------------------------------ */
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/* STID[10:0]: Standard identifier */
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#define CAN_RIxR_STID_MASK (0x3FF << 21)
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#define CAN_RIxR_STID_SHIFT 21
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/* EXID[15:0]: Extended identifier */
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#define CAN_RIxR_STID_MASK (0x1FFFFFF << 3)
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#define CAN_RIxR_STID_SHIFT 3
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/* IDE: Identifier extension */
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#define CAN_RIxR_IDE (1 << 2)
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/* RTR: Remote transmission request */
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#define CAN_RIxR_RTR (1 << 1)
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/* 0 Reserved */
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/* --- CAN_RDTxR values ----------------------------------------------------- */
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/* TIME[15:0]: Message time stamp */
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#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
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#define CAN_RDTxR_TIME_SHIFT 15
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/* 15:6 Reserved, forced by hardware to 0 */
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/* TGT: Transmit global time */
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#define CAN_RDTxR_TGT (1 << 5)
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/* 7:4 Reserved, forced by hardware to 0 */
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/* DLC[3:0]: Data length code */
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#define CAN_RDTxR_DLC_MASK (0xF << 0)
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#define CAN_RDTxR_DLC_SHIFT 0
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/* --- CAN_RDLxR values ----------------------------------------------------- */
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/* DATA3[7:0]: Data byte 3 */
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/* DATA2[7:0]: Data byte 2 */
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/* DATA1[7:0]: Data byte 1 */
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/* DATA0[7:0]: Data byte 0 */
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/* --- CAN_RDHxR values ----------------------------------------------------- */
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/* DATA7[7:0]: Data byte 7 */
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/* DATA6[7:0]: Data byte 6 */
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/* DATA5[7:0]: Data byte 5 */
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/* DATA4[7:0]: Data byte 4 */
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/* --- CAN_FMR values ------------------------------------------------------- */
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/* 31:14 Reserved, forced to reset value */
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/* CAN2SB[5:0]: CAN2 start bank
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* (only on connectivity line devices otherwise reserved) */
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#define CAN_FMR_CAN2SB_MASK (0x3F << 8)
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#define CAN_FMR_CAN2SB_SHIFT 15
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/* 7:1 Reserved, forced to reset value */
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/* FINIT: Filter init mode */
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#define CAN_FMR_FINIT (1 << 0)
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/* --- CAN_FM1R values ------------------------------------------------------ */
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/* 31:28 Reserved, forced by hardware to 0 */
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/* FBMx: Filter mode
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* x is 0..27 should be calculated by a helper function making so many macros
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* seems like an overkill?
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*/
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/* --- CAN_FS1R values ------------------------------------------------------ */
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/* 31:28 Reserved, forced by hardware to 0 */
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/* FSCx: Filter scale configuration
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* x is 0..27 should be calculated by a helper function making so many macros
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* seems like an overkill?
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*/
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/* --- CAN_FFA1R values ----------------------------------------------------- */
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/* 31:28 Reserved, forced by hardware to 0 */
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/* FFAx: Filter scale configuration
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* x is 0..27 should be calculated by a helper function making so many macros
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* seems like an overkill?
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*/
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/* --- CAN_FA1R values ------------------------------------------------------ */
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/* 31:28 Reserved, forced by hardware to 0 */
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/* FACTx: Filter active
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* x is 0..27 should be calculated by a helper function making so many macros
|
||||
* seems like an overkill?
|
||||
*/
|
||||
|
||||
/* --- CAN_FiRx values ------------------------------------------------------ */
|
||||
|
||||
/* FB[31:0]: Filter bits */
|
||||
|
||||
#endif /* LIBOPENSTM32_CAN_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue