Add RCC_AHBRSTR and RCC_CFGR2 bit definitions.
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@ -298,11 +298,66 @@
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/* --- RCC_AHBRSTR values -------------------------------------------------- */
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/* TODO */
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#define ETHMACRST (1 << 14)
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#define OTGFSRST (1 << 12)
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/* --- RCC_CFGR2 values ---------------------------------------------------- */
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/* TODO */
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/* I2S3SRC: I2S3 clock source */
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#define I2S3SRC_SYSCLK 0x0
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#define I2S3SRC_PLL3_VCO_CLK 0x1
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/* I2S2SRC: I2S2 clock source */
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#define I2S2SRC_SYSCLK 0x0
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#define I2S2SRC_PLL3_VCO_CLK 0x1
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/* PREDIV1SRC: PREDIV1 entry clock source */
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#define PREDIV1SRC_HSE_CLK 0x0
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#define PREDIV1SRC_PLL2_CLK 0x1
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#define PLL2MUL (1 << 0)
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#define PREDIV2 (1 << 0)
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#define PREDIV1 (1 << 0)
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/* PLL3MUL: PLL3 multiplication factor */
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#define PLL3MUL_PLL3_CLK_MUL8 0x6
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#define PLL3MUL_PLL3_CLK_MUL9 0x7
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#define PLL3MUL_PLL3_CLK_MUL10 0x8
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#define PLL3MUL_PLL3_CLK_MUL11 0x9
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#define PLL3MUL_PLL3_CLK_MUL12 0xa
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#define PLL3MUL_PLL3_CLK_MUL13 0xb
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#define PLL3MUL_PLL3_CLK_MUL14 0xc
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#define PLL3MUL_PLL3_CLK_MUL16 0xe
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#define PLL3MUL_PLL3_CLK_MUL20 0xf
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/* PLL2MUL: PLL2 multiplication factor */
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#define PLL2MUL_PLL2_CLK_MUL8 0x6
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#define PLL2MUL_PLL2_CLK_MUL9 0x7
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#define PLL2MUL_PLL2_CLK_MUL10 0x8
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#define PLL2MUL_PLL2_CLK_MUL11 0x9
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#define PLL2MUL_PLL2_CLK_MUL12 0xa
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#define PLL2MUL_PLL2_CLK_MUL13 0xb
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#define PLL2MUL_PLL2_CLK_MUL14 0xc
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#define PLL2MUL_PLL2_CLK_MUL16 0xe
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#define PLL2MUL_PLL2_CLK_MUL20 0xf
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/* PREDIV2: PREDIV2 division factor */
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#define PREDIV2_NODIV 0x0
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#define PREDIV2_DIV2 0x1
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#define PREDIV2_DIV3 0x2
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#define PREDIV2_DIV4 0x3
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#define PREDIV2_DIV5 0x4
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#define PREDIV2_DIV6 0x5
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#define PREDIV2_DIV7 0x6
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#define PREDIV2_DIV8 0x7
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#define PREDIV2_DIV9 0x8
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#define PREDIV2_DIV10 0x9
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#define PREDIV2_DIV11 0xa
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#define PREDIV2_DIV12 0xb
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#define PREDIV2_DIV13 0xc
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#define PREDIV2_DIV14 0xd
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#define PREDIV2_DIV15 0xe
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#define PREDIV2_DIV16 0xf
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typedef enum {
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PLL, HSE, HSI, LSE, LSI
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