ethernet: stm32: PTP naming fixes.
Verify all hardware differences between F1 and F4/F7 Ethernet hardware. Flags registers missing on F1 as well. Reviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
BOJIT
Karl Palsson
parent
5968b8a856
commit
5d393b17a3
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@ -58,8 +58,7 @@
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#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C)
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#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28)
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#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C)
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/* not available on F1 ?*/
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#define ETH_MACDBGR MMIO32(ETHERNET_BASE + 0x34)
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#define ETH_MACDBGR MMIO32(ETHERNET_BASE + 0x34) /* Not on STM32F1 */
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#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38)
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#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C)
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@ -81,7 +80,7 @@
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#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198)
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#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4)
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/* Ethrenet IEEE 1588 time stamp registers */
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/* Ethernet IEEE 1588 time stamp registers */
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#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700)
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#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704)
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#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708)
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@ -91,8 +90,8 @@
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#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718)
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#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C)
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#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720)
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/* not available on F1 ?*/
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#define ETH_PTPTSSR MMIO32(ETHERNET_BASE + 0x728)
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#define ETH_PTPTSSR MMIO32(ETHERNET_BASE + 0x728) /* Not on STM32F1 */
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#define ETH_PTPPPSCR MMIO32(ETHERNET_BASE + 0x72C) /* Not on STM32F1 */
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/* Ethernet DMA registers */
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#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000)
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@ -104,6 +103,7 @@
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#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018)
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#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C)
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#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020)
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#define ETH_DMARSWTR MMIO32(ETHERNET_BASE + 0x1024) /* Not on STM32F1 */
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#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048)
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#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C)
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#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050)
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@ -154,7 +154,7 @@
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#define ETH_MACCR_JD (1<<22)
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#define ETH_MACCR_WD (1<<23)
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#define ETH_MACCR_CSTF (1<<25)
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#define ETH_MACCR_CSTF (1<<25) /* Not on STM32F1 */
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/*---------------------------------------------------------------------------*/
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/* MACFFR -------------------------------------------------------------------*/
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@ -247,6 +247,7 @@
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/*---------------------------------------------------------------------------*/
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/* MACDBGR -------------------------------------------------------------------*/
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/* Not on STM32F1 */
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#define ETH_MACDBGR_MMRPEA (1<<0)
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#define ETH_MACDBGR_MSFRWCS (3<<1)
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#define ETH_MACDBGR_RFWRA (1<<4)
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@ -331,8 +332,9 @@
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#define ETH_MMCCR_CSR (1<<1)
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#define ETH_MMCCR_ROR (1<<2)
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#define ETH_MMCCR_MCF (1<<3)
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#define ETH_MMCCR_MCP (1<<4)
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#define ETH_MMCCR_MCFHP (1<<5)
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#define ETH_MMCCR_MCP (1<<4) /* Not on STM32F1 */
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#define ETH_MMCCR_MCFHP (1<<5) /* Not on STM32F1 */
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/*---------------------------------------------------------------------------*/
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/* MMCRIR -------------------------------------------------------------------*/
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@ -371,6 +373,8 @@
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#define ETH_PTPTSCR_TSSTU (1<<3)
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#define ETH_PTPTSCR_TSITE (1<<4)
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#define ETH_PTPTSCR_TTSARU (1<<5)
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/* Not on STM32F1 */
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#define ETH_PTPTSCR_TSSARFE (1<<8)
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#define ETH_PTPTSCR_TSSSR (1<<9)
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#define ETH_PTPTSCR_TSPTPPSV2E (1<<10)
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@ -410,29 +414,33 @@
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/*---------------------------------------------------------------------------*/
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/* PTPTSSR ------------------------------------------------------------------*/
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/* Not on STM32F1 */
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#define ETH_PTPTSSR_TSSO (1<<0)
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#define ETH_PTPTSSR_TSTTR (1<<1)
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/*---------------------------------------------------------------------------*/
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/* PTPTSCR ------------------------------------------------------------------*/
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#define ETH_PTPTSCR_PPSFREQ (0x0F<<0)
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#define ETH_PTPTSCR_PPSFREQ_1HZ (0x00<<0)
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#define ETH_PTPTSCR_PPSFREQ_2HZ (0x01<<0)
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#define ETH_PTPTSCR_PPSFREQ_4HZ (0x02<<0)
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#define ETH_PTPTSCR_PPSFREQ_8HZ (0x03<<0)
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#define ETH_PTPTSCR_PPSFREQ_16HZ (0x04<<0)
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#define ETH_PTPTSCR_PPSFREQ_32HZ (0x05<<0)
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#define ETH_PTPTSCR_PPSFREQ_64HZ (0x06<<0)
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#define ETH_PTPTSCR_PPSFREQ_128HZ (0x07<<0)
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#define ETH_PTPTSCR_PPSFREQ_256HZ (0x08<<0)
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#define ETH_PTPTSCR_PPSFREQ_512HZ (0x09<<0)
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#define ETH_PTPTSCR_PPSFREQ_1024HZ (0x0A<<0)
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#define ETH_PTPTSCR_PPSFREQ_2048HZ (0x0B<<0)
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#define ETH_PTPTSCR_PPSFREQ_4096HZ (0x0C<<0)
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#define ETH_PTPTSCR_PPSFREQ_8192HZ (0x0D<<0)
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#define ETH_PTPTSCR_PPSFREQ_16384HZ (0x0E<<0)
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#define ETH_PTPTSCR_PPSFREQ_32768HZ (0x0F<<0)
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/*---------------------------------------------------------------------------*/
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/* PTPPPSCR -----------------------------------------------------------------*/
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/* Not on STM32F1 */
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#define ETH_PTPPPSCR_PPSFREQ_MASK (0x0F<<0)
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#define ETH_PTPPPSCR_PPSFREQ_1HZ (0x00<<0)
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#define ETH_PTPPPSCR_PPSFREQ_2HZ (0x01<<0)
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#define ETH_PTPPPSCR_PPSFREQ_4HZ (0x02<<0)
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#define ETH_PTPPPSCR_PPSFREQ_8HZ (0x03<<0)
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#define ETH_PTPPPSCR_PPSFREQ_16HZ (0x04<<0)
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#define ETH_PTPPPSCR_PPSFREQ_32HZ (0x05<<0)
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#define ETH_PTPPPSCR_PPSFREQ_64HZ (0x06<<0)
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#define ETH_PTPPPSCR_PPSFREQ_128HZ (0x07<<0)
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#define ETH_PTPPPSCR_PPSFREQ_256HZ (0x08<<0)
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#define ETH_PTPPPSCR_PPSFREQ_512HZ (0x09<<0)
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#define ETH_PTPPPSCR_PPSFREQ_1024HZ (0x0A<<0)
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#define ETH_PTPPPSCR_PPSFREQ_2048HZ (0x0B<<0)
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#define ETH_PTPPPSCR_PPSFREQ_4096HZ (0x0C<<0)
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#define ETH_PTPPPSCR_PPSFREQ_8192HZ (0x0D<<0)
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#define ETH_PTPPPSCR_PPSFREQ_16384HZ (0x0E<<0)
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#define ETH_PTPPPSCR_PPSFREQ_32768HZ (0x0F<<0)
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/*---------------------------------------------------------------------------*/
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/* DMABMR -------------------------------------------------------------------*/
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@ -463,7 +471,7 @@
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#define ETH_DMABMR_USP (1<<23)
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#define ETH_DMABMR_FPM (1<<24)
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#define ETH_DMABMR_AAB (1<<25)
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#define ETH_DMABMR_MB (1<<26)
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#define ETH_DMABMR_MB (1<<26) /* Not on STM32F1 */
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/*---------------------------------------------------------------------------*/
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/* DMASR --------------------------------------------------------------------*/
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@ -574,6 +582,7 @@
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/*---------------------------------------------------------------------------*/
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/* DMARSWTR -----------------------------------------------------------------*/
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/* Not on STM32F1 */
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#define ETH_DMARSWTR_RSWTC 0xFF
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/*---------------------------------------------------------------------------*/
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