Fixed multi-line comments now it is "compliant" with Linux CodingStyle.
This commit is contained in:
TitanMKD
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686c0cf050
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58d5b96291
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@ -2,6 +2,7 @@
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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@ -299,11 +300,9 @@
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/* Analog function select register */
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#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90)
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/* EMC clock delay register */
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#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00)
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/* Pin interrupt select registers */
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/* Pin interrupt select register for pin interrupts 0 to 3 */
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@ -315,68 +314,76 @@
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/**************************/
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/* SCU I2C0 Configuration */
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/**************************/
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/* Select input glitch filter time constant for the SCL pin.
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0 = 50 ns glitch filter.
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1 = 3ns glitch filter.
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/*
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* Select input glitch filter time constant for the SCL pin.
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* 0 = 50 ns glitch filter.
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* 1 = 3ns glitch filter.
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*/
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#define SCU_SCL_EFP (BIT0)
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/* BIT1 Reserved. Always write a 0 to this bit. */
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/* Select I2C mode for the SCL pin.
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0 = Standard/Fast mode transmit.
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1 = Fast-mode Plus transmit.
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*/
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/*
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* Select I2C mode for the SCL pin.
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* 0 = Standard/Fast mode transmit.
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* 1 = Fast-mode Plus transmit.
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*/
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#define SCU_SCL_EHD (BIT2)
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/* Enable the input receiver for the SCL pin.
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Always write a 1 to this bit when using the
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I2C0.
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0 = Disabled.
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1 = Enabled.
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*/
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/*
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* Enable the input receiver for the SCL pin.
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* Always write a 1 to this bit when using the
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* I2C0.
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* 0 = Disabled.
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* 1 = Enabled.
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*/
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#define SCU_SCL_EZI_EN (BIT3)
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/* BIT4-6 Reserved. */
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/* Enable or disable input glitch filter for the
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SCL pin. The filter time constant is
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determined by bit EFP.
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0 = Enable input filter.
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1 = Disable input filter.
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*/
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/*
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* Enable or disable input glitch filter for the
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* SCL pin. The filter time constant is
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* determined by bit EFP.
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* 0 = Enable input filter.
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* 1 = Disable input filter.
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*/
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#define SCU_SCL_ZIF_DIS (BIT7)
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/* Select input glitch filter time constant for the SDA pin.
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0 = 50 ns glitch filter.
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1 = 3ns glitch filter.
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/*
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* Select input glitch filter time constant for the SDA pin.
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* 0 = 50 ns glitch filter.
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* 1 = 3ns glitch filter.
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*/
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#define SCU_SDA_EFP (BIT8)
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/* BIT9 Reserved. Always write a 0 to this bit. */
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/* Select I2C mode for the SDA pin.
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0 = Standard/Fast mode transmit.
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1 = Fast-mode Plus transmit.
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*/
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/*
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* Select I2C mode for the SDA pin.
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* 0 = Standard/Fast mode transmit.
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* 1 = Fast-mode Plus transmit.
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*/
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#define SCU_SDA_EHD (BIT10)
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/* Enable the input receiver for the SDA pin.
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Always write a 1 to this bit when using the
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I2C0.
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0 = Disabled.
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1 = Enabled.
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*/
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/*
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* Enable the input receiver for the SDA pin.
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* Always write a 1 to this bit when using the
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* I2C0.
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* 0 = Disabled.
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* 1 = Enabled.
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*/
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#define SCU_SDA_EZI_EN (BIT11)
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/* BIT 12-14 - Reserved */
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/* Enable or disable input glitch filter for the
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SDA pin. The filter time constant is
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determined by bit SDA_EFP.
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0 = Enable input filter.
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1 = Disable input filter.
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*/
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/*
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* Enable or disable input glitch filter for the
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* SDA pin. The filter time constant is
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* determined by bit SDA_EFP.
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* 0 = Enable input filter.
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* 1 = Disable input filter.
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*/
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#define SCU_SDA_ZIF_DIS (BIT15)
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/* Standard mode for I2C SCL/SDA Standard/Fast mode */
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@ -387,35 +394,35 @@ determined by bit SDA_EFP.
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SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)
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/*
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SCU PIN Normal Drive:
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The pin configuration registers for normal-drive pins control the following pins:
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- P0_0 and P0_1
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- P1_0 to P1_16 and P1_18 to P1_20
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- P2_0 to P2_2 and P2_6 to P2_13
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- P3_0 to P3_2 and P3_4 to P3_8
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- P4_0 to P4_10
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- P5_0 to P5_7
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- P6_0 to P6_12
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- P7_0 to P7_7
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- P8_3 to P8_8
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- P9_0 to P9_6
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- PA_0 and PA_4
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- PB_0 to PB_6
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- PC_0 to PC_14
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- PE_0 to PE_15
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- PF_0 to PF_11
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Pin configuration registers for High-Drive pins.
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The pin configuration registers for high-drive pins control the following pins:
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• P1_17
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• P2_3 to P2_5
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• P8_0 to P8_2
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• PA_1 to PA_3
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Pin configuration registers for High-Speed pins.
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This register controls the following pins:
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P3_3 and pins CLK0 to CLK3.
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*/
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* SCU PIN Normal Drive:
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* The pin configuration registers for normal-drive pins control the following pins:
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* - P0_0 and P0_1
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* - P1_0 to P1_16 and P1_18 to P1_20
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* - P2_0 to P2_2 and P2_6 to P2_13
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* - P3_0 to P3_2 and P3_4 to P3_8
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* - P4_0 to P4_10
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* - P5_0 to P5_7
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* - P6_0 to P6_12
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* - P7_0 to P7_7
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* - P8_3 to P8_8
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* - P9_0 to P9_6
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* - PA_0 and PA_4
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* - PB_0 to PB_6
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* - PC_0 to PC_14
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* - PE_0 to PE_15
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* - PF_0 to PF_11
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*
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* Pin configuration registers for High-Drive pins.
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* The pin configuration registers for high-drive pins control the following pins:
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* - P1_17
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* - P2_3 to P2_5
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* - P8_0 to P8_2
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* - PA_1 to PA_3
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*
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* Pin configuration registers for High-Speed pins.
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* This register controls the following pins:
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* - P3_3 and pins CLK0 to CLK3.
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*/
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typedef enum {
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/* Group Port 0 */
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P0_0 = (PIN_GROUP0+PIN0),
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@ -643,12 +650,14 @@ typedef enum {
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} scu_grp_pin_t;
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/******************************************************************/
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/* Pin Configuration to be used for scu_pinmux() parameter scu_conf
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For normal-drive pins, high-drive pins, high-speed pins */
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/******************************************************************/
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/* Function BIT0 to 2.
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Common to normal-drive pins, high-drive pins, high-speed pins. */
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/*
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* Pin Configuration to be used for scu_pinmux() parameter scu_conf
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* For normal-drive pins, high-drive pins, high-speed pins
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*/
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/*
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* Function BIT0 to 2.
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* Common to normal-drive pins, high-drive pins, high-speed pins.
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*/
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#define SCU_CONF_FUNCTION0 (0x0)
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#define SCU_CONF_FUNCTION1 (0x1)
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#define SCU_CONF_FUNCTION2 (0x2)
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@ -658,34 +667,46 @@ Common to normal-drive pins, high-drive pins, high-speed pins. */
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#define SCU_CONF_FUNCTION6 (0x6)
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#define SCU_CONF_FUNCTION7 (0x7)
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/* Enable pull-down resistor at pad
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By default=0 Disable pull-down.
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Available to normal-drive pins, high-drive pins, high-speed pins */
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/*
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* Enable pull-down resistor at pad
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* By default=0 Disable pull-down.
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* Available to normal-drive pins, high-drive pins, high-speed pins
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*/
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#define SCU_CONF_EPD_EN_PULLDOWN (BIT3)
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/* Disable pull-up resistor at pad.
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By default=0 the pull-up resistor is enabled at reset.
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Available to normal-drive pins, high-drive pins, high-speed pins */
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/*
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* Disable pull-up resistor at pad.
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* By default=0 the pull-up resistor is enabled at reset.
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* Available to normal-drive pins, high-drive pins, high-speed pins
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*/
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#define SCU_CONF_EPUN_DIS_PULLUP (BIT4)
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/* Select Slew Rate.
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By Default=0 Slow.
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Available to normal-drive pins and high-speed pins, reserved for high-drive pins. */
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/*
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* Select Slew Rate.
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* By Default=0 Slow.
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* Available to normal-drive pins and high-speed pins, reserved for high-drive pins.
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*/
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#define SCU_CONF_EHS_FAST (BIT5)
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/* Input buffer enable.
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By Default=0 Disable Input Buffer.
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The input buffer is disabled by default at reset and must be enabled
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for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins).
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Available to normal-drive pins, high-drive pins, high-speed pins */
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/*
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* Input buffer enable.
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* By Default=0 Disable Input Buffer.
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* The input buffer is disabled by default at reset and must be enabled.
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* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins).
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* Available to normal-drive pins, high-drive pins, high-speed pins.
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*/
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#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6)
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/* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.
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Available to normal-drive pins, high-drive pins, high-speed pins */
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/*
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* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.
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* Available to normal-drive pins, high-drive pins, high-speed pins.
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*/
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#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)
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/* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9)
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Available to high-drive pins, reserved for others. */
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/*
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* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9).
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* Available to high-drive pins, reserved for others.
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*/
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#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100)
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#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200)
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#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300)
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