lpc43xx: Convert register definitions to YAML
This commit is contained in:
Ben Gamari
Piotr Esden-Tempski
parent
4fd218ad4c
commit
580be39e47
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@ -1,77 +0,0 @@
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ADC0_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw
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ADC0_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw
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ADC0_CR,16,1,BURST,Controls Burst mode,0,rw
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ADC0_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw
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ADC0_CR,21,1,PDN,Power mode,0,rw
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ADC0_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw
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ADC0_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw
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ADC1_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw
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ADC1_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw
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ADC1_CR,16,1,BURST,Controls Burst mode,0,rw
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ADC1_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw
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ADC1_CR,21,1,PDN,Power mode,0,rw
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ADC1_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw
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ADC1_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw
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ADC0_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r
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ADC0_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r
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ADC0_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r
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ADC0_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r
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ADC1_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r
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ADC1_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r
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ADC1_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r
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ADC1_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r
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ADC0_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw
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ADC0_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw
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ADC1_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw
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ADC1_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw
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ADC0_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r
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ADC0_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC0_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC1_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r
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ADC1_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
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ADC1_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
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ADC0_STAT,0,8,DONE,These bits mirror the DONE status flags that appear in the result register for each A/D channel.,0,r
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ADC0_STAT,8,8,OVERRUN,These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel.,0,r
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ADC0_STAT,16,1,ADINT,This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.,0,r
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@ -0,0 +1,607 @@
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!!omap
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- ADC0_CR:
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fields: !!omap
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- SEL:
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access: rw
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description: Selects which of the ADCn_[7:0] inputs are to be sampled and
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converted
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lsb: 0
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reset_value: '0'
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width: 8
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- CLKDIV:
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access: rw
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description: The ADC clock is divided by the CLKDIV value plus one to produce
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the clock for the A/D converter
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lsb: 8
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reset_value: '0'
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width: 8
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- BURST:
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access: rw
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description: Controls Burst mode
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lsb: 16
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reset_value: '0'
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width: 1
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- CLKS:
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access: rw
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description: This field selects the number of clocks used for each conversion
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in Burst mode and the number of bits of accuracy of the result in the LS
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bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
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lsb: 17
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reset_value: '0'
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width: 3
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- PDN:
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access: rw
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description: Power mode
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lsb: 21
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reset_value: '0'
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width: 1
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- START:
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access: rw
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description: Controls the start of an A/D conversion when the BURST bit is
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0
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lsb: 24
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reset_value: '0'
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width: 3
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- EDGE:
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access: rw
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description: Controls rising or falling edge on the selected signal for the
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start of a conversion
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lsb: 27
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reset_value: '0'
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width: 1
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- ADC1_CR:
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fields: !!omap
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- SEL:
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access: rw
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description: Selects which of the ADCn_[7:0] inputs are to be sampled and
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converted
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lsb: 0
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reset_value: '0'
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width: 8
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- CLKDIV:
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access: rw
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description: The ADC clock is divided by the CLKDIV value plus one to produce
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the clock for the A/D converter
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lsb: 8
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reset_value: '0'
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width: 8
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- BURST:
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access: rw
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description: Controls Burst mode
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lsb: 16
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reset_value: '0'
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width: 1
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- CLKS:
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access: rw
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description: This field selects the number of clocks used for each conversion
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in Burst mode and the number of bits of accuracy of the result in the LS
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bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
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lsb: 17
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reset_value: '0'
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width: 3
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- PDN:
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access: rw
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description: Power mode
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lsb: 21
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reset_value: '0'
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width: 1
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- START:
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access: rw
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description: Controls the start of an A/D conversion when the BURST bit is
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0
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lsb: 24
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reset_value: '0'
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width: 3
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- EDGE:
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access: rw
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description: Controls rising or falling edge on the selected signal for the
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start of a conversion
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lsb: 27
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reset_value: '0'
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width: 1
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- ADC0_GDR:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADCn pin selected by the SEL field, divided by the reference
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voltage on the VDDA pin
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lsb: 6
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reset_value: '0'
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width: 10
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- CHN:
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access: r
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description: These bits contain the channel from which the LS bits were converted
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lsb: 24
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reset_value: '0'
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width: 3
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an analog-to-digital conversion completes.
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It is cleared when this register is read and when the AD0/1CR register is
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written
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC1_GDR:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADCn pin selected by the SEL field, divided by the reference
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voltage on the VDDA pin
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lsb: 6
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reset_value: '0'
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width: 10
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- CHN:
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access: r
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description: These bits contain the channel from which the LS bits were converted
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lsb: 24
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reset_value: '0'
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width: 3
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an analog-to-digital conversion completes.
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It is cleared when this register is read and when the AD0/1CR register is
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written
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC0_INTEN:
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fields: !!omap
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- ADINTEN:
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access: rw
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description: These bits allow control over which A/D channels generate interrupts
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for conversion completion
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lsb: 0
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reset_value: '0'
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width: 8
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- ADGINTEN:
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access: rw
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description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
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When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
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interrupts.
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lsb: 8
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reset_value: '1'
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width: 1
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- ADC1_INTEN:
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fields: !!omap
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- ADINTEN:
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access: rw
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description: These bits allow control over which A/D channels generate interrupts
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for conversion completion
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lsb: 0
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reset_value: '0'
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width: 8
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- ADGINTEN:
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access: rw
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description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
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When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
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interrupts.
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lsb: 8
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reset_value: '1'
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width: 1
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- ADC0_DR0:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC0 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC1_DR0:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC0 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC0_DR1:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC1 pin divided by the reference voltage on the VDDA
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pin
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||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC1_DR1:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC1 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC0_DR2:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC2 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC1_DR2:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC2 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC0_DR3:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC3 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC1_DR3:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC3 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC0_DR4:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC4 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC1_DR4:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC4 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC0_DR5:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC5 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC1_DR5:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC5 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC0_DR6:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC6 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC1_DR6:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC6 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC0_DR7:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC7 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC1_DR7:
|
||||
fields: !!omap
|
||||
- V_VREF:
|
||||
access: r
|
||||
description: When DONE is 1, this field contains a binary fraction representing
|
||||
the voltage on the ADC7 pin divided by the reference voltage on the VDDA
|
||||
pin
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 10
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: This bit is 1 in burst mode if the results of one or more conversions
|
||||
was (were) lost and overwritten before the conversion that produced the
|
||||
result in the V_VREF bits in this register.
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DONE:
|
||||
access: r
|
||||
description: This bit is set to 1 when an A/D conversion completes.
|
||||
lsb: 31
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADC0_STAT:
|
||||
fields: !!omap
|
||||
- DONE:
|
||||
access: r
|
||||
description: These bits mirror the DONE status flags that appear in the result
|
||||
register for each A/D channel.
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- OVERRUN:
|
||||
access: r
|
||||
description: These bits mirror the OVERRRUN status flags that appear in the
|
||||
result register for each A/D channel.
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- ADINT:
|
||||
access: r
|
||||
description: This bit is the A/D interrupt flag. It is one when any of the
|
||||
individual A/D channel Done flags is asserted and enabled to contribute
|
||||
to the A/D interrupt via the ADINTEN register.
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
ATIMER_DOWNCOUNTER,0,16,CVAL,When equal to zero an interrupt is raised,0,rw
|
||||
ATIMER_PRESET,0,16,PRESETVAL,Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero,0,rw
|
||||
ATIMER_CLR_EN,0,1,CLR_EN,Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register,0,w
|
||||
ATIMER_SET_EN,0,1,SET_EN,Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register,0,w
|
||||
ATIMER_STATUS,0,1,STAT,A 1 in this bit shows that the STATUS interrupt has been raised,0,r
|
||||
ATIMER_ENABLE,0,1,ENA,A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register,0,r
|
||||
ATIMER_CLR_STAT,0,1,CSTAT,Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register,0,w
|
||||
ATIMER_SET_STAT,0,1,SSTAT,Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register,0,w
|
||||
|
|
|
@ -0,0 +1,71 @@
|
|||
!!omap
|
||||
- ATIMER_DOWNCOUNTER:
|
||||
fields: !!omap
|
||||
- CVAL:
|
||||
access: rw
|
||||
description: When equal to zero an interrupt is raised
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 16
|
||||
- ATIMER_PRESET:
|
||||
fields: !!omap
|
||||
- PRESETVAL:
|
||||
access: rw
|
||||
description: Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 16
|
||||
- ATIMER_CLR_EN:
|
||||
fields: !!omap
|
||||
- CLR_EN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the interrupt enable bit in the
|
||||
ENABLE register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_SET_EN:
|
||||
fields: !!omap
|
||||
- SET_EN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the interrupt enable bit in the
|
||||
ENABLE register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_STATUS:
|
||||
fields: !!omap
|
||||
- STAT:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the STATUS interrupt has been raised
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_ENABLE:
|
||||
fields: !!omap
|
||||
- ENA:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the STATUS interrupt has been enabled
|
||||
and that the STATUS interrupt request signal is asserted when STAT = 1 in
|
||||
the STATUS register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_CLR_STAT:
|
||||
fields: !!omap
|
||||
- CSTAT:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS interrupt bit in the
|
||||
STATUS register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_SET_STAT:
|
||||
fields: !!omap
|
||||
- SSTAT:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS interrupt bit in the
|
||||
STATUS register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
|
|
@ -1,359 +0,0 @@
|
|||
CCU1_PM,0,1,PD,Initiate power-down mode,0,rw
|
||||
CCU1_BASE_STAT,0,1,BASE_APB3_CLK_IND,Base clock indicator for BASE_APB3_CLK,1,r
|
||||
CCU1_BASE_STAT,1,1,BASE_APB1_CLK_IND,Base clock indicator for BASE_APB1_CLK,1,r
|
||||
CCU1_BASE_STAT,2,1,BASE_SPIFI_CLK_IND,Base clock indicator for BASE_SPIFI_CLK,1,r
|
||||
CCU1_BASE_STAT,3,1,BASE_M4_CLK_IND,Base clock indicator for BASE_M4_CLK,1,r
|
||||
CCU1_BASE_STAT,6,1,BASE_PERIPH_CLK_IND,Base clock indicator for BASE_PERIPH_CLK,1,r
|
||||
CCU1_BASE_STAT,7,1,BASE_USB0_CLK_IND,Base clock indicator for BASE_USB0_CLK,1,r
|
||||
CCU1_BASE_STAT,8,1,BASE_USB1_CLK_IND,Base clock indicator for BASE_USB1_CLK,1,r
|
||||
CCU1_BASE_STAT,9,1,BASE_SPI_CLK_IND,Base clock indicator for BASE_SPI_CLK,1,r
|
||||
CCU1_CLK_APB3_BUS_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB3_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB3_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB3_BUS_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB3_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB3_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB3_I2C1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB3_I2C1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB3_I2C1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB3_I2C1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB3_I2C1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB3_I2C1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB3_DAC_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB3_DAC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB3_DAC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB3_DAC_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB3_DAC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB3_DAC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB3_ADC0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB3_ADC0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB3_ADC0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB3_ADC0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB3_ADC0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB3_ADC0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB3_ADC1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB3_ADC1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB3_ADC1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB3_ADC1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB3_ADC1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB3_ADC1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB3_CAN0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB3_CAN0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB3_CAN0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB3_CAN0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB3_CAN0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB3_CAN0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB1_BUS_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB1_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB1_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB1_BUS_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB1_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB1_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB1_MOTOCONPWM_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB1_MOTOCONPWM_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB1_MOTOCONPWM_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB1_MOTOCONPWM_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB1_MOTOCONPWM_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB1_MOTOCONPWM_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB1_I2C0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB1_I2C0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB1_I2C0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB1_I2C0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB1_I2C0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB1_I2C0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB1_I2S_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB1_I2S_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB1_I2S_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB1_I2S_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB1_I2S_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB1_I2S_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_APB1_CAN1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_APB1_CAN1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_APB1_CAN1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_APB1_CAN1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_APB1_CAN1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_APB1_CAN1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_SPIFI_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_SPIFI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_SPIFI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_SPIFI_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_SPIFI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_SPIFI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_BUS_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_BUS_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_SPIFI_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_SPIFI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_SPIFI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_SPIFI_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_SPIFI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_SPIFI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_GPIO_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_GPIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_GPIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_GPIO_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_GPIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_GPIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_LCD_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_LCD_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_LCD_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_LCD_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_LCD_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_LCD_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_ETHERNET_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_ETHERNET_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_ETHERNET_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_ETHERNET_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_ETHERNET_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_ETHERNET_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_USB0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_USB0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_USB0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_USB0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_USB0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_USB0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_EMC_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_EMC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_EMC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_EMC_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_EMC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_EMC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_SDIO_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_SDIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_SDIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_SDIO_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_SDIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_SDIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_DMA_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_DMA_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_DMA_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_DMA_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_DMA_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_DMA_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_M4CORE_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_M4CORE_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_M4CORE_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_M4CORE_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_M4CORE_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_M4CORE_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_SCT_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_SCT_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_SCT_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_SCT_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_SCT_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_SCT_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_USB1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_USB1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_USB1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_USB1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_USB1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_USB1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_EMCDIV_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_EMCDIV_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_EMCDIV_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_EMCDIV_CFG,5,3,DIV,Clock divider value,0,rw
|
||||
CCU1_CLK_M4_EMCDIV_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_EMCDIV_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_EMCDIV_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_M0APP_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_M0APP_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_M0APP_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_M0APP_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_M0APP_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_M0APP_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_VADC_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_VADC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_VADC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_VADC_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_VADC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_VADC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_WWDT_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_WWDT_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_WWDT_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_WWDT_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_WWDT_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_WWDT_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_USART0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_USART0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_USART0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_USART0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_USART0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_USART0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_UART1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_UART1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_UART1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_UART1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_UART1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_UART1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_SSP0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_SSP0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_SSP0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_SSP0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_SSP0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_SSP0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_TIMER0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_TIMER0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_TIMER0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_TIMER0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_TIMER0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_TIMER0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_TIMER1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_TIMER1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_TIMER1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_TIMER1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_TIMER1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_TIMER1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_SCU_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_SCU_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_SCU_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_SCU_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_SCU_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_SCU_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_CREG_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_CREG_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_CREG_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_CREG_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_CREG_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_CREG_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_RITIMER_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_RITIMER_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_RITIMER_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_RITIMER_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_RITIMER_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_RITIMER_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_USART2_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_USART2_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_USART2_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_USART2_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_USART2_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_USART2_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_USART3_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_USART3_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_USART3_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_USART3_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_USART3_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_USART3_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_TIMER2_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_TIMER2_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_TIMER2_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_TIMER2_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_TIMER2_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_TIMER2_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_TIMER3_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_TIMER3_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_TIMER3_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_TIMER3_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_TIMER3_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_TIMER3_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_SSP1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_SSP1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_SSP1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_SSP1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_SSP1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_SSP1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_M4_QEI_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_M4_QEI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_M4_QEI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_M4_QEI_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_M4_QEI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_M4_QEI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_PERIPH_BUS_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_PERIPH_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_PERIPH_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_PERIPH_BUS_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_PERIPH_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_PERIPH_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_PERIPH_CORE_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_PERIPH_CORE_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_PERIPH_CORE_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_PERIPH_CORE_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_PERIPH_CORE_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_PERIPH_CORE_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_PERIPH_SGPIO_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_PERIPH_SGPIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_PERIPH_SGPIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_PERIPH_SGPIO_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_PERIPH_SGPIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_PERIPH_SGPIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_USB0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_USB0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_USB0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_USB0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_USB0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_USB0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_USB1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_USB1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_USB1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_USB1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_USB1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_USB1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_SPI_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_SPI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_SPI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_SPI_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_SPI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_SPI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU1_CLK_VADC_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU1_CLK_VADC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU1_CLK_VADC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU1_CLK_VADC_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU1_CLK_VADC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU1_CLK_VADC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_PM,0,1,PD,Initiate power-down mode,0,rw
|
||||
CCU2_BASE_STAT,1,1,BASE_UART3_CLK_IND,Base clock indicator for BASE_UART3_CLK,1,r
|
||||
CCU2_BASE_STAT,2,1,BASE_UART2_CLK_IND,Base clock indicator for BASE_UART2_CLK,1,r
|
||||
CCU2_BASE_STAT,3,1,BASE_UART1_CLK_IND,Base clock indicator for BASE_UART1_CLK,1,r
|
||||
CCU2_BASE_STAT,4,1,BASE_UART0_CLK_IND,Base clock indicator for BASE_UART0_CLK,1,r
|
||||
CCU2_BASE_STAT,5,1,BASE_SSP1_CLK_IND,Base clock indicator for BASE_SSP1_CLK,1,r
|
||||
CCU2_BASE_STAT,6,1,BASE_SSP0_CLK_IND,Base clock indicator for BASE_SSP0_CLK,1,r
|
||||
CCU2_CLK_APLL_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_APLL_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_APLL_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_APLL_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_APLL_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_APLL_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_CLK_APB2_USART3_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_APB2_USART3_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_APB2_USART3_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_APB2_USART3_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_APB2_USART3_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_APB2_USART3_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_CLK_APB2_USART2_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_APB2_USART2_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_APB2_USART2_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_APB2_USART2_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_APB2_USART2_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_APB2_USART2_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_CLK_APB0_UART1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_APB0_UART1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_APB0_UART1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_APB0_UART1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_APB0_UART1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_APB0_UART1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_CLK_APB0_USART0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_APB0_USART0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_APB0_USART0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_APB0_USART0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_APB0_USART0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_APB0_USART0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_CLK_APB2_SSP1_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_APB2_SSP1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_APB2_SSP1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_APB2_SSP1_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_APB2_SSP1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_APB2_SSP1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_CLK_APB0_SSP0_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_APB0_SSP0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_APB0_SSP0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_APB0_SSP0_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_APB0_SSP0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_APB0_SSP0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
CCU2_CLK_SDIO_CFG,0,1,RUN,Run enable,1,rw
|
||||
CCU2_CLK_SDIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw
|
||||
CCU2_CLK_SDIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw
|
||||
CCU2_CLK_SDIO_STAT,0,1,RUN,Run enable status,1,r
|
||||
CCU2_CLK_SDIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r
|
||||
CCU2_CLK_SDIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r
|
||||
|
File diff suppressed because it is too large
Load Diff
|
|
@ -1,142 +0,0 @@
|
|||
CGU_FREQ_MON,0,9,RCNT,9-bit reference clock-counter value,0,rw
|
||||
CGU_FREQ_MON,9,14,FCNT,14-bit selected clock-counter value,0,r
|
||||
CGU_FREQ_MON,23,1,MEAS,Measure frequency,0,rw
|
||||
CGU_FREQ_MON,24,5,CLK_SEL,Clock-source selection for the clock to be measured,0,rw
|
||||
CGU_XTAL_OSC_CTRL,0,1,ENABLE,Oscillator-pad enable,1,rw
|
||||
CGU_XTAL_OSC_CTRL,1,1,BYPASS,Configure crystal operation or external-clock input pin XTAL1,0,rw
|
||||
CGU_XTAL_OSC_CTRL,2,1,HF,Select frequency range,1,rw
|
||||
CGU_PLL0USB_STAT,0,1,LOCK,PLL0 lock indicator,0,r
|
||||
CGU_PLL0USB_STAT,1,1,FR,PLL0 free running indicator,0,r
|
||||
CGU_PLL0USB_CTRL,0,1,PD,PLL0 power down,1,rw
|
||||
CGU_PLL0USB_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
|
||||
CGU_PLL0USB_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw
|
||||
CGU_PLL0USB_CTRL,3,1,DIRECTO,PLL0 direct output,0,rw
|
||||
CGU_PLL0USB_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw
|
||||
CGU_PLL0USB_CTRL,6,1,FRM,Free running mode,0,rw
|
||||
CGU_PLL0USB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_PLL0USB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_PLL0USB_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw
|
||||
CGU_PLL0USB_MDIV,17,5,SELP,Bandwidth select P value,0x1C,rw
|
||||
CGU_PLL0USB_MDIV,22,6,SELI,Bandwidth select I value,0x17,rw
|
||||
CGU_PLL0USB_MDIV,28,4,SELR,Bandwidth select R value,0x0,rw
|
||||
CGU_PLL0USB_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw
|
||||
CGU_PLL0USB_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw
|
||||
CGU_PLL0AUDIO_STAT,0,1,LOCK,PLL0 lock indicator,0,r
|
||||
CGU_PLL0AUDIO_STAT,1,1,FR,PLL0 free running indicator,0,r
|
||||
CGU_PLL0AUDIO_CTRL,0,1,PD,PLL0 power down,1,rw
|
||||
CGU_PLL0AUDIO_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
|
||||
CGU_PLL0AUDIO_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw
|
||||
CGU_PLL0AUDIO_CTRL,3,1,DIRECTO,PLL0 direct output,0,rw
|
||||
CGU_PLL0AUDIO_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw
|
||||
CGU_PLL0AUDIO_CTRL,6,1,FRM,Free running mode,0,rw
|
||||
CGU_PLL0AUDIO_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_PLL0AUDIO_CTRL,12,1,PLLFRACT_REQ,Fractional PLL word write request,0,rw
|
||||
CGU_PLL0AUDIO_CTRL,13,1,SEL_EXT,Select fractional divider,0,rw
|
||||
CGU_PLL0AUDIO_CTRL,14,1,MOD_PD,Sigma-Delta modulator power-down,1,rw
|
||||
CGU_PLL0AUDIO_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_PLL0AUDIO_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw
|
||||
CGU_PLL0AUDIO_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw
|
||||
CGU_PLL0AUDIO_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw
|
||||
CGU_PLLAUDIO_FRAC,0,22,PLLFRACT_CTRL,PLL fractional divider control word,0x00,rw
|
||||
CGU_PLL1_STAT,0,1,LOCK,PLL1 lock indicator,0,r
|
||||
CGU_PLL1_CTRL,0,1,PD,PLL1 power down,1,rw
|
||||
CGU_PLL1_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
|
||||
CGU_PLL1_CTRL,6,1,FBSEL,PLL feedback select,0,rw
|
||||
CGU_PLL1_CTRL,7,1,DIRECT,PLL direct CCO output,0,rw
|
||||
CGU_PLL1_CTRL,8,2,PSEL,Post-divider division ratio P,0x1,rw
|
||||
CGU_PLL1_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_PLL1_CTRL,12,2,NSEL,Pre-divider division ratio N,0x2,rw
|
||||
CGU_PLL1_CTRL,16,8,MSEL,Feedback-divider division ratio (M),0x18,rw
|
||||
CGU_PLL1_CTRL,24,5,CLK_SEL,Clock-source selection,0x01,rw
|
||||
CGU_IDIVA_CTRL,0,1,PD,Integer divider power down,0,rw
|
||||
CGU_IDIVA_CTRL,2,2,IDIV,Integer divider A divider value (1/(IDIV + 1)),0x0,rw
|
||||
CGU_IDIVA_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_IDIVA_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_IDIVB_CTRL,0,1,PD,Integer divider power down,0,rw
|
||||
CGU_IDIVB_CTRL,2,4,IDIV,Integer divider B divider value (1/(IDIV + 1)),0x0,rw
|
||||
CGU_IDIVB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_IDIVB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_IDIVC_CTRL,0,1,PD,Integer divider power down,0,rw
|
||||
CGU_IDIVC_CTRL,2,4,IDIV,Integer divider C divider value (1/(IDIV + 1)),0x0,rw
|
||||
CGU_IDIVC_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_IDIVC_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_IDIVD_CTRL,0,1,PD,Integer divider power down,0,rw
|
||||
CGU_IDIVD_CTRL,2,4,IDIV,Integer divider D divider value (1/(IDIV + 1)),0x0,rw
|
||||
CGU_IDIVD_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_IDIVD_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_IDIVE_CTRL,0,1,PD,Integer divider power down,0,rw
|
||||
CGU_IDIVE_CTRL,2,8,IDIV,Integer divider E divider value (1/(IDIV + 1)),0x00,rw
|
||||
CGU_IDIVE_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_IDIVE_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_SAFE_CLK,0,1,PD,Output stage power down,0,r
|
||||
CGU_BASE_SAFE_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,r
|
||||
CGU_BASE_SAFE_CLK,24,5,CLK_SEL,Clock source selection,0x01,r
|
||||
CGU_BASE_USB0_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_USB0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_USB0_CLK,24,5,CLK_SEL,Clock source selection,0x07,rw
|
||||
CGU_BASE_PERIPH_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_PERIPH_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_PERIPH_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_USB1_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_USB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_USB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_M4_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_M4_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_M4_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_SPIFI_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_SPIFI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_SPIFI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_SPI_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_SPI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_SPI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_PHY_RX_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_PHY_RX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_PHY_RX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_PHY_TX_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_PHY_TX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_PHY_TX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_APB1_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_APB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_APB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_APB3_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_APB3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_APB3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_LCD_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_LCD_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_LCD_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_VADC_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_VADC_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_VADC_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_SDIO_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_SDIO_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_SDIO_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_SSP0_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_SSP0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_SSP0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_SSP1_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_SSP1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_SSP1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_UART0_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_UART0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_UART0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_UART1_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_UART1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_UART1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_UART2_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_UART2_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_UART2_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_UART3_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_UART3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_UART3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_OUT_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_OUT_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_OUT_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_APLL_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_APLL_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_APLL_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_CGU_OUT0_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_CGU_OUT0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_CGU_OUT0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
CGU_BASE_CGU_OUT1_CLK,0,1,PD,Output stage power down,0,rw
|
||||
CGU_BASE_CGU_OUT1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
|
||||
CGU_BASE_CGU_OUT1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
|
||||
|
|
|
@ -0,0 +1,937 @@
|
|||
!!omap
|
||||
- CGU_FREQ_MON:
|
||||
fields: !!omap
|
||||
- RCNT:
|
||||
access: rw
|
||||
description: 9-bit reference clock-counter value
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 9
|
||||
- FCNT:
|
||||
access: r
|
||||
description: 14-bit selected clock-counter value
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 14
|
||||
- MEAS:
|
||||
access: rw
|
||||
description: Measure frequency
|
||||
lsb: 23
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock-source selection for the clock to be measured
|
||||
lsb: 24
|
||||
reset_value: '0'
|
||||
width: 5
|
||||
- CGU_XTAL_OSC_CTRL:
|
||||
fields: !!omap
|
||||
- ENABLE:
|
||||
access: rw
|
||||
description: Oscillator-pad enable
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- BYPASS:
|
||||
access: rw
|
||||
description: Configure crystal operation or external-clock input pin XTAL1
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- HF:
|
||||
access: rw
|
||||
description: Select frequency range
|
||||
lsb: 2
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- CGU_PLL0USB_STAT:
|
||||
fields: !!omap
|
||||
- LOCK:
|
||||
access: r
|
||||
description: PLL0 lock indicator
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- FR:
|
||||
access: r
|
||||
description: PLL0 free running indicator
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CGU_PLL0USB_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: PLL0 power down
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- BYPASS:
|
||||
access: rw
|
||||
description: Input clock bypass control
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- DIRECTI:
|
||||
access: rw
|
||||
description: PLL0 direct input
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DIRECTO:
|
||||
access: rw
|
||||
description: PLL0 direct output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLKEN:
|
||||
access: rw
|
||||
description: PLL0 clock enable
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- FRM:
|
||||
access: rw
|
||||
description: Free running mode
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_PLL0USB_MDIV:
|
||||
fields: !!omap
|
||||
- MDEC:
|
||||
access: rw
|
||||
description: Decoded M-divider coefficient value
|
||||
lsb: 0
|
||||
reset_value: '0x5B6A'
|
||||
width: 17
|
||||
- SELP:
|
||||
access: rw
|
||||
description: Bandwidth select P value
|
||||
lsb: 17
|
||||
reset_value: '0x1C'
|
||||
width: 5
|
||||
- SELI:
|
||||
access: rw
|
||||
description: Bandwidth select I value
|
||||
lsb: 22
|
||||
reset_value: '0x17'
|
||||
width: 6
|
||||
- SELR:
|
||||
access: rw
|
||||
description: Bandwidth select R value
|
||||
lsb: 28
|
||||
reset_value: '0x0'
|
||||
width: 4
|
||||
- CGU_PLL0USB_NP_DIV:
|
||||
fields: !!omap
|
||||
- PDEC:
|
||||
access: rw
|
||||
description: Decoded P-divider coefficient value
|
||||
lsb: 0
|
||||
reset_value: '0x02'
|
||||
width: 7
|
||||
- NDEC:
|
||||
access: rw
|
||||
description: Decoded N-divider coefficient value
|
||||
lsb: 12
|
||||
reset_value: '0xB1'
|
||||
width: 10
|
||||
- CGU_PLL0AUDIO_STAT:
|
||||
fields: !!omap
|
||||
- LOCK:
|
||||
access: r
|
||||
description: PLL0 lock indicator
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- FR:
|
||||
access: r
|
||||
description: PLL0 free running indicator
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CGU_PLL0AUDIO_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: PLL0 power down
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- BYPASS:
|
||||
access: rw
|
||||
description: Input clock bypass control
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- DIRECTI:
|
||||
access: rw
|
||||
description: PLL0 direct input
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DIRECTO:
|
||||
access: rw
|
||||
description: PLL0 direct output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLKEN:
|
||||
access: rw
|
||||
description: PLL0 clock enable
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- FRM:
|
||||
access: rw
|
||||
description: Free running mode
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PLLFRACT_REQ:
|
||||
access: rw
|
||||
description: Fractional PLL word write request
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SEL_EXT:
|
||||
access: rw
|
||||
description: Select fractional divider
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- MOD_PD:
|
||||
access: rw
|
||||
description: Sigma-Delta modulator power-down
|
||||
lsb: 14
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_PLL0AUDIO_MDIV:
|
||||
fields: !!omap
|
||||
- MDEC:
|
||||
access: rw
|
||||
description: Decoded M-divider coefficient value
|
||||
lsb: 0
|
||||
reset_value: '0x5B6A'
|
||||
width: 17
|
||||
- CGU_PLL0AUDIO_NP_DIV:
|
||||
fields: !!omap
|
||||
- PDEC:
|
||||
access: rw
|
||||
description: Decoded P-divider coefficient value
|
||||
lsb: 0
|
||||
reset_value: '0x02'
|
||||
width: 7
|
||||
- NDEC:
|
||||
access: rw
|
||||
description: Decoded N-divider coefficient value
|
||||
lsb: 12
|
||||
reset_value: '0xB1'
|
||||
width: 10
|
||||
- CGU_PLLAUDIO_FRAC:
|
||||
fields: !!omap
|
||||
- PLLFRACT_CTRL:
|
||||
access: rw
|
||||
description: PLL fractional divider control word
|
||||
lsb: 0
|
||||
reset_value: '0x00'
|
||||
width: 22
|
||||
- CGU_PLL1_STAT:
|
||||
fields: !!omap
|
||||
- LOCK:
|
||||
access: r
|
||||
description: PLL1 lock indicator
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CGU_PLL1_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: PLL1 power down
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- BYPASS:
|
||||
access: rw
|
||||
description: Input clock bypass control
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- FBSEL:
|
||||
access: rw
|
||||
description: PLL feedback select
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- DIRECT:
|
||||
access: rw
|
||||
description: PLL direct CCO output
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PSEL:
|
||||
access: rw
|
||||
description: Post-divider division ratio P
|
||||
lsb: 8
|
||||
reset_value: '0x1'
|
||||
width: 2
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- NSEL:
|
||||
access: rw
|
||||
description: Pre-divider division ratio N
|
||||
lsb: 12
|
||||
reset_value: '0x2'
|
||||
width: 2
|
||||
- MSEL:
|
||||
access: rw
|
||||
description: Feedback-divider division ratio (M)
|
||||
lsb: 16
|
||||
reset_value: '0x18'
|
||||
width: 8
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock-source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_IDIVA_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Integer divider power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- IDIV:
|
||||
access: rw
|
||||
description: Integer divider A divider value (1/(IDIV + 1))
|
||||
lsb: 2
|
||||
reset_value: '0x0'
|
||||
width: 2
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_IDIVB_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Integer divider power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- IDIV:
|
||||
access: rw
|
||||
description: Integer divider B divider value (1/(IDIV + 1))
|
||||
lsb: 2
|
||||
reset_value: '0x0'
|
||||
width: 4
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_IDIVC_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Integer divider power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- IDIV:
|
||||
access: rw
|
||||
description: Integer divider C divider value (1/(IDIV + 1))
|
||||
lsb: 2
|
||||
reset_value: '0x0'
|
||||
width: 4
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_IDIVD_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Integer divider power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- IDIV:
|
||||
access: rw
|
||||
description: Integer divider D divider value (1/(IDIV + 1))
|
||||
lsb: 2
|
||||
reset_value: '0x0'
|
||||
width: 4
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_IDIVE_CTRL:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Integer divider power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- IDIV:
|
||||
access: rw
|
||||
description: Integer divider E divider value (1/(IDIV + 1))
|
||||
lsb: 2
|
||||
reset_value: '0x00'
|
||||
width: 8
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_SAFE_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: r
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: r
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: r
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_USB0_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x07'
|
||||
width: 5
|
||||
- CGU_BASE_PERIPH_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_USB1_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_M4_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_SPIFI_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_SPI_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_PHY_RX_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_PHY_TX_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_APB1_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_APB3_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_LCD_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_VADC_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_SDIO_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_SSP0_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_SSP1_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_UART0_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_UART1_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_UART2_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_UART3_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_OUT_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_APLL_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_CGU_OUT0_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
- CGU_BASE_CGU_OUT1_CLK:
|
||||
fields: !!omap
|
||||
- PD:
|
||||
access: rw
|
||||
description: Output stage power down
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- AUTOBLOCK:
|
||||
access: rw
|
||||
description: Block clock automatically during frequency change
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CLK_SEL:
|
||||
access: rw
|
||||
description: Clock source selection
|
||||
lsb: 24
|
||||
reset_value: '0x01'
|
||||
width: 5
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
CREG_CREG0,0,1,EN1KHZ,Enable 1 kHz output,0,rw
|
||||
CREG_CREG0,1,1,EN32KHZ,Enable 32 kHz output,0,rw
|
||||
CREG_CREG0,2,1,RESET32KHZ,32 kHz oscillator reset,1,rw
|
||||
CREG_CREG0,3,1,PD32KHZ,32 kHz power control,1,rw
|
||||
CREG_CREG0,5,1,USB0PHY,USB0 PHY power control,1,rw
|
||||
CREG_CREG0,6,2,ALARMCTRL,RTC_ALARM pin output control,0,rw
|
||||
CREG_CREG0,8,2,BODLVL1,BOD trip level to generate an interrupt,0x3,rw
|
||||
CREG_CREG0,10,2,BODLVL2,BOD trip level to generate a reset,0x3,rw
|
||||
CREG_CREG0,12,2,SAMPLECTRL,SAMPLE pin input/output control,0,rw
|
||||
CREG_CREG0,14,2,WAKEUP0CTRL,WAKEUP0 pin input/output control,0,rw
|
||||
CREG_CREG0,16,2,WAKEUP1CTRL,WAKEUP1 pin input/output control,0,rw
|
||||
CREG_M4MEMMAP,12,20,M4MAP,Shadow address when accessing memory at address 0x00000000,0x10400000,rw
|
||||
CREG_CREG5,6,1,M4TAPSEL,JTAG debug select for M4 core,1,rw
|
||||
CREG_CREG5,9,1,M0APPTAPSEL,JTAG debug select for M0 co-processor,1,rw
|
||||
CREG_DMAMUX,0,2,DMAMUXPER0,Select DMA to peripheral connection for DMA peripheral 0,0,rw
|
||||
CREG_DMAMUX,2,2,DMAMUXPER1,Select DMA to peripheral connection for DMA peripheral 1,0,rw
|
||||
CREG_DMAMUX,4,2,DMAMUXPER2,Select DMA to peripheral connection for DMA peripheral 2,0,rw
|
||||
CREG_DMAMUX,6,2,DMAMUXPER3,Select DMA to peripheral connection for DMA peripheral 3,0,rw
|
||||
CREG_DMAMUX,8,2,DMAMUXPER4,Select DMA to peripheral connection for DMA peripheral 4,0,rw
|
||||
CREG_DMAMUX,10,2,DMAMUXPER5,Select DMA to peripheral connection for DMA peripheral 5,0,rw
|
||||
CREG_DMAMUX,12,2,DMAMUXPER6,Select DMA to peripheral connection for DMA peripheral 6,0,rw
|
||||
CREG_DMAMUX,14,2,DMAMUXPER7,Select DMA to peripheral connection for DMA peripheral 7,0,rw
|
||||
CREG_DMAMUX,16,2,DMAMUXPER8,Select DMA to peripheral connection for DMA peripheral 8,0,rw
|
||||
CREG_DMAMUX,18,2,DMAMUXPER9,Select DMA to peripheral connection for DMA peripheral 9,0,rw
|
||||
CREG_DMAMUX,20,2,DMAMUXPER10,Select DMA to peripheral connection for DMA peripheral 10,0,rw
|
||||
CREG_DMAMUX,22,2,DMAMUXPER11,Select DMA to peripheral connection for DMA peripheral 11,0,rw
|
||||
CREG_DMAMUX,24,2,DMAMUXPER12,Select DMA to peripheral connection for DMA peripheral 12,0,rw
|
||||
CREG_DMAMUX,26,2,DMAMUXPER13,Select DMA to peripheral connection for DMA peripheral 13,0,rw
|
||||
CREG_DMAMUX,28,2,DMAMUXPER14,Select DMA to peripheral connection for DMA peripheral 14,0,rw
|
||||
CREG_DMAMUX,30,2,DMAMUXPER15,Select DMA to peripheral connection for DMA peripheral 15,0,rw
|
||||
CREG_FLASHCFGA,12,4,FLASHTIM,Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access,,rw
|
||||
CREG_FLASHCFGA,31,1,POW,Flash bank A power control,1,rw
|
||||
CREG_FLASHCFGB,12,4,FLASHTIM,Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access,,rw
|
||||
CREG_FLASHCFGB,31,1,POW,Flash bank B power control,1,rw
|
||||
CREG_ETBCFG,0,1,ETB,Select SRAM interface,1,rw
|
||||
CREG_CREG6,0,3,ETHMODE,Selects the Ethernet mode. Reset the ethernet after changing the PHY interface,,rw
|
||||
CREG_CREG6,4,1,CTOUTCTRL,Selects the functionality of the SCT outputs,0,rw
|
||||
CREG_CREG6,12,1,I2S0_TX_SCK_IN_SEL,I2S0_TX_SCK input select,0,rw
|
||||
CREG_CREG6,13,1,I2S0_RX_SCK_IN_SEL,I2S0_RX_SCK input select,0,rw
|
||||
CREG_CREG6,14,1,I2S1_TX_SCK_IN_SEL,I2S1_TX_SCK input select,0,rw
|
||||
CREG_CREG6,15,1,I2S1_RX_SCK_IN_SEL,I2S1_RX_SCK input select,0,rw
|
||||
CREG_CREG6,16,1,EMC_CLK_SEL,EMC_CLK divided clock select,0,rw
|
||||
CREG_M4TXEVENT,0,1,TXEVCLR,Cortex-M4 TXEV event,0,rw
|
||||
CREG_M0TXEVENT,0,1,TXEVCLR,Cortex-M0 TXEV event,0,rw
|
||||
CREG_M0APPMEMMAP,12,20,M0APPMAP,Shadow address when accessing memory at address 0x00000000,0x20000000,rw
|
||||
CREG_USB0FLADJ,0,6,FLTV,Frame length timing value,0x20,rw
|
||||
CREG_USB1FLADJ,0,6,FLTV,Frame length timing value,0x20,rw
|
||||
|
|
|
@ -0,0 +1,312 @@
|
|||
!!omap
|
||||
- CREG_CREG0:
|
||||
fields: !!omap
|
||||
- EN1KHZ:
|
||||
access: rw
|
||||
description: Enable 1 kHz output
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EN32KHZ:
|
||||
access: rw
|
||||
description: Enable 32 kHz output
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET32KHZ:
|
||||
access: rw
|
||||
description: 32 kHz oscillator reset
|
||||
lsb: 2
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- PD32KHZ:
|
||||
access: rw
|
||||
description: 32 kHz power control
|
||||
lsb: 3
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- USB0PHY:
|
||||
access: rw
|
||||
description: USB0 PHY power control
|
||||
lsb: 5
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- ALARMCTRL:
|
||||
access: rw
|
||||
description: RTC_ALARM pin output control
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- BODLVL1:
|
||||
access: rw
|
||||
description: BOD trip level to generate an interrupt
|
||||
lsb: 8
|
||||
reset_value: '0x3'
|
||||
width: 2
|
||||
- BODLVL2:
|
||||
access: rw
|
||||
description: BOD trip level to generate a reset
|
||||
lsb: 10
|
||||
reset_value: '0x3'
|
||||
width: 2
|
||||
- SAMPLECTRL:
|
||||
access: rw
|
||||
description: SAMPLE pin input/output control
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- WAKEUP0CTRL:
|
||||
access: rw
|
||||
description: WAKEUP0 pin input/output control
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- WAKEUP1CTRL:
|
||||
access: rw
|
||||
description: WAKEUP1 pin input/output control
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- CREG_M4MEMMAP:
|
||||
fields: !!omap
|
||||
- M4MAP:
|
||||
access: rw
|
||||
description: Shadow address when accessing memory at address 0x00000000
|
||||
lsb: 12
|
||||
reset_value: '0x10400000'
|
||||
width: 20
|
||||
- CREG_CREG5:
|
||||
fields: !!omap
|
||||
- M4TAPSEL:
|
||||
access: rw
|
||||
description: JTAG debug select for M4 core
|
||||
lsb: 6
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- M0APPTAPSEL:
|
||||
access: rw
|
||||
description: JTAG debug select for M0 co-processor
|
||||
lsb: 9
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- CREG_DMAMUX:
|
||||
fields: !!omap
|
||||
- DMAMUXPER0:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 0
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER1:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 1
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER2:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 2
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER3:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 3
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER4:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 4
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER5:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 5
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER6:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 6
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER7:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 7
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER8:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 8
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER9:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 9
|
||||
lsb: 18
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER10:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 10
|
||||
lsb: 20
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER11:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 11
|
||||
lsb: 22
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER12:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 12
|
||||
lsb: 24
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER13:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 13
|
||||
lsb: 26
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER14:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 14
|
||||
lsb: 28
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- DMAMUXPER15:
|
||||
access: rw
|
||||
description: Select DMA to peripheral connection for DMA peripheral 15
|
||||
lsb: 30
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- CREG_FLASHCFGA:
|
||||
fields: !!omap
|
||||
- FLASHTIM:
|
||||
access: rw
|
||||
description: Flash access time. The value of this field plus 1 gives the number
|
||||
of BASE_M4_CLK clocks used for a flash access
|
||||
lsb: 12
|
||||
reset_value: ''
|
||||
width: 4
|
||||
- POW:
|
||||
access: rw
|
||||
description: Flash bank A power control
|
||||
lsb: 31
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- CREG_FLASHCFGB:
|
||||
fields: !!omap
|
||||
- FLASHTIM:
|
||||
access: rw
|
||||
description: Flash access time. The value of this field plus 1 gives the number
|
||||
of BASE_M4_CLK clocks used for a flash access
|
||||
lsb: 12
|
||||
reset_value: ''
|
||||
width: 4
|
||||
- POW:
|
||||
access: rw
|
||||
description: Flash bank B power control
|
||||
lsb: 31
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- CREG_ETBCFG:
|
||||
fields: !!omap
|
||||
- ETB:
|
||||
access: rw
|
||||
description: Select SRAM interface
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- CREG_CREG6:
|
||||
fields: !!omap
|
||||
- ETHMODE:
|
||||
access: rw
|
||||
description: Selects the Ethernet mode. Reset the ethernet after changing
|
||||
the PHY interface
|
||||
lsb: 0
|
||||
reset_value: ''
|
||||
width: 3
|
||||
- CTOUTCTRL:
|
||||
access: rw
|
||||
description: Selects the functionality of the SCT outputs
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S0_TX_SCK_IN_SEL:
|
||||
access: rw
|
||||
description: I2S0_TX_SCK input select
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S0_RX_SCK_IN_SEL:
|
||||
access: rw
|
||||
description: I2S0_RX_SCK input select
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S1_TX_SCK_IN_SEL:
|
||||
access: rw
|
||||
description: I2S1_TX_SCK input select
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S1_RX_SCK_IN_SEL:
|
||||
access: rw
|
||||
description: I2S1_RX_SCK input select
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EMC_CLK_SEL:
|
||||
access: rw
|
||||
description: EMC_CLK divided clock select
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CREG_M4TXEVENT:
|
||||
fields: !!omap
|
||||
- TXEVCLR:
|
||||
access: rw
|
||||
description: Cortex-M4 TXEV event
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CREG_M0TXEVENT:
|
||||
fields: !!omap
|
||||
- TXEVCLR:
|
||||
access: rw
|
||||
description: Cortex-M0 TXEV event
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CREG_M0APPMEMMAP:
|
||||
fields: !!omap
|
||||
- M0APPMAP:
|
||||
access: rw
|
||||
description: Shadow address when accessing memory at address 0x00000000
|
||||
lsb: 12
|
||||
reset_value: '0x20000000'
|
||||
width: 20
|
||||
- CREG_USB0FLADJ:
|
||||
fields: !!omap
|
||||
- FLTV:
|
||||
access: rw
|
||||
description: Frame length timing value
|
||||
lsb: 0
|
||||
reset_value: '0x20'
|
||||
width: 6
|
||||
- CREG_USB1FLADJ:
|
||||
fields: !!omap
|
||||
- FLTV:
|
||||
access: rw
|
||||
description: Frame length timing value
|
||||
lsb: 0
|
||||
reset_value: '0x20'
|
||||
width: 6
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
EVENTROUTER_HILO,0,1,WAKEUP0_L,Level detect mode for WAKEUP0 event,0,rw
|
||||
EVENTROUTER_HILO,1,1,WAKEUP1_L,Level detect mode for WAKEUP1 event,0,rw
|
||||
EVENTROUTER_HILO,2,1,WAKEUP2_L,Level detect mode for WAKEUP2 event,0,rw
|
||||
EVENTROUTER_HILO,3,1,WAKEUP3_L,Level detect mode for WAKEUP3 event,0,rw
|
||||
EVENTROUTER_HILO,4,1,ATIMER_L,Level detect mode for alarm timer event,0,rw
|
||||
EVENTROUTER_HILO,5,1,RTC_L,Level detect mode for RTC event,0,rw
|
||||
EVENTROUTER_HILO,6,1,BOD_L,Level detect mode for BOD event,0,rw
|
||||
EVENTROUTER_HILO,7,1,WWDT_L,Level detect mode for WWDT event,0,rw
|
||||
EVENTROUTER_HILO,8,1,ETH_L,Level detect mode for Ethernet event,0,rw
|
||||
EVENTROUTER_HILO,9,1,USB0_L,Level detect mode for USB0 event,0,rw
|
||||
EVENTROUTER_HILO,10,1,USB1_L,Level detect mode for USB1 event,0,rw
|
||||
EVENTROUTER_HILO,11,1,SDMMC_L,Level detect mode for SD/MMC event,0,rw
|
||||
EVENTROUTER_HILO,12,1,CAN_L,Level detect mode for C_CAN event,0,rw
|
||||
EVENTROUTER_HILO,13,1,TIM2_L,Level detect mode for combined timer output 2 event,0,rw
|
||||
EVENTROUTER_HILO,14,1,TIM6_L,Level detect mode for combined timer output 6 event,0,rw
|
||||
EVENTROUTER_HILO,15,1,QEI_L,Level detect mode for QEI event,0,rw
|
||||
EVENTROUTER_HILO,16,1,TIM14_L,Level detect mode for combined timer output 14 event,0,rw
|
||||
EVENTROUTER_HILO,19,1,RESET_L,Level detect mode for Reset,0,rw
|
||||
EVENTROUTER_EDGE,0,1,WAKEUP0_E,Edge/Level detect mode for WAKEUP0 event,0,rw
|
||||
EVENTROUTER_EDGE,1,1,WAKEUP1_E,Edge/Level detect mode for WAKEUP1 event,0,rw
|
||||
EVENTROUTER_EDGE,2,1,WAKEUP2_E,Edge/Level detect mode for WAKEUP2 event,0,rw
|
||||
EVENTROUTER_EDGE,3,1,WAKEUP3_E,Edge/Level detect mode for WAKEUP3 event,0,rw
|
||||
EVENTROUTER_EDGE,4,1,ATIMER_E,Edge/Level detect mode for alarm timer event,0,rw
|
||||
EVENTROUTER_EDGE,5,1,RTC_E,Edge/Level detect mode for RTC event,0,rw
|
||||
EVENTROUTER_EDGE,6,1,BOD_E,Edge/Level detect mode for BOD event,0,rw
|
||||
EVENTROUTER_EDGE,7,1,WWDT_E,Edge/Level detect mode for WWDT event,0,rw
|
||||
EVENTROUTER_EDGE,8,1,ETH_E,Edge/Level detect mode for Ethernet event,0,rw
|
||||
EVENTROUTER_EDGE,9,1,USB0_E,Edge/Level detect mode for USB0 event,0,rw
|
||||
EVENTROUTER_EDGE,10,1,USB1_E,Edge/Level detect mode for USB1 event,0,rw
|
||||
EVENTROUTER_EDGE,11,1,SDMMC_E,Edge/Level detect mode for SD/MMC event,0,rw
|
||||
EVENTROUTER_EDGE,12,1,CAN_E,Edge/Level detect mode for C_CAN event,0,rw
|
||||
EVENTROUTER_EDGE,13,1,TIM2_E,Edge/Level detect mode for combined timer output 2 event,0,rw
|
||||
EVENTROUTER_EDGE,14,1,TIM6_E,Edge/Level detect mode for combined timer output 6 event,0,rw
|
||||
EVENTROUTER_EDGE,15,1,QEI_E,Edge/Level detect mode for QEI event,0,rw
|
||||
EVENTROUTER_EDGE,16,1,TIM14_E,Edge/Level detect mode for combined timer output 14 event,0,rw
|
||||
EVENTROUTER_EDGE,19,1,RESET_E,Edge/Level detect mode for Reset,0,rw
|
||||
EVENTROUTER_CLR_EN,0,1,WAKEUP0_CLREN,Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,1,1,WAKEUP1_CLREN,Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,2,1,WAKEUP2_CLREN,Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,3,1,WAKEUP3_CLREN,Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,4,1,ATIMER_CLREN,Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,5,1,RTC_CLREN,Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,6,1,BOD_CLREN,Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,7,1,WWDT_CLREN,Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,8,1,ETH_CLREN,Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,9,1,USB0_CLREN,Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,10,1,USB1_CLREN,Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,11,1,SDMCC_CLREN,Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,12,1,CAN_CLREN,Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,13,1,TIM2_CLREN,Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,14,1,TIM6_CLREN,Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,15,1,QEI_CLREN,Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,16,1,TIM14_CLREN,Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register,0,w
|
||||
EVENTROUTER_CLR_EN,19,1,RESET_CLREN,Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,0,1,WAKEUP0_SETEN,Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,1,1,WAKEUP1_SETEN,Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,2,1,WAKEUP2_SETEN,Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,3,1,WAKEUP3_SETEN,Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,4,1,ATIMER_SETEN,Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,5,1,RTC_SETEN,Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,6,1,BOD_SETEN,Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,7,1,WWDT_SETEN,Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,8,1,ETH_SETEN,Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,9,1,USB0_SETEN,Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,10,1,USB1_SETEN,Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,11,1,SDMCC_SETEN,Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,12,1,CAN_SETEN,Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,13,1,TIM2_SETEN,Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,14,1,TIM6_SETEN,Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,15,1,QEI_SETEN,Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,16,1,TIM14_SETEN,Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register,0,w
|
||||
EVENTROUTER_SET_EN,19,1,RESET_SETEN,Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register,0,w
|
||||
EVENTROUTER_STATUS,0,1,WAKEUP0_ST,A 1 in this bit shows that the WAKEUP0 event has been raised,1,r
|
||||
EVENTROUTER_STATUS,1,1,WAKEUP1_ST,A 1 in this bit shows that the WAKEUP1 event has been raised,1,r
|
||||
EVENTROUTER_STATUS,2,1,WAKEUP2_ST,A 1 in this bit shows that the WAKEUP2 event has been raised,1,r
|
||||
EVENTROUTER_STATUS,3,1,WAKEUP3_ST,A 1 in this bit shows that the WAKEUP3 event has been raised,1,r
|
||||
EVENTROUTER_STATUS,4,1,ATIMER_ST,A 1 in this bit shows that the ATIMER event has been raised,1,r
|
||||
EVENTROUTER_STATUS,5,1,RTC_ST,A 1 in this bit shows that the RTC event has been raised,1,r
|
||||
EVENTROUTER_STATUS,6,1,BOD_ST,A 1 in this bit shows that the BOD event has been raised,1,r
|
||||
EVENTROUTER_STATUS,7,1,WWDT_ST,A 1 in this bit shows that the WWDT event has been raised,1,r
|
||||
EVENTROUTER_STATUS,8,1,ETH_ST,A 1 in this bit shows that the ETH event has been raised,1,r
|
||||
EVENTROUTER_STATUS,9,1,USB0_ST,A 1 in this bit shows that the USB0 event has been raised,1,r
|
||||
EVENTROUTER_STATUS,10,1,USB1_ST,A 1 in this bit shows that the USB1 event has been raised,1,r
|
||||
EVENTROUTER_STATUS,11,1,SDMMC_ST,A 1 in this bit shows that the SDMMC event has been raised,1,r
|
||||
EVENTROUTER_STATUS,12,1,CAN_ST,A 1 in this bit shows that the CAN event has been raised,1,r
|
||||
EVENTROUTER_STATUS,13,1,TIM2_ST,A 1 in this bit shows that the combined timer 2 output event has been raised,1,r
|
||||
EVENTROUTER_STATUS,14,1,TIM6_ST,A 1 in this bit shows that the combined timer 6 output event has been raised,1,r
|
||||
EVENTROUTER_STATUS,15,1,QEI_ST,A 1 in this bit shows that the QEI event has been raised,1,r
|
||||
EVENTROUTER_STATUS,16,1,TIM14_ST,A 1 in this bit shows that the combined timer 14 output event has been raised,1,r
|
||||
EVENTROUTER_STATUS,19,1,RESET_ST,A 1 in this bit shows that the reset event has been raised,1,r
|
||||
EVENTROUTER_ENABLE,0,1,WAKEUP0_EN,A 1 in this bit shows that the WAKEUP0 event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,1,1,WAKEUP1_EN,A 1 in this bit shows that the WAKEUP1 event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,2,1,WAKEUP2_EN,A 1 in this bit shows that the WAKEUP2 event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,3,1,WAKEUP3_EN,A 1 in this bit shows that the WAKEUP3 event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,4,1,ATIMER_EN,A 1 in this bit shows that the ATIMER event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,5,1,RTC_EN,A 1 in this bit shows that the RTC event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,6,1,BOD_EN,A 1 in this bit shows that the BOD event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,7,1,WWDT_EN,A 1 in this bit shows that the WWDT event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,8,1,ETH_EN,A 1 in this bit shows that the ETH event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,9,1,USB0_EN,A 1 in this bit shows that the USB0 event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,10,1,USB1_EN,A 1 in this bit shows that the USB1 event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,11,1,SDMMC_EN,A 1 in this bit shows that the SDMMC event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,12,1,CAN_EN,A 1 in this bit shows that the CAN event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,13,1,TIM2_EN,A 1 in this bit shows that the combined timer 2 output event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,14,1,TIM6_EN,A 1 in this bit shows that the combined timer 6 output event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,15,1,QEI_EN,A 1 in this bit shows that the QEI event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,16,1,TIM14_EN,A 1 in this bit shows that the combined timer 14 output event has been enabled,0,r
|
||||
EVENTROUTER_ENABLE,19,1,RESET_EN,A 1 in this bit shows that the reset event has been enabled,0,r
|
||||
EVENTROUTER_CLR_STAT,0,1,WAKEUP0_CLRST,Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,1,1,WAKEUP1_CLRST,Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,2,1,WAKEUP2_CLRST,Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,3,1,WAKEUP3_CLRST,Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,4,1,ATIMER_CLRST,Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,5,1,RTC_CLRST,Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,6,1,BOD_CLRST,Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,7,1,WWDT_CLRST,Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,8,1,ETH_CLRST,Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,9,1,USB0_CLRST,Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,10,1,USB1_CLRST,Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,11,1,SDMCC_CLRST,Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,12,1,CAN_CLRST,Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,13,1,TIM2_CLRST,Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,14,1,TIM6_CLRST,Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,15,1,QEI_CLRST,Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,16,1,TIM14_CLRST,Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register,0,w
|
||||
EVENTROUTER_CLR_STAT,19,1,RESET_CLRST,Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,0,1,WAKEUP0_SETST,Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,1,1,WAKEUP1_SETST,Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,2,1,WAKEUP2_SETST,Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,3,1,WAKEUP3_SETST,Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,4,1,ATIMER_SETST,Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,5,1,RTC_SETST,Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,6,1,BOD_SETST,Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,7,1,WWDT_SETST,Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,8,1,ETH_SETST,Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,9,1,USB0_SETST,Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,10,1,USB1_SETST,Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,11,1,SDMCC_SETST,Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,12,1,CAN_SETST,Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,13,1,TIM2_SETST,Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,14,1,TIM6_SETST,Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,15,1,QEI_SETST,Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,16,1,TIM14_SETST,Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register,0,w
|
||||
EVENTROUTER_SET_STAT,19,1,RESET_SETST,Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register,0,w
|
||||
|
|
|
@ -0,0 +1,959 @@
|
|||
!!omap
|
||||
- EVENTROUTER_HILO:
|
||||
fields: !!omap
|
||||
- WAKEUP0_L:
|
||||
access: rw
|
||||
description: Level detect mode for WAKEUP0 event
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP1_L:
|
||||
access: rw
|
||||
description: Level detect mode for WAKEUP1 event
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP2_L:
|
||||
access: rw
|
||||
description: Level detect mode for WAKEUP2 event
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP3_L:
|
||||
access: rw
|
||||
description: Level detect mode for WAKEUP3 event
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_L:
|
||||
access: rw
|
||||
description: Level detect mode for alarm timer event
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTC_L:
|
||||
access: rw
|
||||
description: Level detect mode for RTC event
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BOD_L:
|
||||
access: rw
|
||||
description: Level detect mode for BOD event
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WWDT_L:
|
||||
access: rw
|
||||
description: Level detect mode for WWDT event
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ETH_L:
|
||||
access: rw
|
||||
description: Level detect mode for Ethernet event
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB0_L:
|
||||
access: rw
|
||||
description: Level detect mode for USB0 event
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB1_L:
|
||||
access: rw
|
||||
description: Level detect mode for USB1 event
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SDMMC_L:
|
||||
access: rw
|
||||
description: Level detect mode for SD/MMC event
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CAN_L:
|
||||
access: rw
|
||||
description: Level detect mode for C_CAN event
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM2_L:
|
||||
access: rw
|
||||
description: Level detect mode for combined timer output 2 event
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM6_L:
|
||||
access: rw
|
||||
description: Level detect mode for combined timer output 6 event
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- QEI_L:
|
||||
access: rw
|
||||
description: Level detect mode for QEI event
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM14_L:
|
||||
access: rw
|
||||
description: Level detect mode for combined timer output 14 event
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET_L:
|
||||
access: rw
|
||||
description: Level detect mode for Reset
|
||||
lsb: 19
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EVENTROUTER_EDGE:
|
||||
fields: !!omap
|
||||
- WAKEUP0_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for WAKEUP0 event
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP1_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for WAKEUP1 event
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP2_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for WAKEUP2 event
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP3_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for WAKEUP3 event
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for alarm timer event
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTC_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for RTC event
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BOD_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for BOD event
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WWDT_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for WWDT event
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ETH_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for Ethernet event
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB0_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for USB0 event
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB1_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for USB1 event
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SDMMC_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for SD/MMC event
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CAN_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for C_CAN event
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM2_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for combined timer output 2 event
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM6_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for combined timer output 6 event
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- QEI_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for QEI event
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM14_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for combined timer output 14 event
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET_E:
|
||||
access: rw
|
||||
description: Edge/Level detect mode for Reset
|
||||
lsb: 19
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EVENTROUTER_CLR_EN:
|
||||
fields: !!omap
|
||||
- WAKEUP0_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 0 in the
|
||||
ENABLE register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP1_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 1 in the
|
||||
ENABLE register
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP2_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 2 in the
|
||||
ENABLE register
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP3_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 3 in the
|
||||
ENABLE register
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 4 in the
|
||||
ENABLE register
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTC_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 5 in the
|
||||
ENABLE register
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BOD_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 6 in the
|
||||
ENABLE register
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WWDT_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 7 in the
|
||||
ENABLE register
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ETH_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 8 in the
|
||||
ENABLE register
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB0_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 9 in the
|
||||
ENABLE register
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB1_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 10 in the
|
||||
ENABLE register
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SDMCC_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 11 in the
|
||||
ENABLE register
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CAN_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 12 in the
|
||||
ENABLE register
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM2_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 13 in the
|
||||
ENABLE register
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM6_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 14 in the
|
||||
ENABLE register
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- QEI_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 15 in the
|
||||
ENABLE register
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM14_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 16 in the
|
||||
ENABLE register
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET_CLREN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the event enable bit 19 in the
|
||||
ENABLE register
|
||||
lsb: 19
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EVENTROUTER_SET_EN:
|
||||
fields: !!omap
|
||||
- WAKEUP0_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 0 in the ENABLE
|
||||
register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP1_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 1 in the ENABLE
|
||||
register
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP2_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 2 in the ENABLE
|
||||
register
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP3_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 3 in the ENABLE
|
||||
register
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 4 in the ENABLE
|
||||
register
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTC_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 5 in the ENABLE
|
||||
register
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BOD_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 6 in the ENABLE
|
||||
register
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WWDT_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 7 in the ENABLE
|
||||
register
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ETH_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 8 in the ENABLE
|
||||
register
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB0_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 9 in the ENABLE
|
||||
register
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB1_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 10 in the ENABLE
|
||||
register
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SDMCC_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 11 in the ENABLE
|
||||
register
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CAN_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 12 in the ENABLE
|
||||
register
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM2_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 13 in the ENABLE
|
||||
register
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM6_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 14 in the ENABLE
|
||||
register
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- QEI_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 15 in the ENABLE
|
||||
register
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM14_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 16 in the ENABLE
|
||||
register
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET_SETEN:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the event enable bit 19 in the ENABLE
|
||||
register
|
||||
lsb: 19
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EVENTROUTER_STATUS:
|
||||
fields: !!omap
|
||||
- WAKEUP0_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP0 event has been raised
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WAKEUP1_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP1 event has been raised
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WAKEUP2_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP2 event has been raised
|
||||
lsb: 2
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WAKEUP3_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP3 event has been raised
|
||||
lsb: 3
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- ATIMER_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the ATIMER event has been raised
|
||||
lsb: 4
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RTC_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the RTC event has been raised
|
||||
lsb: 5
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- BOD_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the BOD event has been raised
|
||||
lsb: 6
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WWDT_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WWDT event has been raised
|
||||
lsb: 7
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- ETH_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the ETH event has been raised
|
||||
lsb: 8
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- USB0_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the USB0 event has been raised
|
||||
lsb: 9
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- USB1_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the USB1 event has been raised
|
||||
lsb: 10
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- SDMMC_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the SDMMC event has been raised
|
||||
lsb: 11
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- CAN_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the CAN event has been raised
|
||||
lsb: 12
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- TIM2_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the combined timer 2 output event
|
||||
has been raised
|
||||
lsb: 13
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- TIM6_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the combined timer 6 output event
|
||||
has been raised
|
||||
lsb: 14
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- QEI_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the QEI event has been raised
|
||||
lsb: 15
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- TIM14_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the combined timer 14 output event
|
||||
has been raised
|
||||
lsb: 16
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RESET_ST:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the reset event has been raised
|
||||
lsb: 19
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- EVENTROUTER_ENABLE:
|
||||
fields: !!omap
|
||||
- WAKEUP0_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP0 event has been enabled
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP1_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP1 event has been enabled
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP2_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP2 event has been enabled
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP3_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WAKEUP3 event has been enabled
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the ATIMER event has been enabled
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTC_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the RTC event has been enabled
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BOD_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the BOD event has been enabled
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WWDT_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the WWDT event has been enabled
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ETH_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the ETH event has been enabled
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB0_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the USB0 event has been enabled
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB1_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the USB1 event has been enabled
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SDMMC_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the SDMMC event has been enabled
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CAN_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the CAN event has been enabled
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM2_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the combined timer 2 output event
|
||||
has been enabled
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM6_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the combined timer 6 output event
|
||||
has been enabled
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- QEI_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the QEI event has been enabled
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM14_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the combined timer 14 output event
|
||||
has been enabled
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET_EN:
|
||||
access: r
|
||||
description: A 1 in this bit shows that the reset event has been enabled
|
||||
lsb: 19
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EVENTROUTER_CLR_STAT:
|
||||
fields: !!omap
|
||||
- WAKEUP0_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 0 in the
|
||||
STATUS register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP1_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 1 in the
|
||||
STATUS register
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP2_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 2 in the
|
||||
STATUS register
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP3_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 3 in the
|
||||
STATUS register
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 4 in the
|
||||
STATUS register
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTC_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 5 in the
|
||||
STATUS register
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BOD_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 6 in the
|
||||
STATUS register
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WWDT_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 7 in the
|
||||
STATUS register
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ETH_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 8 in the
|
||||
STATUS register
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB0_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 9 in the
|
||||
STATUS register
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB1_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 10 in the
|
||||
STATUS register
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SDMCC_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 11 in the
|
||||
STATUS register
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CAN_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 12 in the
|
||||
STATUS register
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM2_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 13 in the
|
||||
STATUS register
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM6_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 14 in the
|
||||
STATUS register
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- QEI_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 15 in the
|
||||
STATUS register
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM14_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 16 in the
|
||||
STATUS register
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET_CLRST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the STATUS event bit 19 in the
|
||||
STATUS register
|
||||
lsb: 19
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EVENTROUTER_SET_STAT:
|
||||
fields: !!omap
|
||||
- WAKEUP0_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS
|
||||
register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP1_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS
|
||||
register
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP2_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS
|
||||
register
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WAKEUP3_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS
|
||||
register
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ATIMER_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS
|
||||
register
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTC_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS
|
||||
register
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BOD_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS
|
||||
register
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WWDT_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS
|
||||
register
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ETH_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS
|
||||
register
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB0_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS
|
||||
register
|
||||
lsb: 9
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- USB1_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS
|
||||
register
|
||||
lsb: 10
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SDMCC_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS
|
||||
register
|
||||
lsb: 11
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CAN_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS
|
||||
register
|
||||
lsb: 12
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM2_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS
|
||||
register
|
||||
lsb: 13
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM6_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS
|
||||
register
|
||||
lsb: 14
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- QEI_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS
|
||||
register
|
||||
lsb: 15
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TIM14_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS
|
||||
register
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET_SETST:
|
||||
access: w
|
||||
description: Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS
|
||||
register
|
||||
lsb: 19
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
GIMA_CAP0_0_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP0_0_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP0_0_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP0_0_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP0_0_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP0_1_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP0_1_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP0_1_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP0_1_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP0_1_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP0_2_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP0_2_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP0_2_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP0_2_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP0_2_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP0_3_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP0_3_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP0_3_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP0_3_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP0_3_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP1_0_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP1_0_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP1_0_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP1_0_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP1_0_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP1_1_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP1_1_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP1_1_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP1_1_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP1_1_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP1_2_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP1_2_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP1_2_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP1_2_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP1_2_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP1_3_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP1_3_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP1_3_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP1_3_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP1_3_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP2_0_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP2_0_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP2_0_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP2_0_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP2_0_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP2_1_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP2_1_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP2_1_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP2_1_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP2_1_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP2_2_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP2_2_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP2_2_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP2_2_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP2_2_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP2_3_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP2_3_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP2_3_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP2_3_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP2_3_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP3_0_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP3_0_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP3_0_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP3_0_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP3_0_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP3_1_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP3_1_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP3_1_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP3_1_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP3_1_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP3_2_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP3_2_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP3_2_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP3_2_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP3_2_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CAP3_3_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CAP3_3_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CAP3_3_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CAP3_3_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CAP3_3_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_0_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_0_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_0_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_0_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_0_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_1_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_1_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_1_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_1_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_1_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_2_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_2_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_2_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_2_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_2_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_3_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_3_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_3_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_3_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_3_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_4_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_4_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_4_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_4_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_4_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_5_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_5_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_5_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_5_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_5_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_6_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_6_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_6_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_6_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_6_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_CTIN_7_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_CTIN_7_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_CTIN_7_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_CTIN_7_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_CTIN_7_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_VADC_TRIGGER_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_VADC_TRIGGER_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_VADC_TRIGGER_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_VADC_TRIGGER_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_VADC_TRIGGER_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_EVENTROUTER_13_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_EVENTROUTER_13_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_EVENTROUTER_13_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_EVENTROUTER_13_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_EVENTROUTER_13_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_EVENTROUTER_14_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_EVENTROUTER_14_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_EVENTROUTER_14_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_EVENTROUTER_14_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_EVENTROUTER_14_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_EVENTROUTER_16_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_EVENTROUTER_16_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_EVENTROUTER_16_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_EVENTROUTER_16_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_EVENTROUTER_16_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_ADCSTART0_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_ADCSTART0_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_ADCSTART0_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_ADCSTART0_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_ADCSTART0_IN,4,4,SELECT,Select input,0,rw
|
||||
GIMA_ADCSTART1_IN,0,1,INV,Invert input,0,rw
|
||||
GIMA_ADCSTART1_IN,1,1,EDGE,Enable rising edge detection,0,rw
|
||||
GIMA_ADCSTART1_IN,2,1,SYNCH,Enable synchronization,0,rw
|
||||
GIMA_ADCSTART1_IN,3,1,PULSE,Enable single pulse generation,0,rw
|
||||
GIMA_ADCSTART1_IN,4,4,SELECT,Select input,0,rw
|
||||
|
|
|
@ -0,0 +1,961 @@
|
|||
!!omap
|
||||
- GIMA_CAP0_0_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP0_1_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP0_2_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP0_3_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP1_0_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP1_1_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP1_2_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP1_3_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP2_0_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP2_1_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP2_2_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP2_3_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP3_0_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP3_1_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP3_2_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CAP3_3_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_0_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_1_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_2_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_3_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_4_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_5_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_6_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_CTIN_7_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_VADC_TRIGGER_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_EVENTROUTER_13_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_EVENTROUTER_14_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_EVENTROUTER_16_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_ADCSTART0_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- GIMA_ADCSTART1_IN:
|
||||
fields: !!omap
|
||||
- INV:
|
||||
access: rw
|
||||
description: Invert input
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- EDGE:
|
||||
access: rw
|
||||
description: Enable rising edge detection
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SYNCH:
|
||||
access: rw
|
||||
description: Enable synchronization
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- PULSE:
|
||||
access: rw
|
||||
description: Enable single pulse generation
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SELECT:
|
||||
access: rw
|
||||
description: Select input
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
|
|
@ -1,224 +0,0 @@
|
|||
GPDMA_INTSTAT,0,8,INTSTAT,Status of DMA channel interrupts after masking,0x00,r
|
||||
GPDMA_INTTCSTAT,0,8,INTTCSTAT,Terminal count interrupt request status for DMA channels,0x00,r
|
||||
GPDMA_INTTCCLEAR,0,8,INTTCCLEAR,Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels,0x00,w
|
||||
GPDMA_INTERRSTAT,0,8,INTERRSTAT,Interrupt error status for DMA channels,0x00,r
|
||||
GPDMA_INTERRCLR,0,8,INTERRCLR,Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels,0x00,w
|
||||
GPDMA_RAWINTTCSTAT,0,8,RAWINTTCSTAT,Status of the terminal count interrupt for DMA channels prior to masking,0x00,r
|
||||
GPDMA_RAWINTERRSTAT,0,8,RAWINTERRSTAT,Status of the error interrupt for DMA channels prior to masking,0x00,r
|
||||
GPDMA_ENBLDCHNS,0,8,ENABLEDCHANNELS,Enable status for DMA channels,0x00,r
|
||||
GPDMA_SOFTBREQ,0,16,SOFTBREQ,Software burst request flags for each of 16 possible sources,0x00,rw
|
||||
GPDMA_SOFTSREQ,0,16,SOFTSREQ,Software single transfer request flags for each of 16 possible sources,0x00,rw
|
||||
GPDMA_SOFTLBREQ,0,16,SOFTLBREQ,Software last burst request flags for each of 16 possible sources,0x00,rw
|
||||
GPDMA_SOFTLSREQ,0,16,SOFTLSREQ,Software last single transfer request flags for each of 16 possible sources,0x00,rw
|
||||
GPDMA_CONFIG,0,1,E,DMA Controller enable,0,rw
|
||||
GPDMA_CONFIG,1,1,M0,AHB Master 0 endianness configuration,0,rw
|
||||
GPDMA_CONFIG,2,1,M1,AHB Master 1 endianness configuration,0,rw
|
||||
GPDMA_SYNC,0,16,DMACSYNC,Controls the synchronization logic for DMA request signals,0x00,rw
|
||||
GPDMA_C0SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C1SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C2SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C3SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C4SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C5SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C6SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C7SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C0DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C1DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C2DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C3DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C4DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C5DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C6DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C7DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw
|
||||
GPDMA_C0LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C0LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C1LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C1LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C2LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C2LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C3LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C3LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C4LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C4LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C5LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C5LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C6LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C6LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C7LLI,0,1,LM,AHB master select for loading the next LLI,0,rw
|
||||
GPDMA_C7LLI,2,30,LLI,Linked list item,0x00000000,rw
|
||||
GPDMA_C0CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C0CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C0CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C0CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C0CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C0CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C0CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C0CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C0CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C0CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C0CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C0CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C0CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C1CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C1CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C1CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C1CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C1CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C1CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C1CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C1CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C1CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C1CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C1CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C1CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C1CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C2CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C2CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C2CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C2CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C2CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C2CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C2CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C2CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C2CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C2CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C2CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C2CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C2CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C3CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C3CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C3CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C3CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C3CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C3CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C3CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C3CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C3CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C3CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C3CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C3CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C3CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C4CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C4CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C4CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C4CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C4CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C4CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C4CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C4CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C4CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C4CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C4CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C4CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C4CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C5CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C5CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C5CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C5CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C5CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C5CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C5CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C5CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C5CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C5CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C5CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C5CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C5CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C6CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C6CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C6CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C6CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C6CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C6CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C6CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C6CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C6CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C6CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C6CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C6CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C6CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C7CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw
|
||||
GPDMA_C7CONTROL,12,3,SBSIZE,Source burst size,0x0,rw
|
||||
GPDMA_C7CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw
|
||||
GPDMA_C7CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw
|
||||
GPDMA_C7CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw
|
||||
GPDMA_C7CONTROL,24,1,S,Source AHB master select,0,rw
|
||||
GPDMA_C7CONTROL,25,1,D,Destination AHB master select,0,rw
|
||||
GPDMA_C7CONTROL,26,1,SI,Source increment,0,rw
|
||||
GPDMA_C7CONTROL,27,1,DI,Destination increment,0,rw
|
||||
GPDMA_C7CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw
|
||||
GPDMA_C7CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw
|
||||
GPDMA_C7CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw
|
||||
GPDMA_C7CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw
|
||||
GPDMA_C0CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C0CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C0CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C0CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C0CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C0CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C0CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C0CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C0CONFIG,18,1,H,Halt,,rw
|
||||
GPDMA_C1CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C1CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C1CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C1CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C1CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C1CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C1CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C1CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C1CONFIG,18,1,H,Halt,,rw
|
||||
GPDMA_C2CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C2CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C2CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C2CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C2CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C2CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C2CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C2CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C2CONFIG,18,1,H,Halt,,rw
|
||||
GPDMA_C3CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C3CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C3CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C3CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C3CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C3CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C3CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C3CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C3CONFIG,18,1,H,Halt,,rw
|
||||
GPDMA_C4CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C4CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C4CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C4CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C4CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C4CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C4CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C4CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C4CONFIG,18,1,H,Halt,,rw
|
||||
GPDMA_C5CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C5CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C5CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C5CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C5CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C5CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C5CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C5CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C5CONFIG,18,1,H,Halt,,rw
|
||||
GPDMA_C6CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C6CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C6CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C6CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C6CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C6CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C6CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C6CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C6CONFIG,18,1,H,Halt,,rw
|
||||
GPDMA_C7CONFIG,0,1,E,Channel enable,0,rw
|
||||
GPDMA_C7CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw
|
||||
GPDMA_C7CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw
|
||||
GPDMA_C7CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw
|
||||
GPDMA_C7CONFIG,14,1,IE,Interrupt error mask,,rw
|
||||
GPDMA_C7CONFIG,15,1,ITC,Terminal count interrupt mask,,rw
|
||||
GPDMA_C7CONFIG,16,1,L,Lock,,rw
|
||||
GPDMA_C7CONFIG,17,1,A,Active,,r
|
||||
GPDMA_C7CONFIG,18,1,H,Halt,,rw
|
||||
|
File diff suppressed because it is too large
Load Diff
|
|
@ -1,616 +0,0 @@
|
|||
GPIO_PIN_INTERRUPT_ISEL,0,8,PMODE,Selects the interrupt mode for each pin interrupt,0,rw
|
||||
GPIO_PIN_INTERRUPT_IENR,0,8,ENRL,Enables the rising edge or level interrupt for each pin interrupt,0,rw
|
||||
GPIO_PIN_INTERRUPT_SIENR,0,8,SETENRL,"Ones written to this address set bits in the IENR, thus enabling interrupts",,w
|
||||
GPIO_PIN_INTERRUPT_CIENR,0,8,CENRL,"Ones written to this address clear bits in the IENR, thus disabling the interrupts",,w
|
||||
GPIO_PIN_INTERRUPT_IENF,0,8,ENAF,Enables the falling edge or configures the active level interrupt for each pin interrupt,0,rw
|
||||
GPIO_PIN_INTERRUPT_SIENF,0,8,SETENAF,"Ones written to this address set bits in the IENF, thus enabling interrupts",,w
|
||||
GPIO_PIN_INTERRUPT_CIENF,0,8,CENAF,"Ones written to this address clears bits in the IENF, thus disabling interrupts",,w
|
||||
GPIO_PIN_INTERRUPT_RISE,0,8,RDET,Rising edge detect,0,rw
|
||||
GPIO_PIN_INTERRUPT_FALL,0,8,FDET,Falling edge detect,0,rw
|
||||
GPIO_PIN_INTERRUPT_IST,0,8,PSTAT,Pin interrupt status,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_CTRL,0,1,INT,Group interrupt status,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_CTRL,1,1,COMB,Combine enabled inputs for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_CTRL,2,1,TRIG,Group interrupt trigger,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL0,0,32,POL,Configure pin polarity of port 0 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL1,0,32,POL,Configure pin polarity of port 1 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL2,0,32,POL,Configure pin polarity of port 2 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL3,0,32,POL,Configure pin polarity of port 3 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL4,0,32,POL,Configure pin polarity of port 4 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL5,0,32,POL,Configure pin polarity of port 5 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL6,0,32,POL,Configure pin polarity of port 6 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_POL7,0,32,POL,Configure pin polarity of port 7 pins for group interrupt,1,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA0,0,32,ENA,Enable port 0 pin for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA1,0,32,ENA,Enable port 1 pin for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA2,0,32,ENA,Enable port 2 pin for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA3,0,32,ENA,Enable port 3 pin for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA4,0,32,ENA,Enable port 4 pin for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA5,0,32,ENA,Enable port 5 pin for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA6,0,32,ENA,Enable port 6 pin for group interrupt,0,rw
|
||||
GPIO_GROUP0_INTERRUPT_PORT_ENA7,0,32,ENA,Enable port 7 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_CTRL,0,1,INT,Group interrupt status,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_CTRL,1,1,COMB,Combine enabled inputs for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_CTRL,2,1,TRIG,Group interrupt trigger,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL0,0,32,POL,Configure pin polarity of port 0 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL1,0,32,POL,Configure pin polarity of port 1 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL2,0,32,POL,Configure pin polarity of port 2 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL3,0,32,POL,Configure pin polarity of port 3 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL4,0,32,POL,Configure pin polarity of port 4 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL5,0,32,POL,Configure pin polarity of port 5 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL6,0,32,POL,Configure pin polarity of port 6 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_POL7,0,32,POL,Configure pin polarity of port 7 pins for group interrupt,1,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA0,0,32,ENA,Enable port 0 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA1,0,32,ENA,Enable port 1 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA2,0,32,ENA,Enable port 2 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA3,0,32,ENA,Enable port 3 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA4,0,32,ENA,Enable port 4 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA5,0,32,ENA,Enable port 5 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA6,0,32,ENA,Enable port 6 pin for group interrupt,0,rw
|
||||
GPIO_GROUP1_INTERRUPT_PORT_ENA7,0,32,ENA,Enable port 7 pin for group interrupt,0,rw
|
||||
GPIO_B0,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B1,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B2,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B3,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B4,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B5,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B6,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B7,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B8,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B9,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B10,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B11,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B12,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B13,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B14,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B15,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B16,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B17,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B18,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B19,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B20,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B21,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B22,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B23,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B24,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B25,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B26,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B27,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B28,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B29,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B30,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B31,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B32,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B33,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B34,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B35,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B36,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B37,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B38,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B39,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B40,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B41,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B42,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B43,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B44,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B45,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B46,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B47,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B48,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B49,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B50,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B51,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B52,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B53,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B54,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B55,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B56,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B57,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B58,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B59,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B60,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B61,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B62,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B63,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B64,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B65,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B66,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B67,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B68,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B69,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B70,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B71,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B72,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B73,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B74,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B75,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B76,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B77,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B78,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B79,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B80,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B81,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B82,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B83,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B84,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B85,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B86,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B87,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B88,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B89,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B90,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B91,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B92,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B93,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B94,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B95,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B96,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B97,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B98,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B99,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B100,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B101,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B102,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B103,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B104,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B105,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B106,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B107,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B108,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B109,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B110,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B111,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B112,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B113,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B114,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B115,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B116,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B117,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B118,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B119,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B120,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B121,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B122,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B123,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B124,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B125,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B126,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B127,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B128,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B129,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B130,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B131,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B132,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B133,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B134,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B135,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B136,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B137,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B138,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B139,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B140,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B141,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B142,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B143,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B144,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B145,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B146,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B147,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B148,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B149,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B150,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B151,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B152,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B153,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B154,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B155,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B156,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B157,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B158,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B159,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B160,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B161,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B162,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B163,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B164,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B165,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B166,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B167,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B168,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B169,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B170,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B171,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B172,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B173,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B174,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B175,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B176,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B177,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B178,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B179,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B180,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B181,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B182,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B183,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B184,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B185,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B186,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B187,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B188,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B189,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B190,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B191,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B192,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B193,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B194,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B195,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B196,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B197,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B198,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B199,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B200,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B201,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B202,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B203,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B204,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B205,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B206,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B207,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B208,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B209,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B210,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B211,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B212,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B213,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B214,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B215,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B216,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B217,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B218,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B219,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B220,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B221,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B222,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B223,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B224,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B225,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B226,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B227,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B228,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B229,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B230,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B231,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B232,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B233,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B234,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B235,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B236,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B237,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B238,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B239,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B240,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B241,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B242,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B243,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B244,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B245,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B246,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B247,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B248,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B249,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B250,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B251,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B252,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B253,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B254,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_B255,0,1,PBYTE,GPIO port byte pin register,,rw
|
||||
GPIO_W0,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W1,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W2,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W3,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W4,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W5,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W6,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W7,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W8,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W9,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W10,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W11,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W12,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W13,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W14,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W15,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W16,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W17,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W18,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W19,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W20,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W21,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W22,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W23,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W24,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W25,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W26,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W27,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W28,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W29,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W30,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W31,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W32,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W33,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W34,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W35,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W36,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W37,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W38,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W39,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W40,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W41,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W42,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W43,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W44,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W45,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W46,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W47,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W48,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W49,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W50,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W51,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W52,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W53,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W54,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W55,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W56,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W57,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W58,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W59,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W60,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W61,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W62,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W63,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W64,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W65,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W66,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W67,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W68,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W69,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W70,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W71,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W72,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W73,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W74,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W75,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W76,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W77,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W78,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W79,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W80,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W81,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W82,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W83,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W84,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W85,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W86,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W87,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W88,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W89,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W90,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W91,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W92,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W93,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W94,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W95,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W96,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W97,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W98,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W99,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W100,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W101,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W102,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W103,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W104,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W105,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W106,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W107,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W108,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W109,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W110,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W111,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W112,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W113,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W114,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W115,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W116,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W117,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W118,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W119,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W120,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W121,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W122,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W123,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W124,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W125,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W126,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W127,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W128,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W129,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W130,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W131,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W132,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W133,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W134,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W135,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W136,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W137,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W138,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W139,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W140,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W141,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W142,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W143,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W144,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W145,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W146,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W147,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W148,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W149,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W150,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W151,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W152,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W153,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W154,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W155,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W156,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W157,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W158,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W159,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W160,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W161,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W162,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W163,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W164,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W165,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W166,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W167,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W168,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W169,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W170,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W171,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W172,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W173,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W174,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W175,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W176,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W177,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W178,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W179,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W180,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W181,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W182,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W183,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W184,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W185,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W186,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W187,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W188,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W189,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W190,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W191,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W192,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W193,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W194,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W195,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W196,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W197,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W198,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W199,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W200,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W201,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W202,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W203,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W204,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W205,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W206,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W207,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W208,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W209,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W210,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W211,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W212,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W213,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W214,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W215,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W216,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W217,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W218,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W219,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W220,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W221,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W222,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W223,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W224,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W225,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W226,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W227,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W228,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W229,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W230,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W231,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W232,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W233,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W234,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W235,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W236,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W237,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W238,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W239,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W240,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W241,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W242,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W243,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W244,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W245,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W246,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W247,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W248,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W249,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W250,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W251,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W252,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W253,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W254,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO_W255,0,32,PWORD,GPIO port word pin register,,rw
|
||||
GPIO0_DIR,0,32,DIR,Selects pin direction for GPIO0,0,rw
|
||||
GPIO1_DIR,0,32,DIR,Selects pin direction for GPIO1,0,rw
|
||||
GPIO2_DIR,0,32,DIR,Selects pin direction for GPIO2,0,rw
|
||||
GPIO3_DIR,0,32,DIR,Selects pin direction for GPIO3,0,rw
|
||||
GPIO4_DIR,0,32,DIR,Selects pin direction for GPIO4,0,rw
|
||||
GPIO5_DIR,0,32,DIR,Selects pin direction for GPIO5,0,rw
|
||||
GPIO6_DIR,0,32,DIR,Selects pin direction for GPIO6,0,rw
|
||||
GPIO7_DIR,0,32,DIR,Selects pin direction for GPIO7,0,rw
|
||||
GPIO0_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO1_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO2_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO3_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO4_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO5_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO6_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO7_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw
|
||||
GPIO0_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO1_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO2_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO3_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO4_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO5_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO6_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO7_PIN,0,32,PORT,Reads pin states or loads output bits,,rw
|
||||
GPIO0_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO1_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO2_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO3_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO4_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO5_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO6_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO7_MPIN,0,32,MPORT,Masked port register,,rw
|
||||
GPIO0_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO1_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO2_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO3_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO4_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO5_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO6_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO7_SET,0,32,SET,Read or set output bits,0,rw
|
||||
GPIO0_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO1_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO2_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO3_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO4_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO5_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO6_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO7_CLR,0,32,CLR,Clear output bits,,w
|
||||
GPIO0_NOT,0,32,NOT,Toggle output bits,,w
|
||||
GPIO1_NOT,0,32,NOT,Toggle output bits,,w
|
||||
GPIO2_NOT,0,32,NOT,Toggle output bits,,w
|
||||
GPIO3_NOT,0,32,NOT,Toggle output bits,,w
|
||||
GPIO4_NOT,0,32,NOT,Toggle output bits,,w
|
||||
GPIO5_NOT,0,32,NOT,Toggle output bits,,w
|
||||
GPIO6_NOT,0,32,NOT,Toggle output bits,,w
|
||||
GPIO7_NOT,0,32,NOT,Toggle output bits,,w
|
||||
|
File diff suppressed because it is too large
Load Diff
|
|
@ -1,58 +0,0 @@
|
|||
I2C0_CONSET,2,1,AA,Assert acknowledge flag,0,rw
|
||||
I2C0_CONSET,3,1,SI,I2C interrupt flag,0,rw
|
||||
I2C0_CONSET,4,1,STO,STOP flag,0,rw
|
||||
I2C0_CONSET,5,1,STA,START flag,0,rw
|
||||
I2C0_CONSET,6,1,I2EN,I2C interface enable,0,rw
|
||||
I2C1_CONSET,2,1,AA,Assert acknowledge flag,0,rw
|
||||
I2C1_CONSET,3,1,SI,I2C interrupt flag,0,rw
|
||||
I2C1_CONSET,4,1,STO,STOP flag,0,rw
|
||||
I2C1_CONSET,5,1,STA,START flag,0,rw
|
||||
I2C1_CONSET,6,1,I2EN,I2C interface enable,0,rw
|
||||
I2C0_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r
|
||||
I2C1_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r
|
||||
I2C0_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw
|
||||
I2C1_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw
|
||||
I2C0_ADR0,0,1,GC,General Call enable bit,0,rw
|
||||
I2C0_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C1_ADR0,0,1,GC,General Call enable bit,0,rw
|
||||
I2C1_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C0_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw
|
||||
I2C1_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw
|
||||
I2C0_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw
|
||||
I2C1_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw
|
||||
I2C0_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w
|
||||
I2C0_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w
|
||||
I2C0_CONCLR,5,1,STAC,START flag Clear bit,0,w
|
||||
I2C0_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w
|
||||
I2C1_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w
|
||||
I2C1_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w
|
||||
I2C1_CONCLR,5,1,STAC,START flag Clear bit,0,w
|
||||
I2C1_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w
|
||||
I2C0_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw
|
||||
I2C0_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw
|
||||
I2C0_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw
|
||||
I2C1_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw
|
||||
I2C1_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw
|
||||
I2C1_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw
|
||||
I2C0_ADR1,0,1,GC,General Call enable bit,0,rw
|
||||
I2C0_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C1_ADR1,0,1,GC,General Call enable bit,0,rw
|
||||
I2C1_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C0_ADR2,0,1,GC,General Call enable bit,0,rw
|
||||
I2C0_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C1_ADR2,0,1,GC,General Call enable bit,0,rw
|
||||
I2C1_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C0_ADR3,0,1,GC,General Call enable bit,0,rw
|
||||
I2C0_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C1_ADR3,0,1,GC,General Call enable bit,0,rw
|
||||
I2C1_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw
|
||||
I2C0_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r
|
||||
I2C1_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r
|
||||
I2C0_MASK0,1,7,MASK,Mask bits,0,rw
|
||||
I2C1_MASK0,1,7,MASK,Mask bits,0,rw
|
||||
I2C0_MASK1,1,7,MASK,Mask bits,0,rw
|
||||
I2C1_MASK1,1,7,MASK,Mask bits,0,rw
|
||||
I2C0_MASK2,1,7,MASK,Mask bits,0,rw
|
||||
I2C1_MASK2,1,7,MASK,Mask bits,0,rw
|
||||
I2C0_MASK3,1,7,MASK,Mask bits,0,rw
|
||||
I2C1_MASK3,1,7,MASK,Mask bits,0,rw
|
||||
|
|
|
@ -0,0 +1,415 @@
|
|||
!!omap
|
||||
- I2C0_CONSET:
|
||||
fields: !!omap
|
||||
- AA:
|
||||
access: rw
|
||||
description: Assert acknowledge flag
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SI:
|
||||
access: rw
|
||||
description: I2C interrupt flag
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STO:
|
||||
access: rw
|
||||
description: STOP flag
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STA:
|
||||
access: rw
|
||||
description: START flag
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2EN:
|
||||
access: rw
|
||||
description: I2C interface enable
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2C1_CONSET:
|
||||
fields: !!omap
|
||||
- AA:
|
||||
access: rw
|
||||
description: Assert acknowledge flag
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SI:
|
||||
access: rw
|
||||
description: I2C interrupt flag
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STO:
|
||||
access: rw
|
||||
description: STOP flag
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STA:
|
||||
access: rw
|
||||
description: START flag
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2EN:
|
||||
access: rw
|
||||
description: I2C interface enable
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2C0_STAT:
|
||||
fields: !!omap
|
||||
- STATUS:
|
||||
access: r
|
||||
description: These bits give the actual status information about the I2C interface
|
||||
lsb: 3
|
||||
reset_value: '0x1f'
|
||||
width: 5
|
||||
- I2C1_STAT:
|
||||
fields: !!omap
|
||||
- STATUS:
|
||||
access: r
|
||||
description: These bits give the actual status information about the I2C interface
|
||||
lsb: 3
|
||||
reset_value: '0x1f'
|
||||
width: 5
|
||||
- I2C0_DAT:
|
||||
fields: !!omap
|
||||
- DATA:
|
||||
access: rw
|
||||
description: This register holds data values that have been received or are
|
||||
to be transmitted
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2C1_DAT:
|
||||
fields: !!omap
|
||||
- DATA:
|
||||
access: rw
|
||||
description: This register holds data values that have been received or are
|
||||
to be transmitted
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2C0_ADR0:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_ADR0:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C0_SCLH:
|
||||
fields: !!omap
|
||||
- SCLH:
|
||||
access: rw
|
||||
description: Count for SCL HIGH time period selection
|
||||
lsb: 0
|
||||
reset_value: '0x0004'
|
||||
width: 16
|
||||
- I2C1_SCLH:
|
||||
fields: !!omap
|
||||
- SCLH:
|
||||
access: rw
|
||||
description: Count for SCL HIGH time period selection
|
||||
lsb: 0
|
||||
reset_value: '0x0004'
|
||||
width: 16
|
||||
- I2C0_SCLL:
|
||||
fields: !!omap
|
||||
- SCLL:
|
||||
access: rw
|
||||
description: Count for SCL LOW time period selection
|
||||
lsb: 0
|
||||
reset_value: '0x0004'
|
||||
width: 16
|
||||
- I2C1_SCLL:
|
||||
fields: !!omap
|
||||
- SCLL:
|
||||
access: rw
|
||||
description: Count for SCL LOW time period selection
|
||||
lsb: 0
|
||||
reset_value: '0x0004'
|
||||
width: 16
|
||||
- I2C0_CONCLR:
|
||||
fields: !!omap
|
||||
- AAC:
|
||||
access: w
|
||||
description: Assert acknowledge Clear bit
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SIC:
|
||||
access: w
|
||||
description: I2C interrupt Clear bit
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STAC:
|
||||
access: w
|
||||
description: START flag Clear bit
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2ENC:
|
||||
access: w
|
||||
description: I2C interface Disable bit
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2C1_CONCLR:
|
||||
fields: !!omap
|
||||
- AAC:
|
||||
access: w
|
||||
description: Assert acknowledge Clear bit
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SIC:
|
||||
access: w
|
||||
description: I2C interrupt Clear bit
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STAC:
|
||||
access: w
|
||||
description: START flag Clear bit
|
||||
lsb: 5
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2ENC:
|
||||
access: w
|
||||
description: I2C interface Disable bit
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2C0_MMCTRL:
|
||||
fields: !!omap
|
||||
- MM_ENA:
|
||||
access: rw
|
||||
description: Monitor mode enable
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ENA_SCL:
|
||||
access: rw
|
||||
description: SCL output enable
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- MATCH_ALL:
|
||||
access: rw
|
||||
description: Select interrupt register match
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2C1_MMCTRL:
|
||||
fields: !!omap
|
||||
- MM_ENA:
|
||||
access: rw
|
||||
description: Monitor mode enable
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ENA_SCL:
|
||||
access: rw
|
||||
description: SCL output enable
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- MATCH_ALL:
|
||||
access: rw
|
||||
description: Select interrupt register match
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2C0_ADR1:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_ADR1:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C0_ADR2:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_ADR2:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C0_ADR3:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_ADR3:
|
||||
fields: !!omap
|
||||
- GC:
|
||||
access: rw
|
||||
description: General Call enable bit
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- ADDRESS:
|
||||
access: rw
|
||||
description: The I2C device address for slave mode
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C0_DATA_BUFFER:
|
||||
fields: !!omap
|
||||
- DATA:
|
||||
access: r
|
||||
description: This register holds contents of the 8 MSBs of the DAT shift register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2C1_DATA_BUFFER:
|
||||
fields: !!omap
|
||||
- DATA:
|
||||
access: r
|
||||
description: This register holds contents of the 8 MSBs of the DAT shift register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2C0_MASK0:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_MASK0:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C0_MASK1:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_MASK1:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C0_MASK2:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_MASK2:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C0_MASK3:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
- I2C1_MASK3:
|
||||
fields: !!omap
|
||||
- MASK:
|
||||
access: rw
|
||||
description: Mask bits
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 7
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
I2S0_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
|
||||
I2S0_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
|
||||
I2S0_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
|
||||
I2S0_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
|
||||
I2S0_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
|
||||
I2S0_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
|
||||
I2S0_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
|
||||
I2S1_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
|
||||
I2S1_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
|
||||
I2S1_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
|
||||
I2S1_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
|
||||
I2S1_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
|
||||
I2S1_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
|
||||
I2S1_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
|
||||
I2S0_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
|
||||
I2S0_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
|
||||
I2S0_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
|
||||
I2S0_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
|
||||
I2S0_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
|
||||
I2S0_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
|
||||
I2S0_DAI,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
|
||||
I2S1_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
|
||||
I2S1_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
|
||||
I2S1_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
|
||||
I2S1_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
|
||||
I2S1_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
|
||||
I2S1_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
|
||||
I2S1_DAI,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
|
||||
I2S0_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w
|
||||
I2S1_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w
|
||||
I2S0_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r
|
||||
I2S1_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r
|
||||
I2S0_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r
|
||||
I2S0_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r
|
||||
I2S0_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r
|
||||
I2S0_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r
|
||||
I2S0_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r
|
||||
I2S1_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r
|
||||
I2S1_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r
|
||||
I2S1_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r
|
||||
I2S1_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r
|
||||
I2S1_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r
|
||||
I2S0_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw
|
||||
I2S0_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw
|
||||
I2S0_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw
|
||||
I2S0_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw
|
||||
I2S1_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw
|
||||
I2S1_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw
|
||||
I2S1_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw
|
||||
I2S1_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw
|
||||
I2S0_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw
|
||||
I2S0_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw
|
||||
I2S0_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw
|
||||
I2S0_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw
|
||||
I2S1_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw
|
||||
I2S1_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw
|
||||
I2S1_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw
|
||||
I2S1_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw
|
||||
I2S0_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw
|
||||
I2S0_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw
|
||||
I2S0_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
|
||||
I2S0_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
|
||||
I2S1_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw
|
||||
I2S1_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw
|
||||
I2S1_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
|
||||
I2S1_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
|
||||
I2S0_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw
|
||||
I2S0_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw
|
||||
I2S1_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw
|
||||
I2S1_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw
|
||||
I2S0_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw
|
||||
I2S0_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw
|
||||
I2S1_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw
|
||||
I2S1_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw
|
||||
I2S0_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw
|
||||
I2S1_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw
|
||||
I2S0_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw
|
||||
I2S1_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw
|
||||
I2S0_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw
|
||||
I2S0_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw
|
||||
I2S0_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw
|
||||
I2S1_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw
|
||||
I2S1_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw
|
||||
I2S1_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw
|
||||
I2S0_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw
|
||||
I2S0_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw
|
||||
I2S0_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw
|
||||
I2S1_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw
|
||||
I2S1_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw
|
||||
I2S1_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw
|
||||
|
|
|
@ -0,0 +1,619 @@
|
|||
!!omap
|
||||
- I2S0_DAO:
|
||||
fields: !!omap
|
||||
- WORDWIDTH:
|
||||
access: rw
|
||||
description: Selects the number of bytes in data
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 2
|
||||
- MONO:
|
||||
access: rw
|
||||
description: When 1, data is of monaural format. When 0, the data is in stereo
|
||||
format
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STOP:
|
||||
access: rw
|
||||
description: When 1, disables accesses on FIFOs, places the transmit channel
|
||||
in mute mode
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET:
|
||||
access: rw
|
||||
description: When 1, asynchronously resets the transmit channel and FIFO
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WS_SEL:
|
||||
access: rw
|
||||
description: When 0, the interface is in master mode. When 1, the interface
|
||||
is in slave mode
|
||||
lsb: 5
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WS_HALFPERIOD:
|
||||
access: rw
|
||||
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
|
||||
= 31.
|
||||
lsb: 6
|
||||
reset_value: '0x1f'
|
||||
width: 9
|
||||
- MUTE:
|
||||
access: rw
|
||||
description: When 1, the transmit channel sends only zeroes
|
||||
lsb: 15
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- I2S1_DAO:
|
||||
fields: !!omap
|
||||
- WORDWIDTH:
|
||||
access: rw
|
||||
description: Selects the number of bytes in data
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 2
|
||||
- MONO:
|
||||
access: rw
|
||||
description: When 1, data is of monaural format. When 0, the data is in stereo
|
||||
format
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STOP:
|
||||
access: rw
|
||||
description: When 1, disables accesses on FIFOs, places the transmit channel
|
||||
in mute mode
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET:
|
||||
access: rw
|
||||
description: When 1, asynchronously resets the transmit channel and FIFO
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WS_SEL:
|
||||
access: rw
|
||||
description: When 0, the interface is in master mode. When 1, the interface
|
||||
is in slave mode
|
||||
lsb: 5
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WS_HALFPERIOD:
|
||||
access: rw
|
||||
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
|
||||
= 31.
|
||||
lsb: 6
|
||||
reset_value: '0x1f'
|
||||
width: 9
|
||||
- MUTE:
|
||||
access: rw
|
||||
description: When 1, the transmit channel sends only zeroes
|
||||
lsb: 15
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- I2S0_DAI:
|
||||
fields: !!omap
|
||||
- WORDWIDTH:
|
||||
access: rw
|
||||
description: Selects the number of bytes in data
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 2
|
||||
- MONO:
|
||||
access: rw
|
||||
description: When 1, data is of monaural format. When 0, the data is in stereo
|
||||
format
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STOP:
|
||||
access: rw
|
||||
description: When 1, disables accesses on FIFOs, places the transmit channel
|
||||
in mute mode
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET:
|
||||
access: rw
|
||||
description: When 1, asynchronously resets the transmit channel and FIFO
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WS_SEL:
|
||||
access: rw
|
||||
description: When 0, the interface is in master mode. When 1, the interface
|
||||
is in slave mode
|
||||
lsb: 5
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WS_HALFPERIOD:
|
||||
access: rw
|
||||
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
|
||||
= 31.
|
||||
lsb: 6
|
||||
reset_value: '0x1f'
|
||||
width: 9
|
||||
- MUTE:
|
||||
access: rw
|
||||
description: When 1, the transmit channel sends only zeroes
|
||||
lsb: 15
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- I2S1_DAI:
|
||||
fields: !!omap
|
||||
- WORDWIDTH:
|
||||
access: rw
|
||||
description: Selects the number of bytes in data
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 2
|
||||
- MONO:
|
||||
access: rw
|
||||
description: When 1, data is of monaural format. When 0, the data is in stereo
|
||||
format
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- STOP:
|
||||
access: rw
|
||||
description: When 1, disables accesses on FIFOs, places the transmit channel
|
||||
in mute mode
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RESET:
|
||||
access: rw
|
||||
description: When 1, asynchronously resets the transmit channel and FIFO
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- WS_SEL:
|
||||
access: rw
|
||||
description: When 0, the interface is in master mode. When 1, the interface
|
||||
is in slave mode
|
||||
lsb: 5
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- WS_HALFPERIOD:
|
||||
access: rw
|
||||
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
|
||||
= 31.
|
||||
lsb: 6
|
||||
reset_value: '0x1f'
|
||||
width: 9
|
||||
- MUTE:
|
||||
access: rw
|
||||
description: When 1, the transmit channel sends only zeroes
|
||||
lsb: 15
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- I2S0_TXFIFO:
|
||||
fields: !!omap
|
||||
- I2STXFIFO:
|
||||
access: w
|
||||
description: 8 x 32-bit transmit FIFO
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 32
|
||||
- I2S1_TXFIFO:
|
||||
fields: !!omap
|
||||
- I2STXFIFO:
|
||||
access: w
|
||||
description: 8 x 32-bit transmit FIFO
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 32
|
||||
- I2S0_RXFIFO:
|
||||
fields: !!omap
|
||||
- I2SRXFIFO:
|
||||
access: r
|
||||
description: 8 x 32-bit receive FIFO
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 32
|
||||
- I2S1_RXFIFO:
|
||||
fields: !!omap
|
||||
- I2SRXFIFO:
|
||||
access: r
|
||||
description: 8 x 32-bit receive FIFO
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 32
|
||||
- I2S0_STATE:
|
||||
fields: !!omap
|
||||
- IRQ:
|
||||
access: r
|
||||
description: This bit reflects the presence of Receive Interrupt or Transmit
|
||||
Interrupt
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- DMAREQ1:
|
||||
access: r
|
||||
description: This bit reflects the presence of Receive or Transmit DMA Request
|
||||
1
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- DMAREQ2:
|
||||
access: r
|
||||
description: This bit reflects the presence of Receive or Transmit DMA Request
|
||||
2
|
||||
lsb: 2
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RX_LEVEL:
|
||||
access: r
|
||||
description: Reflects the current level of the Receive FIFO
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_LEVEL:
|
||||
access: r
|
||||
description: Reflects the current level of the Transmit FIFO
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S1_STATE:
|
||||
fields: !!omap
|
||||
- IRQ:
|
||||
access: r
|
||||
description: This bit reflects the presence of Receive Interrupt or Transmit
|
||||
Interrupt
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- DMAREQ1:
|
||||
access: r
|
||||
description: This bit reflects the presence of Receive or Transmit DMA Request
|
||||
1
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- DMAREQ2:
|
||||
access: r
|
||||
description: This bit reflects the presence of Receive or Transmit DMA Request
|
||||
2
|
||||
lsb: 2
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RX_LEVEL:
|
||||
access: r
|
||||
description: Reflects the current level of the Receive FIFO
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_LEVEL:
|
||||
access: r
|
||||
description: Reflects the current level of the Transmit FIFO
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S0_DMA1:
|
||||
fields: !!omap
|
||||
- RX_DMA1_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA1 for I2S receive
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TX_DMA1_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA1 for I2S transmit
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RX_DEPTH_DMA1:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a receive DMA request on DMA1
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_DEPTH_DMA1:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a transmit DMA request on DMA1
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S1_DMA1:
|
||||
fields: !!omap
|
||||
- RX_DMA1_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA1 for I2S receive
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TX_DMA1_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA1 for I2S transmit
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RX_DEPTH_DMA1:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a receive DMA request on DMA1
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_DEPTH_DMA1:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a transmit DMA request on DMA1
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S0_DMA2:
|
||||
fields: !!omap
|
||||
- RX_DMA2_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA2 for I2S receive
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TX_DMA2_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA2 for I2S transmit
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RX_DEPTH_DMA2:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a receive DMA request on DMA2
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_DEPTH_DMA2:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a transmit DMA request on DMA2
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S1_DMA2:
|
||||
fields: !!omap
|
||||
- RX_DMA2_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA2 for I2S receive
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TX_DMA2_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables DMA2 for I2S transmit
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RX_DEPTH_DMA2:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a receive DMA request on DMA2
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_DEPTH_DMA2:
|
||||
access: rw
|
||||
description: Set the FIFO level that triggers a transmit DMA request on DMA2
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S0_IRQ:
|
||||
fields: !!omap
|
||||
- RX_IRQ_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables I2S receive interrupt
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TX_IRQ_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables I2S transmit interrupt
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RX_DEPTH_IRQ:
|
||||
access: rw
|
||||
description: Set the FIFO level on which to create an irq request.
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_DEPTH_IRQ:
|
||||
access: rw
|
||||
description: Set the FIFO level on which to create an irq request.
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S1_IRQ:
|
||||
fields: !!omap
|
||||
- RX_IRQ_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables I2S receive interrupt
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TX_IRQ_ENABLE:
|
||||
access: rw
|
||||
description: When 1, enables I2S transmit interrupt
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RX_DEPTH_IRQ:
|
||||
access: rw
|
||||
description: Set the FIFO level on which to create an irq request.
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- TX_DEPTH_IRQ:
|
||||
access: rw
|
||||
description: Set the FIFO level on which to create an irq request.
|
||||
lsb: 16
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- I2S0_TXRATE:
|
||||
fields: !!omap
|
||||
- Y_DIVIDER:
|
||||
access: rw
|
||||
description: I2S transmit MCLK rate denominator
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- X_DIVIDER:
|
||||
access: rw
|
||||
description: I2S transmit MCLK rate numerator
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2S1_TXRATE:
|
||||
fields: !!omap
|
||||
- Y_DIVIDER:
|
||||
access: rw
|
||||
description: I2S transmit MCLK rate denominator
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- X_DIVIDER:
|
||||
access: rw
|
||||
description: I2S transmit MCLK rate numerator
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2S0_RXRATE:
|
||||
fields: !!omap
|
||||
- Y_DIVIDER:
|
||||
access: rw
|
||||
description: I2S receive MCLK rate denominator
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- X_DIVIDER:
|
||||
access: rw
|
||||
description: I2S receive MCLK rate numerator
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2S1_RXRATE:
|
||||
fields: !!omap
|
||||
- Y_DIVIDER:
|
||||
access: rw
|
||||
description: I2S receive MCLK rate denominator
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- X_DIVIDER:
|
||||
access: rw
|
||||
description: I2S receive MCLK rate numerator
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- I2S0_TXBITRATE:
|
||||
fields: !!omap
|
||||
- TX_BITRATE:
|
||||
access: rw
|
||||
description: I2S transmit bit rate
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 6
|
||||
- I2S1_TXBITRATE:
|
||||
fields: !!omap
|
||||
- TX_BITRATE:
|
||||
access: rw
|
||||
description: I2S transmit bit rate
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 6
|
||||
- I2S0_RXBITRATE:
|
||||
fields: !!omap
|
||||
- RX_BITRATE:
|
||||
access: rw
|
||||
description: I2S receive bit rate
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 6
|
||||
- I2S1_RXBITRATE:
|
||||
fields: !!omap
|
||||
- RX_BITRATE:
|
||||
access: rw
|
||||
description: I2S receive bit rate
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 6
|
||||
- I2S0_TXMODE:
|
||||
fields: !!omap
|
||||
- TXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the transmit bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- TX4PIN:
|
||||
access: rw
|
||||
description: Transmit 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXMCENA:
|
||||
access: rw
|
||||
description: Enable for the TX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S1_TXMODE:
|
||||
fields: !!omap
|
||||
- TXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the transmit bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- TX4PIN:
|
||||
access: rw
|
||||
description: Transmit 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXMCENA:
|
||||
access: rw
|
||||
description: Enable for the TX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S0_RXMODE:
|
||||
fields: !!omap
|
||||
- RXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the receive bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- RX4PIN:
|
||||
access: rw
|
||||
description: Receive 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXMCENA:
|
||||
access: rw
|
||||
description: Enable for the RX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S1_RXMODE:
|
||||
fields: !!omap
|
||||
- RXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the receive bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- RX4PIN:
|
||||
access: rw
|
||||
description: Receive 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXMCENA:
|
||||
access: rw
|
||||
description: Enable for the RX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
RESET_CTRL0,0,1,CORE_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,1,1,PERIPH_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,2,1,MASTER_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,4,1,WWDT_RST,Writing a one to this bit has no effect,0,
|
||||
RESET_CTRL0,5,1,CREG_RST,Writing a one to this bit has no effect,0,
|
||||
RESET_CTRL0,8,1,BUS_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,9,1,SCU_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,13,1,M4_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,16,1,LCD_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,17,1,USB0_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,18,1,USB1_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,19,1,DMA_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,20,1,SDIO_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,21,1,EMC_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,22,1,ETHERNET_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,25,1,FLASHA_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,27,1,EEPROM_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,28,1,GPIO_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL0,29,1,FLASHB_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,0,1,TIMER0_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,1,1,TIMER1_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,2,1,TIMER2_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,3,1,TIMER3_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,4,1,RTIMER_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,5,1,SCT_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,6,1,MOTOCONPWM_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,7,1,QEI_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,8,1,ADC0_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,9,1,ADC1_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,10,1,DAC_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,12,1,UART0_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,13,1,UART1_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,14,1,UART2_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,15,1,UART3_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,16,1,I2C0_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,17,1,I2C1_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,18,1,SSP0_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,19,1,SSP1_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,20,1,I2S_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,21,1,SPIFI_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,22,1,CAN1_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,23,1,CAN0_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,24,1,M0APP_RST,Writing a one activates the reset,1,w
|
||||
RESET_CTRL1,25,1,SGPIO_RST,Writing a one activates the reset,0,w
|
||||
RESET_CTRL1,26,1,SPI_RST,Writing a one activates the reset,0,w
|
||||
RESET_STATUS0,0,2,CORE_RST,Status of the CORE_RST reset generator output,0x0,rw
|
||||
RESET_STATUS0,2,2,PERIPH_RST,Status of the PERIPH_RST reset generator output,0x0,rw
|
||||
RESET_STATUS0,4,2,MASTER_RST,Status of the MASTER_RST reset generator output,0x1,rw
|
||||
RESET_STATUS0,8,2,WWDT_RST,Status of the WWDT_RST reset generator output,0x0,rw
|
||||
RESET_STATUS0,10,2,CREG_RST,Status of the CREG_RST reset generator output,0x0,rw
|
||||
RESET_STATUS0,16,2,BUS_RST,Status of the BUS_RST reset generator output,0x1,rw
|
||||
RESET_STATUS0,18,2,SCU_RST,Status of the SCU_RST reset generator output,0x1,rw
|
||||
RESET_STATUS0,26,2,M4_RST,Status of the M4_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,0,2,LCD_RST,Status of the LCD_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,2,2,USB0_RST,Status of the USB0_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,4,2,USB1_RST,Status of the USB1_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,6,2,DMA_RST,Status of the DMA_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,8,2,SDIO_RST,Status of the SDIO_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,10,2,EMC_RST,Status of the EMC_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,12,2,ETHERNET_RST,Status of the ETHERNET_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,18,2,FLASHA_RST,Status of the FLASHA_RST reset generator output,0x1,
|
||||
RESET_STATUS1,22,2,EEPROM_RST,Status of the EEPROM_RST reset generator output,0x1,
|
||||
RESET_STATUS1,24,2,GPIO_RST,Status of the GPIO_RST reset generator output,0x1,rw
|
||||
RESET_STATUS1,26,2,FLASHB_RST,Status of the FLASHB_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,0,2,TIMER0_RST,Status of the TIMER0_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,2,2,TIMER1_RST,Status of the TIMER1_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,4,2,TIMER2_RST,Status of the TIMER2_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,6,2,TIMER3_RST,Status of the TIMER3_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,8,2,RITIMER_RST,Status of the RITIMER_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,10,2,SCT_RST,Status of the SCT_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,12,2,MOTOCONPWM_RST,Status of the MOTOCONPWM_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,14,2,QEI_RST,Status of the QEI_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,16,2,ADC0_RST,Status of the ADC0_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,18,2,ADC1_RST,Status of the ADC1_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,20,2,DAC_RST,Status of the DAC_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,24,2,UART0_RST,Status of the UART0_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,26,2,UART1_RST,Status of the UART1_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,28,2,UART2_RST,Status of the UART2_RST reset generator output,0x1,rw
|
||||
RESET_STATUS2,30,2,UART3_RST,Status of the UART3_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,0,2,I2C0_RST,Status of the I2C0_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,2,2,I2C1_RST,Status of the I2C1_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,4,2,SSP0_RST,Status of the SSP0_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,6,2,SSP1_RST,Status of the SSP1_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,8,2,I2S_RST,Status of the I2S_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,10,2,SPIFI_RST,Status of the SPIFI_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,12,2,CAN1_RST,Status of the CAN1_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,14,2,CAN0_RST,Status of the CAN0_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,16,2,M0APP_RST,Status of the M0APP_RST reset generator output,0x3,rw
|
||||
RESET_STATUS3,18,2,SGPIO_RST,Status of the SGPIO_RST reset generator output,0x1,rw
|
||||
RESET_STATUS3,20,2,SPI_RST,Status of the SPI_RST reset generator output,0x1,rw
|
||||
RESET_ACTIVE_STATUS0,0,1,CORE_RST,Current status of the CORE_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,1,1,PERIPH_RST,Current status of the PERIPH_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,2,1,MASTER_RST,Current status of the MASTER_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,4,1,WWDT_RST,Current status of the WWDT_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,5,1,CREG_RST,Current status of the CREG_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,8,1,BUS_RST,Current status of the BUS_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,9,1,SCU_RST,Current status of the SCU_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,13,1,M4_RST,Current status of the M4_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,16,1,LCD_RST,Current status of the LCD_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,17,1,USB0_RST,Current status of the USB0_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,18,1,USB1_RST,Current status of the USB1_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,19,1,DMA_RST,Current status of the DMA_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,20,1,SDIO_RST,Current status of the SDIO_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,21,1,EMC_RST,Current status of the EMC_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,22,1,ETHERNET_RST,Current status of the ETHERNET_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,25,1,FLASHA_RST,Current status of the FLASHA_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,27,1,EEPROM_RST,Current status of the EEPROM_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,28,1,GPIO_RST,Current status of the GPIO_RST,0,r
|
||||
RESET_ACTIVE_STATUS0,29,1,FLASHB_RST,Current status of the FLASHB_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,0,1,TIMER0_RST,Current status of the TIMER0_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,1,1,TIMER1_RST,Current status of the TIMER1_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,2,1,TIMER2_RST,Current status of the TIMER2_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,3,1,TIMER3_RST,Current status of the TIMER3_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,4,1,RITIMER_RST,Current status of the RITIMER_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,5,1,SCT_RST,Current status of the SCT_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,6,1,MOTOCONPWM_RST,Current status of the MOTOCONPWM_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,7,1,QEI_RST,Current status of the QEI_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,8,1,ADC0_RST,Current status of the ADC0_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,9,1,ADC1_RST,Current status of the ADC1_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,10,1,DAC_RST,Current status of the DAC_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,12,1,UART0_RST,Current status of the UART0_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,13,1,UART1_RST,Current status of the UART1_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,14,1,UART2_RST,Current status of the UART2_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,15,1,UART3_RST,Current status of the UART3_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,16,1,I2C0_RST,Current status of the I2C0_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,17,1,I2C1_RST,Current status of the I2C1_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,18,1,SSP0_RST,Current status of the SSP0_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,19,1,SSP1_RST,Current status of the SSP1_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,20,1,I2S_RST,Current status of the I2S_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,21,1,SPIFI_RST,Current status of the SPIFI_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,22,1,CAN1_RST,Current status of the CAN1_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,23,1,CAN0_RST,Current status of the CAN0_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,24,1,M0APP_RST,Current status of the M0APP_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,25,1,SGPIO_RST,Current status of the SGPIO_RST,0,r
|
||||
RESET_ACTIVE_STATUS1,26,1,SPI_RST,Current status of the SPI_RST,0,r
|
||||
RESET_EXT_STAT0,0,1,EXT_RESET,Reset activated by external reset from reset pin,0,rw
|
||||
RESET_EXT_STAT0,4,1,BOD_RESET,Reset activated by BOD reset,0,rw
|
||||
RESET_EXT_STAT0,5,1,WWDT_RESET,Reset activated by WWDT time-out,0,rw
|
||||
RESET_EXT_STAT1,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
|
||||
RESET_EXT_STAT2,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT4,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
|
||||
RESET_EXT_STAT5,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
|
||||
RESET_EXT_STAT8,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT9,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT13,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT16,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT17,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT18,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT19,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT20,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT21,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT22,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
|
||||
RESET_EXT_STAT25,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT27,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT28,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT29,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT32,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT33,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT34,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT35,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT36,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT37,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT38,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT39,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT40,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT41,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT42,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT44,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT45,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT46,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT47,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT48,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT49,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT50,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT51,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT52,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT53,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT54,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT55,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT56,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,,rw
|
||||
RESET_EXT_STAT57,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
RESET_EXT_STAT58,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
|
||||
|
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +0,0 @@
|
|||
RITIMER_COMPVAL,0,32,RICOMP,Compare register,0xFFFFFFFF,rw
|
||||
RITIMER_MASK,0,32,RIMASK,Mask register,0,rw
|
||||
RITIMER_CTRL,0,1,RITINT,Interrupt flag,0,rw
|
||||
RITIMER_CTRL,1,1,RITENCLR,Timer enable clear,0,rw
|
||||
RITIMER_CTRL,2,1,RITENBR,Timer enable for debug,1,rw
|
||||
RITIMER_CTRL,3,1,RITEN,Timer enable,1,rw
|
||||
RITIMER_COUNTER,0,32,RICOUNTER,32-bit up counter,0,rw
|
||||
|
|
|
@ -0,0 +1,51 @@
|
|||
!!omap
|
||||
- RITIMER_COMPVAL:
|
||||
fields: !!omap
|
||||
- RICOMP:
|
||||
access: rw
|
||||
description: Compare register
|
||||
lsb: 0
|
||||
reset_value: '0xFFFFFFFF'
|
||||
width: 32
|
||||
- RITIMER_MASK:
|
||||
fields: !!omap
|
||||
- RIMASK:
|
||||
access: rw
|
||||
description: Mask register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 32
|
||||
- RITIMER_CTRL:
|
||||
fields: !!omap
|
||||
- RITINT:
|
||||
access: rw
|
||||
description: Interrupt flag
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RITENCLR:
|
||||
access: rw
|
||||
description: Timer enable clear
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RITENBR:
|
||||
access: rw
|
||||
description: Timer enable for debug
|
||||
lsb: 2
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RITEN:
|
||||
access: rw
|
||||
description: Timer enable
|
||||
lsb: 3
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RITIMER_COUNTER:
|
||||
fields: !!omap
|
||||
- RICOUNTER:
|
||||
access: rw
|
||||
description: 32-bit up counter
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 32
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,304 +0,0 @@
|
|||
SGPIO_OUT_MUX_CFG0,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG0,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG1,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG1,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG2,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG2,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG3,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG3,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG4,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG4,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG5,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG5,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG6,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG6,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG7,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG7,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG8,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG8,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG9,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG9,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG10,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG10,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG11,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG11,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG12,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG12,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG13,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG13,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG14,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG14,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_OUT_MUX_CFG15,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
|
||||
SGPIO_OUT_MUX_CFG15,4,3,P_OE_CFG,Output enable source,0,rw
|
||||
SGPIO_MUX_CFG0,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG0,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG0,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG0,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG0,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG0,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG0,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG0,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG1,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG1,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG1,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG1,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG1,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG1,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG1,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG1,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG2,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG2,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG2,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG2,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG2,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG2,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG2,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG2,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG3,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG3,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG3,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG3,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG3,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG3,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG3,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG3,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG4,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG4,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG4,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG4,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG4,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG4,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG4,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG4,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG5,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG5,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG5,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG5,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG5,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG5,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG5,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG5,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG6,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG6,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG6,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG6,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG6,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG6,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG6,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG6,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG7,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG7,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG7,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG7,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG7,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG7,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG7,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG7,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG8,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG8,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG8,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG8,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG8,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG8,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG8,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG8,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG9,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG9,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG9,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG9,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG9,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG9,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG9,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG9,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG10,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG10,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG10,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG10,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG10,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG10,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG10,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG10,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG11,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG11,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG11,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG11,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG11,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG11,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG11,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG11,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG12,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG12,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG12,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG12,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG12,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG12,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG12,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG12,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG13,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG13,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG13,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG13,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG13,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG13,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG13,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG13,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG14,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG14,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG14,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG14,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG14,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG14,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG14,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG14,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_MUX_CFG15,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
|
||||
SGPIO_MUX_CFG15,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
|
||||
SGPIO_MUX_CFG15,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
|
||||
SGPIO_MUX_CFG15,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
|
||||
SGPIO_MUX_CFG15,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
|
||||
SGPIO_MUX_CFG15,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
|
||||
SGPIO_MUX_CFG15,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
|
||||
SGPIO_MUX_CFG15,12,2,CONCAT_ORDER,Select concatenation order,0,rw
|
||||
SGPIO_SLICE_MUX_CFG0,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG0,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG0,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG0,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG0,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG0,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG0,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG1,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG1,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG1,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG1,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG1,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG1,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG1,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG2,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG2,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG2,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG2,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG2,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG2,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG2,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG3,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG3,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG3,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG3,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG3,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG3,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG3,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG4,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG4,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG4,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG4,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG4,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG4,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG4,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG5,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG5,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG5,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG5,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG5,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG5,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG5,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG6,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG6,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG6,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG6,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG6,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG6,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG6,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG7,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG7,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG7,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG7,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG7,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG7,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG7,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG8,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG8,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG8,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG8,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG8,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG8,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG8,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG9,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG9,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG9,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG9,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG9,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG9,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG9,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG10,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG10,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG10,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG10,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG10,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG10,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG10,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG11,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG11,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG11,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG11,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG11,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG11,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG11,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG12,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG12,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG12,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG12,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG12,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG12,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG12,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG13,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG13,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG13,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG13,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG13,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG13,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG13,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG14,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG14,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG14,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG14,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG14,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG14,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG14,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_SLICE_MUX_CFG15,0,1,MATCH_MODE,Match mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG15,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG15,2,1,CLKGEN_MODE,Clock generation mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG15,3,1,INV_OUT_CLK,Invert output clock,0,rw
|
||||
SGPIO_SLICE_MUX_CFG15,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
|
||||
SGPIO_SLICE_MUX_CFG15,6,2,PARALLEL_MODE,Parallel mode,0,rw
|
||||
SGPIO_SLICE_MUX_CFG15,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
|
||||
SGPIO_POS0,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS0,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS1,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS1,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS2,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS2,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS3,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS3,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS4,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS4,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS5,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS5,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS6,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS6,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS7,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS7,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS8,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS8,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS9,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS9,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS10,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS10,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS11,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS11,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS12,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS12,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS13,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS13,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS14,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS14,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
SGPIO_POS15,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
|
||||
SGPIO_POS15,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
|
||||
|
File diff suppressed because it is too large
Load Diff
|
|
@ -1,63 +0,0 @@
|
|||
SSP0_CR0,0,4,DSS,Data Size Select,0,rw
|
||||
SSP0_CR0,4,2,FRF,Frame Format,0,rw
|
||||
SSP0_CR0,6,1,CPOL,Clock Out Polarity,0,rw
|
||||
SSP0_CR0,7,1,CPHA,Clock Out Phase,0,rw
|
||||
SSP0_CR0,8,8,SCR,Serial Clock Rate,0,rw
|
||||
SSP1_CR0,0,4,DSS,Data Size Select,0,rw
|
||||
SSP1_CR0,4,2,FRF,Frame Format,0,rw
|
||||
SSP1_CR0,6,1,CPOL,Clock Out Polarity,0,rw
|
||||
SSP1_CR0,7,1,CPHA,Clock Out Phase,0,rw
|
||||
SSP1_CR0,8,8,SCR,Serial Clock Rate,0,rw
|
||||
SSP0_CR1,0,1,LBM,Loop Back Mode,0,rw
|
||||
SSP0_CR1,1,1,SSE,SSP Enable,0,rw
|
||||
SSP0_CR1,2,1,MS,Master/Slave Mode,0,rw
|
||||
SSP0_CR1,3,1,SOD,Slave Output Disable,0,rw
|
||||
SSP1_CR1,1,1,SSE,SSP Enable,0,rw
|
||||
SSP1_CR1,2,1,MS,Master/Slave Mode,0,rw
|
||||
SSP1_CR1,3,1,SOD,Slave Output Disable,0,rw
|
||||
SSP0_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
|
||||
SSP1_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
|
||||
SSP0_SR,0,1,TFE,Transmit FIFO Empty,1,r
|
||||
SSP0_SR,1,1,TNF,Transmit FIFO Not Full,1,r
|
||||
SSP0_SR,2,1,RNE,Receive FIFO Not Empty,0,r
|
||||
SSP0_SR,3,1,RFF,Receive FIFO Full,0,r
|
||||
SSP0_SR,4,1,BSY,Busy.,0,r
|
||||
SSP1_SR,0,1,TFE,Transmit FIFO Empty,1,r
|
||||
SSP1_SR,1,1,TNF,Transmit FIFO Not Full,1,r
|
||||
SSP1_SR,2,1,RNE,Receive FIFO Not Empty,0,r
|
||||
SSP1_SR,3,1,RFF,Receive FIFO Full,0,r
|
||||
SSP1_SR,4,1,BSY,Busy.,0,r
|
||||
SSP0_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
|
||||
SSP1_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
|
||||
SSP0_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
|
||||
SSP0_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
|
||||
SSP0_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
|
||||
SSP0_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
|
||||
SSP1_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
|
||||
SSP1_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
|
||||
SSP1_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
|
||||
SSP1_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
|
||||
SSP0_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
|
||||
SSP0_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
|
||||
SSP0_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
|
||||
SSP0_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
|
||||
SSP1_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
|
||||
SSP1_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
|
||||
SSP1_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
|
||||
SSP1_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
|
||||
SSP0_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
|
||||
SSP0_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
|
||||
SSP0_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
|
||||
SSP0_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
|
||||
SSP1_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
|
||||
SSP1_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
|
||||
SSP1_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
|
||||
SSP1_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
|
||||
SSP0_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
|
||||
SSP0_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
|
||||
SSP1_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
|
||||
SSP1_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
|
||||
SSP0_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
|
||||
SSP0_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
|
||||
SSP1_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
|
||||
SSP1_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
|
||||
|
|
|
@ -0,0 +1,445 @@
|
|||
!!omap
|
||||
- SSP0_CR0:
|
||||
fields: !!omap
|
||||
- DSS:
|
||||
access: rw
|
||||
description: Data Size Select
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- FRF:
|
||||
access: rw
|
||||
description: Frame Format
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- CPOL:
|
||||
access: rw
|
||||
description: Clock Out Polarity
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CPHA:
|
||||
access: rw
|
||||
description: Clock Out Phase
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SCR:
|
||||
access: rw
|
||||
description: Serial Clock Rate
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- SSP1_CR0:
|
||||
fields: !!omap
|
||||
- DSS:
|
||||
access: rw
|
||||
description: Data Size Select
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 4
|
||||
- FRF:
|
||||
access: rw
|
||||
description: Frame Format
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- CPOL:
|
||||
access: rw
|
||||
description: Clock Out Polarity
|
||||
lsb: 6
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- CPHA:
|
||||
access: rw
|
||||
description: Clock Out Phase
|
||||
lsb: 7
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SCR:
|
||||
access: rw
|
||||
description: Serial Clock Rate
|
||||
lsb: 8
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- SSP0_CR1:
|
||||
fields: !!omap
|
||||
- LBM:
|
||||
access: rw
|
||||
description: Loop Back Mode
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSE:
|
||||
access: rw
|
||||
description: SSP Enable
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- MS:
|
||||
access: rw
|
||||
description: Master/Slave Mode
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SOD:
|
||||
access: rw
|
||||
description: Slave Output Disable
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP1_CR1:
|
||||
fields: !!omap
|
||||
- SSE:
|
||||
access: rw
|
||||
description: SSP Enable
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- MS:
|
||||
access: rw
|
||||
description: Master/Slave Mode
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SOD:
|
||||
access: rw
|
||||
description: Slave Output Disable
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP0_DR:
|
||||
fields: !!omap
|
||||
- DATA:
|
||||
access: rw
|
||||
description: Software can write data to be transmitted to this register, and
|
||||
read data that has been
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 16
|
||||
- SSP1_DR:
|
||||
fields: !!omap
|
||||
- DATA:
|
||||
access: rw
|
||||
description: Software can write data to be transmitted to this register, and
|
||||
read data that has been
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 16
|
||||
- SSP0_SR:
|
||||
fields: !!omap
|
||||
- TFE:
|
||||
access: r
|
||||
description: Transmit FIFO Empty
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- TNF:
|
||||
access: r
|
||||
description: Transmit FIFO Not Full
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RNE:
|
||||
access: r
|
||||
description: Receive FIFO Not Empty
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RFF:
|
||||
access: r
|
||||
description: Receive FIFO Full
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BSY:
|
||||
access: r
|
||||
description: Busy.
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP1_SR:
|
||||
fields: !!omap
|
||||
- TFE:
|
||||
access: r
|
||||
description: Transmit FIFO Empty
|
||||
lsb: 0
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- TNF:
|
||||
access: r
|
||||
description: Transmit FIFO Not Full
|
||||
lsb: 1
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- RNE:
|
||||
access: r
|
||||
description: Receive FIFO Not Empty
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RFF:
|
||||
access: r
|
||||
description: Receive FIFO Full
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- BSY:
|
||||
access: r
|
||||
description: Busy.
|
||||
lsb: 4
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP0_CPSR:
|
||||
fields: !!omap
|
||||
- CPSDVSR:
|
||||
access: rw
|
||||
description: SSP Clock Prescale Register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- SSP1_CPSR:
|
||||
fields: !!omap
|
||||
- CPSDVSR:
|
||||
access: rw
|
||||
description: SSP Clock Prescale Register
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 8
|
||||
- SSP0_IMSC:
|
||||
fields: !!omap
|
||||
- RORIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when a Receive
|
||||
Overrun occurs
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when a Receive
|
||||
Time-out condition occurs
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when the Rx
|
||||
FIFO is at least half full
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when the Tx
|
||||
FIFO is at least half empty
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP1_IMSC:
|
||||
fields: !!omap
|
||||
- RORIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when a Receive
|
||||
Overrun occurs
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when a Receive
|
||||
Time-out condition occurs
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when the Rx
|
||||
FIFO is at least half full
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXIM:
|
||||
access: rw
|
||||
description: Software should set this bit to enable interrupt when the Tx
|
||||
FIFO is at least half empty
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP0_RIS:
|
||||
fields: !!omap
|
||||
- RORRIS:
|
||||
access: r
|
||||
description: This bit is 1 if another frame was completely received while
|
||||
the RxFIFO was full
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTRIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is not empty, and has not been read
|
||||
for a time-out period
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXRIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is at least half full
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXRIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Tx FIFO is at least half empty
|
||||
lsb: 3
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- SSP1_RIS:
|
||||
fields: !!omap
|
||||
- RORRIS:
|
||||
access: r
|
||||
description: This bit is 1 if another frame was completely received while
|
||||
the RxFIFO was full
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTRIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is not empty, and has not been read
|
||||
for a time-out period
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXRIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is at least half full
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXRIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Tx FIFO is at least half empty
|
||||
lsb: 3
|
||||
reset_value: '1'
|
||||
width: 1
|
||||
- SSP0_MIS:
|
||||
fields: !!omap
|
||||
- RORMIS:
|
||||
access: r
|
||||
description: This bit is 1 if another frame was completely received while
|
||||
the RxFIFO was full, and this interrupt is enabled
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTMIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is not empty, has not been read
|
||||
for a time-out period, and this interrupt is enabled
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXMIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is at least half full, and this
|
||||
interrupt is enabled
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXMIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Tx FIFO is at least half empty, and this
|
||||
interrupt is enabled
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP1_MIS:
|
||||
fields: !!omap
|
||||
- RORMIS:
|
||||
access: r
|
||||
description: This bit is 1 if another frame was completely received while
|
||||
the RxFIFO was full, and this interrupt is enabled
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RTMIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is not empty, has not been read
|
||||
for a time-out period, and this interrupt is enabled
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXMIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Rx FIFO is at least half full, and this
|
||||
interrupt is enabled
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXMIS:
|
||||
access: r
|
||||
description: This bit is 1 if the Tx FIFO is at least half empty, and this
|
||||
interrupt is enabled
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP0_ICR:
|
||||
fields: !!omap
|
||||
- RORIC:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
|
||||
was full' interrupt
|
||||
lsb: 0
|
||||
reset_value: ''
|
||||
width: 1
|
||||
- RTIC:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the Rx FIFO was not empty and
|
||||
has not been read for a time-out period interrupt
|
||||
lsb: 1
|
||||
reset_value: ''
|
||||
width: 1
|
||||
- SSP1_ICR:
|
||||
fields: !!omap
|
||||
- RORIC:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
|
||||
was full' interrupt
|
||||
lsb: 0
|
||||
reset_value: ''
|
||||
width: 1
|
||||
- RTIC:
|
||||
access: w
|
||||
description: Writing a 1 to this bit clears the Rx FIFO was not empty and
|
||||
has not been read for a time-out period interrupt
|
||||
lsb: 1
|
||||
reset_value: ''
|
||||
width: 1
|
||||
- SSP0_DMACR:
|
||||
fields: !!omap
|
||||
- RXDMAE:
|
||||
access: rw
|
||||
description: Receive DMA Enable
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXDMAE:
|
||||
access: rw
|
||||
description: Transmit DMA Enable
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- SSP1_DMACR:
|
||||
fields: !!omap
|
||||
- RXDMAE:
|
||||
access: rw
|
||||
description: Receive DMA Enable
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXDMAE:
|
||||
access: rw
|
||||
description: Transmit DMA Enable
|
||||
lsb: 1
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
|
|
@ -1,221 +0,0 @@
|
|||
USB0_CAPLENGTH,0,8,CAPLENGTH,Indicates offset to add to the register base address at the beginning of the Operational Register,0x40,r
|
||||
USB0_CAPLENGTH,8,16,HCIVERSION,BCD encoding of the EHCI revision number supported by this host controller,0x100,r
|
||||
USB0_HCSPARAMS,0,4,N_PORTS,Number of downstream ports,0x1,r
|
||||
USB0_HCSPARAMS,4,1,PPC,Port Power Control,0x1,r
|
||||
USB0_HCSPARAMS,8,4,N_PCC,Number of Ports per Companion Controller,0x0,r
|
||||
USB0_HCSPARAMS,12,4,N_CC,Number of Companion Controller,0x0,r
|
||||
USB0_HCSPARAMS,16,1,PI,Port indicators,0x1,r
|
||||
USB0_HCSPARAMS,20,4,N_PTT,Number of Ports per Transaction Translator,0x0,r
|
||||
USB0_HCSPARAMS,24,4,N_TT,Number of Transaction Translators,0x0,r
|
||||
USB0_HCCPARAMS,0,1,ADC,64-bit Addressing Capability,0,r
|
||||
USB0_HCCPARAMS,1,1,PFL,Programmable Frame List Flag,1,r
|
||||
USB0_HCCPARAMS,2,1,ASP,Asynchronous Schedule Park Capability,1,r
|
||||
USB0_HCCPARAMS,4,4,IST,Isochronous Scheduling Threshold,0,r
|
||||
USB0_HCCPARAMS,8,4,EECP,EHCI Extended Capabilities Pointer,0,r
|
||||
USB0_DCCPARAMS,0,5,DEN,Device Endpoint Number,0x4,r
|
||||
USB0_DCCPARAMS,7,1,DC,Device Capable,0x1,r
|
||||
USB0_DCCPARAMS,8,1,HC,Host Capable,0x1,r
|
||||
USB0_USBCMD_D,0,1,RS,Run/Stop,0,rw
|
||||
USB0_USBCMD_D,1,1,RST,Controller reset,0,rw
|
||||
USB0_USBCMD_D,13,1,SUTW,Setup trip wire,0,rw
|
||||
USB0_USBCMD_D,14,1,ATDTW,Add dTD trip wire,0,rw
|
||||
USB0_USBCMD_D,16,8,ITC,Interrupt threshold control,0x8,rw
|
||||
USB0_USBCMD_H,0,1,RS,Run/Stop,0,rw
|
||||
USB0_USBCMD_H,1,1,RST,Controller reset,0,rw
|
||||
USB0_USBCMD_H,2,1,FS0,Bit 0 of the Frame List Size bits,0,
|
||||
USB0_USBCMD_H,3,1,FS1,Bit 1 of the Frame List Size bits,0,
|
||||
USB0_USBCMD_H,4,1,PSE,This bit controls whether the host controller skips processing the periodic schedule,0,rw
|
||||
USB0_USBCMD_H,5,1,ASE,This bit controls whether the host controller skips processing the asynchronous schedule,0,rw
|
||||
USB0_USBCMD_H,6,1,IAA,This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule,0,rw
|
||||
USB0_USBCMD_H,8,2,ASP1_0,Asynchronous schedule park mode,0x3,rw
|
||||
USB0_USBCMD_H,11,1,ASPE,Asynchronous Schedule Park Mode Enable,1,rw
|
||||
USB0_USBCMD_H,15,1,FS2,Bit 2 of the Frame List Size bits,0,
|
||||
USB0_USBCMD_H,16,8,ITC,Interrupt threshold control,0x8,rw
|
||||
USB0_USBSTS_D,0,1,UI,USB interrupt,0,rwc
|
||||
USB0_USBSTS_D,1,1,UEI,USB error interrupt,0,rwc
|
||||
USB0_USBSTS_D,2,1,PCI,Port change detect,0,rwc
|
||||
USB0_USBSTS_D,6,1,URI,USB reset received,0,rwc
|
||||
USB0_USBSTS_D,7,1,SRI,SOF received,0,rwc
|
||||
USB0_USBSTS_D,8,1,SLI,DCSuspend,0,rwc
|
||||
USB0_USBSTS_D,16,1,NAKI,NAK interrupt bit,0,r
|
||||
USB0_USBSTS_H,0,1,UI,USB interrupt,0,rwc
|
||||
USB0_USBSTS_H,1,1,UEI,USB error interrupt,0,rwc
|
||||
USB0_USBSTS_H,2,1,PCI,Port change detect,0,rwc
|
||||
USB0_USBSTS_H,3,1,FRI,Frame list roll-over,0,rwc
|
||||
USB0_USBSTS_H,5,1,AAI,Interrupt on async advance,0,rwc
|
||||
USB0_USBSTS_H,7,1,SRI,SOF received,0,rwc
|
||||
USB0_USBSTS_H,12,1,HCH,HCHalted,1,r
|
||||
USB0_USBSTS_H,13,1,RCL,Reclamation,0,r
|
||||
USB0_USBSTS_H,14,1,PS,Periodic schedule status,0,r
|
||||
USB0_USBSTS_H,15,1,AS,Asynchronous schedule status,0,
|
||||
USB0_USBSTS_H,18,1,UAI,USB host asynchronous interrupt (USBHSTASYNCINT),0,rwc
|
||||
USB0_USBSTS_H,19,1,UPI,USB host periodic interrupt (USBHSTPERINT),0,rwc
|
||||
USB0_USBINTR_D,0,1,UE,USB interrupt enable,0,rw
|
||||
USB0_USBINTR_D,1,1,UEE,USB error interrupt enable,0,rw
|
||||
USB0_USBINTR_D,2,1,PCE,Port change detect enable,0,rw
|
||||
USB0_USBINTR_D,6,1,URE,USB reset enable,0,rw
|
||||
USB0_USBINTR_D,7,1,SRE,SOF received enable,0,rw
|
||||
USB0_USBINTR_D,8,1,SLE,Sleep enable,0,rw
|
||||
USB0_USBINTR_D,16,1,NAKE,NAK interrupt enable,0,rw
|
||||
USB0_USBINTR_H,0,1,UE,USB interrupt enable,0,rw
|
||||
USB0_USBINTR_H,1,1,UEE,USB error interrupt enable,0,rw
|
||||
USB0_USBINTR_H,2,1,PCE,Port change detect enable,0,rw
|
||||
USB0_USBINTR_H,3,1,FRE,Frame list rollover enable,0,rw
|
||||
USB0_USBINTR_H,5,1,AAE,Interrupt on asynchronous advance enable,0,rw
|
||||
USB0_USBINTR_H,7,1,SRE,SOF received enable,0,
|
||||
USB0_USBINTR_H,18,1,UAIE,USB host asynchronous interrupt enable,0,rw
|
||||
USB0_USBINTR_H,19,1,UPIA,USB host periodic interrupt enable,0,rw
|
||||
USB0_FRINDEX_D,0,3,FRINDEX2_0,Current micro frame number,,r
|
||||
USB0_FRINDEX_D,3,11,FRINDEX13_3,Current frame number of the last frame transmitted,,r
|
||||
USB0_FRINDEX_H,0,3,FRINDEX2_0,Current micro frame number,,rw
|
||||
USB0_FRINDEX_H,3,10,FRINDEX12_3,Frame list current index,,rw
|
||||
USB0_DEVICEADDR,24,1,USBADRA,Device address advance,0,
|
||||
USB0_DEVICEADDR,25,7,USBADR,USB device address,0,rw
|
||||
USB0_PERIODICLISTBASE,12,20,PERBASE31_12,Base Address (Low),,rw
|
||||
USB0_ENDPOINTLISTADDR,11,21,EPBASE31_11,Endpoint list pointer (low),,rw
|
||||
USB0_ASYNCLISTADDR,5,27,ASYBASE31_5,Link pointer (Low) LPL,,rw
|
||||
USB0_TTCTRL,24,7,TTHA,Hub address when FS or LS device are connected directly,,rw
|
||||
USB0_BURSTSIZE,0,8,RXPBURST,Programmable RX burst length,0x10,rw
|
||||
USB0_BURSTSIZE,8,8,TXPBURST,Programmable TX burst length,0x10,rw
|
||||
USB0_TXFILLTUNING,0,8,TXSCHOH,FIFO burst threshold,0x2,rw
|
||||
USB0_TXFILLTUNING,8,5,TXSCHEATLTH,Scheduler health counter,0x0,rw
|
||||
USB0_TXFILLTUNING,16,6,TXFIFOTHRES,Scheduler overhead,0x0,rw
|
||||
USB0_BINTERVAL,0,4,BINT,bInterval value,0x00,rw
|
||||
USB0_ENDPTNAK,0,6,EPRN,Rx endpoint NAK,0x00,rwc
|
||||
USB0_ENDPTNAK,16,6,EPTN,Tx endpoint NAK,0x00,rwc
|
||||
USB0_ENDPTNAKEN,0,6,EPRNE,Rx endpoint NAK enable,0x00,rw
|
||||
USB0_ENDPTNAKEN,16,6,EPTNE,Tx endpoint NAK,0x00,rw
|
||||
USB0_PORTSC1_D,0,1,CCS,Current connect status,0,r
|
||||
USB0_PORTSC1_D,2,1,PE,Port enable,1,r
|
||||
USB0_PORTSC1_D,3,1,PEC,Port enable/disable change,0,r
|
||||
USB0_PORTSC1_D,6,1,FPR,Force port resume,0,rw
|
||||
USB0_PORTSC1_D,7,1,SUSP,Suspend,0,r
|
||||
USB0_PORTSC1_D,8,1,PR,Port reset,0,r
|
||||
USB0_PORTSC1_D,9,1,HSP,High-speed status,0,r
|
||||
USB0_PORTSC1_D,14,2,PIC1_0,Port indicator control,0,rw
|
||||
USB0_PORTSC1_D,16,4,PTC3_0,Port test control,0,rw
|
||||
USB0_PORTSC1_D,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
|
||||
USB0_PORTSC1_D,24,1,PFSC,Port force full speed connect,0,rw
|
||||
USB0_PORTSC1_D,26,2,PSPD,Port speed,0,r
|
||||
USB0_PORTSC1_H,0,1,CCS,Current connect status,0,rwc
|
||||
USB0_PORTSC1_H,1,1,CSC,Connect status change,0,rwc
|
||||
USB0_PORTSC1_H,2,1,PE,Port enable,0,rw
|
||||
USB0_PORTSC1_H,3,1,PEC,Port disable/enable change,0,rwc
|
||||
USB0_PORTSC1_H,4,1,OCA,Over-current active,0,r
|
||||
USB0_PORTSC1_H,5,1,OCC,Over-current change,0,rwc
|
||||
USB0_PORTSC1_H,6,1,FPR,Force port resume,0,rw
|
||||
USB0_PORTSC1_H,7,1,SUSP,Suspend,0,rw
|
||||
USB0_PORTSC1_H,8,1,PR,Port reset,0,rw
|
||||
USB0_PORTSC1_H,9,1,HSP,High-speed status,0,r
|
||||
USB0_PORTSC1_H,10,2,LS,Line status,0x3,r
|
||||
USB0_PORTSC1_H,12,1,PP,Port power control,0,rw
|
||||
USB0_PORTSC1_H,14,2,PIC1_0,Port indicator control,0,rw
|
||||
USB0_PORTSC1_H,16,4,PTC3_0,Port test control,0,rw
|
||||
USB0_PORTSC1_H,20,1,WKCN,Wake on connect enable (WKCNNT_E),0,rw
|
||||
USB0_PORTSC1_H,21,1,WKDC,Wake on disconnect enable (WKDSCNNT_E),0,rw
|
||||
USB0_PORTSC1_H,22,1,WKOC,Wake on over-current enable (WKOC_E),0,rw
|
||||
USB0_PORTSC1_H,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
|
||||
USB0_PORTSC1_H,24,1,PFSC,Port force full speed connect,0,rw
|
||||
USB0_PORTSC1_H,26,2,PSPD,Port speed,0,r
|
||||
USB0_OTGSC,0,1,VD,VBUS_Discharge,0,rw
|
||||
USB0_OTGSC,1,1,VC,VBUS_Charge,0,rw
|
||||
USB0_OTGSC,2,1,HAAR,Hardware assist auto_reset,0,rw
|
||||
USB0_OTGSC,3,1,OT,OTG termination,0,rw
|
||||
USB0_OTGSC,4,1,DP,Data pulsing,0,rw
|
||||
USB0_OTGSC,5,1,IDPU,ID pull-up,1,rw
|
||||
USB0_OTGSC,6,1,HADP,Hardware assist data pulse,0,rw
|
||||
USB0_OTGSC,7,1,HABA,Hardware assist B-disconnect to A-connect,0,rw
|
||||
USB0_OTGSC,8,1,ID,USB ID,0,r
|
||||
USB0_OTGSC,9,1,AVV,A-VBUS valid,0,r
|
||||
USB0_OTGSC,10,1,ASV,A-session valid,0,r
|
||||
USB0_OTGSC,11,1,BSV,B-session valid,0,r
|
||||
USB0_OTGSC,12,1,BSE,B-session end,0,r
|
||||
USB0_OTGSC,13,1,MS1T,1 millisecond timer toggle,0,r
|
||||
USB0_OTGSC,14,1,DPS,Data bus pulsing status,0,r
|
||||
USB0_OTGSC,16,1,IDIS,USB ID interrupt status,0,rwc
|
||||
USB0_OTGSC,17,1,AVVIS,A-VBUS valid interrupt status,0,rwc
|
||||
USB0_OTGSC,18,1,ASVIS,A-Session valid interrupt status,0,rwc
|
||||
USB0_OTGSC,19,1,BSVIS,B-Session valid interrupt status,0,rwc
|
||||
USB0_OTGSC,20,1,BSEIS,B-Session end interrupt status,0,rwc
|
||||
USB0_OTGSC,21,1,MS1S,1 millisecond timer interrupt status,0,rwc
|
||||
USB0_OTGSC,22,1,DPIS,Data pulse interrupt status,0,rwc
|
||||
USB0_OTGSC,24,1,IDIE,USB ID interrupt enable,0,rw
|
||||
USB0_OTGSC,25,1,AVVIE,A-VBUS valid interrupt enable,0,rw
|
||||
USB0_OTGSC,26,1,ASVIE,A-session valid interrupt enable,0,rw
|
||||
USB0_OTGSC,27,1,BSVIE,B-session valid interrupt enable,0,rw
|
||||
USB0_OTGSC,28,1,BSEIE,B-session end interrupt enable,0,rw
|
||||
USB0_OTGSC,29,1,MS1E,1 millisecond timer interrupt enable,0,rw
|
||||
USB0_OTGSC,30,1,DPIE,Data pulse interrupt enable,0,rw
|
||||
USB0_USBMODE_D,0,2,CM1_0,Controller mode,0,rwo
|
||||
USB0_USBMODE_D,2,1,ES,Endian select,0,rw
|
||||
USB0_USBMODE_D,3,1,SLOM,Setup Lockout mode,0,rw
|
||||
USB0_USBMODE_D,4,1,SDIS,Setup Lockout mode,0,rw
|
||||
USB0_USBMODE_H,0,2,CM,Controller mode,0,rwo
|
||||
USB0_USBMODE_H,2,1,ES,Endian select,0,rw
|
||||
USB0_USBMODE_H,4,1,SDIS,Stream disable mode,0,rw
|
||||
USB0_USBMODE_H,5,1,VBPS,VBUS power select,0,rwo
|
||||
USB0_ENDPTSETUPSTAT,0,6,ENDPTSETUPSTAT,Setup endpoint status for logical endpoints 0 to 5,0,rwc
|
||||
USB0_ENDPTPRIME,0,6,PERB,Prime endpoint receive buffer for physical OUT endpoints 5 to 0,0,rws
|
||||
USB0_ENDPTPRIME,16,6,PETB,Prime endpoint transmit buffer for physical IN endpoints 5 to 0,0,rws
|
||||
USB0_ENDPTFLUSH,0,6,FERB,Flush endpoint receive buffer for physical OUT endpoints 5 to 0,0,rwc
|
||||
USB0_ENDPTFLUSH,16,6,FETB,Flush endpoint transmit buffer for physical IN endpoints 5 to 0,0,rwc
|
||||
USB0_ENDPTSTAT,0,6,ERBR,Endpoint receive buffer ready for physical OUT endpoints 5 to 0,0,r
|
||||
USB0_ENDPTSTAT,16,6,ETBR,Endpoint transmit buffer ready for physical IN endpoints 3 to 0,0,r
|
||||
USB0_ENDPTCOMPLETE,0,6,ERCE,Endpoint receive complete event for physical OUT endpoints 5 to 0,0,rwc
|
||||
USB0_ENDPTCOMPLETE,16,6,ETCE,Endpoint transmit complete event for physical IN endpoints 5 to 0,0,rwc
|
||||
USB0_ENDPTCTRL0,0,1,RXS,Rx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL0,2,2,RXT1_0,Endpoint type,0,rw
|
||||
USB0_ENDPTCTRL0,7,1,RXE,Rx endpoint enable,1,r
|
||||
USB0_ENDPTCTRL0,16,1,TXS,Tx endpoint stall,,rw
|
||||
USB0_ENDPTCTRL0,18,2,TXT1_0,Endpoint type,0,r
|
||||
USB0_ENDPTCTRL0,23,1,TXE,Tx endpoint enable,1,r
|
||||
USB0_ENDPTCTRL1,0,1,RXS,Rx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL1,2,2,RXT,Endpoint type,0,rw
|
||||
USB0_ENDPTCTRL1,5,1,RXI,Rx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL1,6,1,RXR,Rx data toggle reset,0,ws
|
||||
USB0_ENDPTCTRL1,7,1,RXE,Rx endpoint enable,0,rw
|
||||
USB0_ENDPTCTRL1,16,1,TXS,Tx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL1,18,2,TXT1_0,Tx Endpoint type,0,r
|
||||
USB0_ENDPTCTRL1,21,1,TXI,Tx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL1,22,1,TXR,Tx data toggle reset,1,ws
|
||||
USB0_ENDPTCTRL1,23,1,TXE,Tx endpoint enable,0,r
|
||||
USB0_ENDPTCTRL2,0,1,RXS,Rx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL2,2,2,RXT,Endpoint type,0,rw
|
||||
USB0_ENDPTCTRL2,5,1,RXI,Rx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL2,6,1,RXR,Rx data toggle reset,0,ws
|
||||
USB0_ENDPTCTRL2,7,1,RXE,Rx endpoint enable,0,rw
|
||||
USB0_ENDPTCTRL2,16,1,TXS,Tx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL2,18,2,TXT1_0,Tx Endpoint type,0,r
|
||||
USB0_ENDPTCTRL2,21,1,TXI,Tx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL2,22,1,TXR,Tx data toggle reset,1,ws
|
||||
USB0_ENDPTCTRL2,23,1,TXE,Tx endpoint enable,0,r
|
||||
USB0_ENDPTCTRL3,0,1,RXS,Rx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL3,2,2,RXT,Endpoint type,0,rw
|
||||
USB0_ENDPTCTRL3,5,1,RXI,Rx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL3,6,1,RXR,Rx data toggle reset,0,ws
|
||||
USB0_ENDPTCTRL3,7,1,RXE,Rx endpoint enable,0,rw
|
||||
USB0_ENDPTCTRL3,16,1,TXS,Tx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL3,18,2,TXT1_0,Tx Endpoint type,0,r
|
||||
USB0_ENDPTCTRL3,21,1,TXI,Tx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL3,22,1,TXR,Tx data toggle reset,1,ws
|
||||
USB0_ENDPTCTRL3,23,1,TXE,Tx endpoint enable,0,r
|
||||
USB0_ENDPTCTRL4,0,1,RXS,Rx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL4,2,2,RXT,Endpoint type,0,rw
|
||||
USB0_ENDPTCTRL4,5,1,RXI,Rx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL4,6,1,RXR,Rx data toggle reset,0,ws
|
||||
USB0_ENDPTCTRL4,7,1,RXE,Rx endpoint enable,0,rw
|
||||
USB0_ENDPTCTRL4,16,1,TXS,Tx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL4,18,2,TXT1_0,Tx Endpoint type,0,r
|
||||
USB0_ENDPTCTRL4,21,1,TXI,Tx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL4,22,1,TXR,Tx data toggle reset,1,ws
|
||||
USB0_ENDPTCTRL4,23,1,TXE,Tx endpoint enable,0,r
|
||||
USB0_ENDPTCTRL5,0,1,RXS,Rx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL5,2,2,RXT,Endpoint type,0,rw
|
||||
USB0_ENDPTCTRL5,5,1,RXI,Rx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL5,6,1,RXR,Rx data toggle reset,0,ws
|
||||
USB0_ENDPTCTRL5,7,1,RXE,Rx endpoint enable,0,rw
|
||||
USB0_ENDPTCTRL5,16,1,TXS,Tx endpoint stall,0,rw
|
||||
USB0_ENDPTCTRL5,18,2,TXT1_0,Tx Endpoint type,0,r
|
||||
USB0_ENDPTCTRL5,21,1,TXI,Tx data toggle inhibit,0,rw
|
||||
USB0_ENDPTCTRL5,22,1,TXR,Tx data toggle reset,1,ws
|
||||
USB0_ENDPTCTRL5,23,1,TXE,Tx endpoint enable,0,r
|
||||
|
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue