remembered to use MMIO32() everywhere
This commit is contained in:
Michael Ossmann
parent
98bb0b5c91
commit
5585e41311
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@ -26,359 +26,359 @@
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/* --- CCU1 registers ------------------------------------------------------ */
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/* CCU1 power mode register */
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#define CCU1_PM (CCU1_BASE + 0x000)
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#define CCU1_PM MMIO32(CCU1_BASE + 0x000)
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/* CCU1 base clock status register */
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#define CCU1_BASE_STAT (CCU1_BASE + 0x004)
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#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)
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/* CLK_APB3_BUS clock configuration register */
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#define CCU1_CLK_APB3_BUS_CFG (CCU1_BASE + 0x100)
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#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)
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/* CLK_APB3_BUS clock status register */
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#define CCU1_CLK_APB3_BUS_STAT (CCU1_BASE + 0x104)
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#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)
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/* CLK_APB3_I2C1 configuration register */
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#define CCU1_CLK_APB3_I2C1_CFG (CCU1_BASE + 0x108)
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#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)
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/* CLK_APB3_I2C1 status register */
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#define CCU1_CLK_APB3_I2C1_STAT (CCU1_BASE + 0x10C)
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#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)
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/* CLK_APB3_DAC configuration register */
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#define CCU1_CLK_APB3_DAC_CFG (CCU1_BASE + 0x110)
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#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)
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/* CLK_APB3_DAC status register */
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#define CCU1_CLK_APB3_DAC_STAT (CCU1_BASE + 0x114)
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#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)
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/* CLK_APB3_ADC0 configuration register */
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#define CCU1_CLK_APB3_ADC0_CFG (CCU1_BASE + 0x118)
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#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)
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/* CLK_APB3_ADC0 status register */
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#define CCU1_CLK_APB3_ADC0_STAT (CCU1_BASE + 0x11C)
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#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)
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/* CLK_APB3_ADC1 configuration register */
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#define CCU1_CLK_APB3_ADC1_CFG (CCU1_BASE + 0x120)
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#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)
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/* CLK_APB3_ADC1 status register */
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#define CCU1_CLK_APB3_ADC1_STAT (CCU1_BASE + 0x124)
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#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)
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/* CLK_APB3_CAN0 configuration register */
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#define CCU1_CLK_APB3_CAN0_CFG (CCU1_BASE + 0x128)
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#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)
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/* CLK_APB3_CAN0 status register */
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#define CCU1_CLK_APB3_CAN0_STAT (CCU1_BASE + 0x12C)
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#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)
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/* CLK_APB1_BUS configuration register */
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#define CCU1_CLK_APB1_BUS_CFG (CCU1_BASE + 0x200)
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#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)
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/* CLK_APB1_BUS status register */
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#define CCU1_CLK_APB1_BUS_STAT (CCU1_BASE + 0x204)
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#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)
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/* CLK_APB1_MOTOCON configuration register */
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#define CCU1_CLK_APB1_MOTOCONPWM_CFG (CCU1_BASE + 0x208)
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#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)
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/* CLK_APB1_MOTOCON status register */
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#define CCU1_CLK_APB1_MOTOCONPWM_STAT (CCU1_BASE + 0x20C)
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#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)
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/* CLK_APB1_I2C0 configuration register */
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#define CCU1_CLK_APB1_I2C0_CFG (CCU1_BASE + 0x210)
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#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)
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/* CLK_APB1_I2C0 status register */
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#define CCU1_CLK_APB1_I2C0_STAT (CCU1_BASE + 0x214)
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#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)
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/* CLK_APB1_I2S configuration register */
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#define CCU1_CLK_APB1_I2S_CFG (CCU1_BASE + 0x218)
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#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)
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/* CLK_APB1_I2S status register */
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#define CCU1_CLK_APB1_I2S_STAT (CCU1_BASE + 0x21C)
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#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)
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/* CLK_APB3_CAN1 configuration register */
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#define CCU1_CLK_APB1_CAN1_CFG (CCU1_BASE + 0x220)
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#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)
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/* CLK_APB3_CAN1 status register */
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#define CCU1_CLK_APB1_CAN1_STAT (CCU1_BASE + 0x224)
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#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)
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/* CLK_SPIFI configuration register */
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#define CCU1_CLK_SPIFI_CFG (CCU1_BASE + 0x300)
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#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)
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/* CLK_SPIFI status register */
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#define CCU1_CLK_SPIFI_STAT (CCU1_BASE + 0x304)
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#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)
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/* CLK_M4_BUS configuration register */
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#define CCU1_CLK_M4_BUS_CFG (CCU1_BASE + 0x400)
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#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)
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/* CLK_M4_BUS status register */
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#define CCU1_CLK_M4_BUS_STAT (CCU1_BASE + 0x404)
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#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)
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/* CLK_M4_SPIFI configuration register */
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#define CCU1_CLK_M4_SPIFI_CFG (CCU1_BASE + 0x408)
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#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)
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/* CLK_M4_SPIFI status register */
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#define CCU1_CLK_M4_SPIFI_STAT (CCU1_BASE + 0x40C)
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#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)
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/* CLK_M4_GPIO configuration register */
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#define CCU1_CLK_M4_GPIO_CFG (CCU1_BASE + 0x410)
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#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)
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/* CLK_M4_GPIO status register */
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#define CCU1_CLK_M4_GPIO_STAT (CCU1_BASE + 0x414)
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#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)
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/* CLK_M4_LCD configuration register */
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#define CCU1_CLK_M4_LCD_CFG (CCU1_BASE + 0x418)
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#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)
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/* CLK_M4_LCD status register */
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#define CCU1_CLK_M4_LCD_STAT (CCU1_BASE + 0x41C)
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#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)
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/* CLK_M4_ETHERNET configuration register */
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#define CCU1_CLK_M4_ETHERNET_CFG (CCU1_BASE + 0x420)
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#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)
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/* CLK_M4_ETHERNET status register */
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#define CCU1_CLK_M4_ETHERNET_STAT (CCU1_BASE + 0x424)
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#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)
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/* CLK_M4_USB0 configuration register */
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#define CCU1_CLK_M4_USB0_CFG (CCU1_BASE + 0x428)
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#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)
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/* CLK_M4_USB0 status register */
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#define CCU1_CLK_M4_USB0_STAT (CCU1_BASE + 0x42C)
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#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)
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/* CLK_M4_EMC configuration register */
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#define CCU1_CLK_M4_EMC_CFG (CCU1_BASE + 0x430)
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#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)
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/* CLK_M4_EMC status register */
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#define CCU1_CLK_M4_EMC_STAT (CCU1_BASE + 0x434)
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#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)
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/* CLK_M4_SDIO configuration register */
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#define CCU1_CLK_M4_SDIO_CFG (CCU1_BASE + 0x438)
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#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)
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/* CLK_M4_SDIO status register */
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#define CCU1_CLK_M4_SDIO_STAT (CCU1_BASE + 0x43C)
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#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)
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/* CLK_M4_DMA configuration register */
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#define CCU1_CLK_M4_DMA_CFG (CCU1_BASE + 0x440)
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#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)
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/* CLK_M4_DMA status register */
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#define CCU1_CLK_M4_DMA_STAT (CCU1_BASE + 0x444)
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#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)
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/* CLK_M4_M4CORE configuration register */
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#define CCU1_CLK_M4_M4CORE_CFG (CCU1_BASE + 0x448)
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#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)
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/* CLK_M4_M4CORE status register */
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#define CCU1_CLK_M4_M4CORE_STAT (CCU1_BASE + 0x44C)
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#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)
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/* CLK_M4_SCT configuration register */
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#define CCU1_CLK_M4_SCT_CFG (CCU1_BASE + 0x468)
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#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)
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/* CLK_M4_SCT status register */
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#define CCU1_CLK_M4_SCT_STAT (CCU1_BASE + 0x46C)
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#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)
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/* CLK_M4_USB1 configuration register */
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#define CCU1_CLK_M4_USB1_CFG (CCU1_BASE + 0x470)
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#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)
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/* CLK_M4_USB1 status register */
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#define CCU1_CLK_M4_USB1_STAT (CCU1_BASE + 0x474)
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#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)
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/* CLK_M4_EMCDIV configuration register */
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#define CCU1_CLK_M4_EMCDIV_CFG (CCU1_BASE + 0x478)
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#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)
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/* CLK_M4_EMCDIV status register */
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#define CCU1_CLK_M4_EMCDIV_STAT (CCU1_BASE + 0x47C)
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#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)
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/* CLK_M4_M0_CFG configuration register */
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#define CCU1_CLK_M4_M0APP_CFG (CCU1_BASE + 0x490)
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#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)
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/* CLK_M4_M0_STAT status register */
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#define CCU1_CLK_M4_M0APP_STAT (CCU1_BASE + 0x494)
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#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)
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/* CLK_M4_VADC_CFG configuration register */
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#define CCU1_CLK_M4_VADC_CFG (CCU1_BASE + 0x498)
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#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)
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/* CLK_M4_VADC_STAT configuration register */
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#define CCU1_CLK_M4_VADC_STAT (CCU1_BASE + 0x49C)
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#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)
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/* CLK_M4_WWDT configuration register */
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#define CCU1_CLK_M4_WWDT_CFG (CCU1_BASE + 0x500)
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#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)
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/* CLK_M4_WWDT status register */
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#define CCU1_CLK_M4_WWDT_STAT (CCU1_BASE + 0x504)
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#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)
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/* CLK_M4_UART0 configuration register */
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#define CCU1_CLK_M4_USART0_CFG (CCU1_BASE + 0x508)
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#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)
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/* CLK_M4_UART0 status register */
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#define CCU1_CLK_M4_USART0_STAT (CCU1_BASE + 0x50C)
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#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)
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/* CLK_M4_UART1 configuration register */
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#define CCU1_CLK_M4_UART1_CFG (CCU1_BASE + 0x510)
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#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)
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/* CLK_M4_UART1 status register */
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#define CCU1_CLK_M4_UART1_STAT (CCU1_BASE + 0x514)
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#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)
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/* CLK_M4_SSP0 configuration register */
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#define CCU1_CLK_M4_SSP0_CFG (CCU1_BASE + 0x518)
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#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)
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/* CLK_M4_SSP0 status register */
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#define CCU1_CLK_M4_SSP0_STAT (CCU1_BASE + 0x51C)
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#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)
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/* CLK_M4_TIMER0 configuration register */
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#define CCU1_CLK_M4_TIMER0_CFG (CCU1_BASE + 0x520)
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#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)
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/* CLK_M4_TIMER0 status register */
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#define CCU1_CLK_M4_TIMER0_STAT (CCU1_BASE + 0x524)
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#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)
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/* CLK_M4_TIMER1 configuration register */
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#define CCU1_CLK_M4_TIMER1_CFG (CCU1_BASE + 0x528)
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#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)
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/* CLK_M4_TIMER1 status register */
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#define CCU1_CLK_M4_TIMER1_STAT (CCU1_BASE + 0x52C)
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#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)
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/* CLK_M4_SCU configuration register */
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#define CCU1_CLK_M4_SCU_CFG (CCU1_BASE + 0x530)
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#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)
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/* CLK_M4_SCU status register */
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#define CCU1_CLK_M4_SCU_STAT (CCU1_BASE + 0x534)
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#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)
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/* CLK_M4_CREG configuration register */
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#define CCU1_CLK_M4_CREG_CFG (CCU1_BASE + 0x538)
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#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)
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/* CLK_M4_CREG status register */
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#define CCU1_CLK_M4_CREG_STAT (CCU1_BASE + 0x53C)
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#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)
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/* CLK_M4_RITIMER configuration register */
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#define CCU1_CLK_M4_RITIMER_CFG (CCU1_BASE + 0x600)
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#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)
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/* CLK_M4_RITIMER status register */
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#define CCU1_CLK_M4_RITIMER_STAT (CCU1_BASE + 0x604)
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#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)
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/* CLK_M4_UART2 configuration register */
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#define CCU1_CLK_M4_USART2_CFG (CCU1_BASE + 0x608)
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#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)
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/* CLK_M4_UART2 status register */
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#define CCU1_CLK_M4_USART2_STAT (CCU1_BASE + 0x60C)
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#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)
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/* CLK_M4_UART3 configuration register */
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#define CCU1_CLK_M4_USART3_CFG (CCU1_BASE + 0x610)
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#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)
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/* CLK_M4_UART3 status register */
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#define CCU1_CLK_M4_USART3_STAT (CCU1_BASE + 0x614)
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||||
#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)
|
||||
|
||||
/* CLK_M4_TIMER2 configuration register */
|
||||
#define CCU1_CLK_M4_TIMER2_CFG (CCU1_BASE + 0x618)
|
||||
#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)
|
||||
|
||||
/* CLK_M4_TIMER2 status register */
|
||||
#define CCU1_CLK_M4_TIMER2_STAT (CCU1_BASE + 0x61C)
|
||||
#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)
|
||||
|
||||
/* CLK_M4_TIMER3 configuration register */
|
||||
#define CCU1_CLK_M4_TIMER3_CFG (CCU1_BASE + 0x620)
|
||||
#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)
|
||||
|
||||
/* CLK_M4_TIMER3 status register */
|
||||
#define CCU1_CLK_M4_TIMER3_STAT (CCU1_BASE + 0x624)
|
||||
#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)
|
||||
|
||||
/* CLK_M4_SSP1 configuration register */
|
||||
#define CCU1_CLK_M4_SSP1_CFG (CCU1_BASE + 0x628)
|
||||
#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)
|
||||
|
||||
/* CLK_M4_SSP1 status register */
|
||||
#define CCU1_CLK_M4_SSP1_STAT (CCU1_BASE + 0x62C)
|
||||
#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)
|
||||
|
||||
/* CLK_M4_QEI configuration register */
|
||||
#define CCU1_CLK_M4_QEI_CFG (CCU1_BASE + 0x630)
|
||||
#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)
|
||||
|
||||
/* CLK_M4_QEI status register */
|
||||
#define CCU1_CLK_M4_QEI_STAT (CCU1_BASE + 0x634)
|
||||
#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)
|
||||
|
||||
/* CLK_PERIPH_BUS configuration register */
|
||||
#define CCU1_CLK_PERIPH_BUS_CFG (CCU1_BASE + 0x700)
|
||||
#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)
|
||||
|
||||
/* CLK_PERIPH_BUS status register */
|
||||
#define CCU1_CLK_PERIPH_BUS_STAT (CCU1_BASE + 0x704)
|
||||
#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)
|
||||
|
||||
/* CLK_PERIPH_CORE configuration register */
|
||||
#define CCU1_CLK_PERIPH_CORE_CFG (CCU1_BASE + 0x710)
|
||||
#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)
|
||||
|
||||
/* CLK_PERIPH_CORE status register */
|
||||
#define CCU1_CLK_PERIPH_CORE_STAT (CCU1_BASE + 0x714)
|
||||
#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)
|
||||
|
||||
/* CLK_PERIPH_SGPIO configuration register */
|
||||
#define CCU1_CLK_PERIPH_SGPIO_CFG (CCU1_BASE + 0x718)
|
||||
#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)
|
||||
|
||||
/* CLK_PERIPH_SGPIO status register */
|
||||
#define CCU1_CLK_PERIPH_SGPIO_STAT (CCU1_BASE + 0x71C)
|
||||
#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)
|
||||
|
||||
/* CLK_USB0 configuration register */
|
||||
#define CCU1_CLK_USB0_CFG (CCU1_BASE + 0x800)
|
||||
#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)
|
||||
|
||||
/* CLK_USB0 status register */
|
||||
#define CCU1_CLK_USB0_STAT (CCU1_BASE + 0x804)
|
||||
#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)
|
||||
|
||||
/* CLK_USB1 configuration register */
|
||||
#define CCU1_CLK_USB1_CFG (CCU1_BASE + 0x900)
|
||||
#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)
|
||||
|
||||
/* CLK_USB1 status register */
|
||||
#define CCU1_CLK_USB1_STAT (CCU1_BASE + 0x904)
|
||||
#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)
|
||||
|
||||
/* CLK_SPI configuration register */
|
||||
#define CCU1_CLK_SPI_CFG (CCU1_BASE + 0xA00)
|
||||
#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)
|
||||
|
||||
/* CLK_SPI status register */
|
||||
#define CCU1_CLK_SPI_STAT (CCU1_BASE + 0xA04)
|
||||
#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)
|
||||
|
||||
/* CLK_VADC configuration register */
|
||||
#define CCU1_CLK_VADC_CFG (CCU1_BASE + 0xB00)
|
||||
#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)
|
||||
|
||||
/* CLK_VADC status register */
|
||||
#define CCU1_CLK_VADC_STAT (CCU1_BASE + 0xB04)
|
||||
#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)
|
||||
|
||||
/* --- CCU2 registers ------------------------------------------------------ */
|
||||
|
||||
/* CCU2 power mode register */
|
||||
#define CCU2_PM (CCU2_BASE + 0x000)
|
||||
#define CCU2_PM MMIO32(CCU2_BASE + 0x000)
|
||||
|
||||
/* CCU2 base clocks status register */
|
||||
#define CCU2_BASE_STAT (CCU2_BASE + 0x004)
|
||||
#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)
|
||||
|
||||
/* CLK_APLL configuration register */
|
||||
#define CCU2_CLK_APLL_CFG (CCU2_BASE + 0x100)
|
||||
#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)
|
||||
|
||||
/* CLK_APLL status register */
|
||||
#define CCU2_CLK_APLL_STAT (CCU2_BASE + 0x104)
|
||||
#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)
|
||||
|
||||
/* CLK_APB2_UART3 configuration register */
|
||||
#define CCU2_CLK_APB2_USART3_CFG (CCU2_BASE + 0x200)
|
||||
#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)
|
||||
|
||||
/* CLK_APB2_UART3 status register */
|
||||
#define CCU2_CLK_APB2_USART3_STAT (CCU2_BASE + 0x204)
|
||||
#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)
|
||||
|
||||
/* CLK_APB2_UART2 configuration register */
|
||||
#define CCU2_CLK_APB2_USART2_CFG (CCU2_BASE + 0x300)
|
||||
#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)
|
||||
|
||||
/* CLK_APB2_UART2 status register */
|
||||
#define CCU2_CLK_APB2_USART2_STAT (CCU2_BASE + 0x304)
|
||||
#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)
|
||||
|
||||
/* CLK_APB0_UART1 configuration register */
|
||||
#define CCU2_CLK_APB0_UART1_CFG (CCU2_BASE + 0x400)
|
||||
#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)
|
||||
|
||||
/* CLK_APB0_UART1 status register */
|
||||
#define CCU2_CLK_APB0_UART1_STAT (CCU2_BASE + 0x404)
|
||||
#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)
|
||||
|
||||
/* CLK_APB0_UART0 configuration register */
|
||||
#define CCU2_CLK_APB0_USART0_CFG (CCU2_BASE + 0x500)
|
||||
#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)
|
||||
|
||||
/* CLK_APB0_UART0 status register */
|
||||
#define CCU2_CLK_APB0_USART0_STAT (CCU2_BASE + 0x504)
|
||||
#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)
|
||||
|
||||
/* CLK_APB2_SSP1 configuration register */
|
||||
#define CCU2_CLK_APB2_SSP1_CFG (CCU2_BASE + 0x600)
|
||||
#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)
|
||||
|
||||
/* CLK_APB2_SSP1 status register */
|
||||
#define CCU2_CLK_APB2_SSP1_STAT (CCU2_BASE + 0x604)
|
||||
#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)
|
||||
|
||||
/* CLK_APB0_SSP0 configuration register */
|
||||
#define CCU2_CLK_APB0_SSP0_CFG (CCU2_BASE + 0x700)
|
||||
#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)
|
||||
|
||||
/* CLK_APB0_SSP0 status register */
|
||||
#define CCU2_CLK_APB0_SSP0_STAT (CCU2_BASE + 0x704)
|
||||
#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)
|
||||
|
||||
/* CLK_SDIO configuration register (for SD/MMC) */
|
||||
#define CCU2_CLK_SDIO_CFG (CCU2_BASE + 0x800)
|
||||
#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)
|
||||
|
||||
/* CLK_SDIO status register (for SD/MMC) */
|
||||
#define CCU2_CLK_SDIO_STAT (CCU2_BASE + 0x804)
|
||||
#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -26,141 +26,141 @@
|
|||
/* --- CGU registers ------------------------------------------------------- */
|
||||
|
||||
/* Frequency monitor register */
|
||||
#define CGU_FREQ_MON (CGU_BASE + 0x014)
|
||||
#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)
|
||||
|
||||
/* Crystal oscillator control register */
|
||||
#define CGU_XTAL_OSC_CTRL (CGU_BASE + 0x018)
|
||||
#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)
|
||||
|
||||
/* PLL0USB status register */
|
||||
#define CGU_PLL0USB_STAT (CGU_BASE + 0x01C)
|
||||
#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)
|
||||
|
||||
/* PLL0USB control register */
|
||||
#define CGU_PLL0USB_CTRL (CGU_BASE + 0x020)
|
||||
#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)
|
||||
|
||||
/* PLL0USB M-divider register */
|
||||
#define CGU_PLL0USB_MDIV (CGU_BASE + 0x024)
|
||||
#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)
|
||||
|
||||
/* PLL0USB N/P-divider register */
|
||||
#define PLL0USB_NP_DIV (CGU_BASE + 0x028)
|
||||
#define PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
|
||||
|
||||
/* PLL0AUDIO status register */
|
||||
#define PLL0AUDIO_STAT (CGU_BASE + 0x02C)
|
||||
#define PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
|
||||
|
||||
/* PLL0AUDIO control register */
|
||||
#define PLL0AUDIO_CTRL (CGU_BASE + 0x030)
|
||||
#define PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
|
||||
|
||||
/* PLL0AUDIO M-divider register */
|
||||
#define PLL0AUDIO_MDIV (CGU_BASE + 0x034)
|
||||
#define PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
|
||||
|
||||
/* PLL0AUDIO N/P-divider register */
|
||||
#define PLL0AUDIO_NP_DIV (CGU_BASE + 0x038)
|
||||
#define PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
|
||||
|
||||
/* PLL0AUDIO fractional divider register */
|
||||
#define PLLAUDIO_FRAC (CGU_BASE + 0x03C)
|
||||
#define PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
|
||||
|
||||
/* PLL1 status register */
|
||||
#define PLL1_STAT (CGU_BASE + 0x040)
|
||||
#define PLL1_STAT MMIO32(CGU_BASE + 0x040)
|
||||
|
||||
/* PLL1 control register */
|
||||
#define PLL1_CTRL (CGU_BASE + 0x044)
|
||||
#define PLL1_CTRL MMIO32(CGU_BASE + 0x044)
|
||||
|
||||
/* Integer divider A control register */
|
||||
#define IDIVA_CTRL (CGU_BASE + 0x048)
|
||||
#define IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
|
||||
|
||||
/* Integer divider B control register */
|
||||
#define IDIVB_CTRL (CGU_BASE + 0x04C)
|
||||
#define IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
|
||||
|
||||
/* Integer divider C control register */
|
||||
#define IDIVC_CTRL (CGU_BASE + 0x050)
|
||||
#define IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
|
||||
|
||||
/* Integer divider D control register */
|
||||
#define IDIVD_CTRL (CGU_BASE + 0x054)
|
||||
#define IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
|
||||
|
||||
/* Integer divider E control register */
|
||||
#define IDIVE_CTRL (CGU_BASE + 0x058)
|
||||
#define IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
|
||||
|
||||
/* Output stage 0 control register */
|
||||
#define BASE_SAFE_CLK (CGU_BASE + 0x05C)
|
||||
#define BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
|
||||
|
||||
/* Output stage 1 control register for base clock */
|
||||
#define BASE_USB0_CLK (CGU_BASE + 0x060)
|
||||
#define BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
|
||||
|
||||
/* Output stage 2 control register for base clock */
|
||||
#define BASE_PERIPH_CLK (CGU_BASE + 0x064)
|
||||
#define BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
|
||||
|
||||
/* Output stage 3 control register for base clock */
|
||||
#define BASE_USB1_CLK (CGU_BASE + 0x068)
|
||||
#define BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
|
||||
|
||||
/* Output stage 4 control register for base clock */
|
||||
#define BASE_M4_CLK (CGU_BASE + 0x06C)
|
||||
#define BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
|
||||
|
||||
/* Output stage 5 control register for base clock */
|
||||
#define BASE_SPIFI_CLK (CGU_BASE + 0x070)
|
||||
#define BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
|
||||
|
||||
/* Output stage 6 control register for base clock */
|
||||
#define BASE_SPI_CLK (CGU_BASE + 0x074)
|
||||
#define BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
|
||||
|
||||
/* Output stage 7 control register for base clock */
|
||||
#define BASE_PHY_RX_CLK (CGU_BASE + 0x078)
|
||||
#define BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
|
||||
|
||||
/* Output stage 8 control register for base clock */
|
||||
#define BASE_PHY_TX_CLK (CGU_BASE + 0x07C)
|
||||
#define BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
|
||||
|
||||
/* Output stage 9 control register for base clock */
|
||||
#define BASE_APB1_CLK (CGU_BASE + 0x080)
|
||||
#define BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
|
||||
|
||||
/* Output stage 10 control register for base clock */
|
||||
#define BASE_APB3_CLK (CGU_BASE + 0x084)
|
||||
#define BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
|
||||
|
||||
/* Output stage 11 control register for base clock */
|
||||
#define BASE_LCD_CLK (CGU_BASE + 0x088)
|
||||
#define BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
|
||||
|
||||
/* Output stage 12 control register for base clock */
|
||||
#define BASE_VADC_CLK (CGU_BASE + 0x08C)
|
||||
#define BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
|
||||
|
||||
/* Output stage 13 control register for base clock */
|
||||
#define BASE_SDIO_CLK (CGU_BASE + 0x090)
|
||||
#define BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
|
||||
|
||||
/* Output stage 14 control register for base clock */
|
||||
#define BASE_SSP0_CLK (CGU_BASE + 0x094)
|
||||
#define BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
|
||||
|
||||
/* Output stage 15 control register for base clock */
|
||||
#define BASE_SSP1_CLK (CGU_BASE + 0x098)
|
||||
#define BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
|
||||
|
||||
/* Output stage 16 control register for base clock */
|
||||
#define BASE_UART0_CLK (CGU_BASE + 0x09C)
|
||||
#define BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
|
||||
|
||||
/* Output stage 17 control register for base clock */
|
||||
#define BASE_UART1_CLK (CGU_BASE + 0x0A0)
|
||||
#define BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
|
||||
|
||||
/* Output stage 18 control register for base clock */
|
||||
#define BASE_UART2_CLK (CGU_BASE + 0x0A4)
|
||||
#define BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
|
||||
|
||||
/* Output stage 19 control register for base clock */
|
||||
#define BASE_UART3_CLK (CGU_BASE + 0x0A8)
|
||||
#define BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
|
||||
|
||||
/* Output stage 20 control register for base clock */
|
||||
#define BASE_OUT_CLK (CGU_BASE + 0x0AC)
|
||||
#define BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define OUTCLK_21_CTRL (CGU_BASE + 0x0B0)
|
||||
#define OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define OUTCLK_22_CTRL (CGU_BASE + 0x0B4)
|
||||
#define OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define OUTCLK_23_CTRL (CGU_BASE + 0x0B8)
|
||||
#define OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define OUTCLK_24_CTRL (CGU_BASE + 0x0BC)
|
||||
#define OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
|
||||
|
||||
/* Output stage 25 control register for base clock */
|
||||
#define BASE_APLL_CLK (CGU_BASE + 0x0C0)
|
||||
#define BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
|
||||
|
||||
/* Output stage 26 control CLK register for base clock */
|
||||
#define BASE_CGU_OUT0_CLK (CGU_BASE + 0x0C4)
|
||||
#define BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
|
||||
|
||||
/* Output stage 27 control CLK register for base clock */
|
||||
#define BASE_CGU_OUT1_CLK (CGU_BASE + 0x0C8)
|
||||
#define BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -29,48 +29,48 @@
|
|||
* Chip configuration register 32 kHz oscillator output and BOD control
|
||||
* register
|
||||
*/
|
||||
#define CREG0 (CREG_BASE + 0x004)
|
||||
#define CREG0 MMIO32(CREG_BASE + 0x004)
|
||||
|
||||
/* ARM Cortex-M4 memory mapping */
|
||||
#define M4MEMMAP (CREG_BASE + 0x100)
|
||||
#define M4MEMMAP MMIO32(CREG_BASE + 0x100)
|
||||
|
||||
/* Chip configuration register 1 */
|
||||
#define CREG1 (CREG_BASE + 0x108)
|
||||
#define CREG1 MMIO32(CREG_BASE + 0x108)
|
||||
|
||||
/* Chip configuration register 2 */
|
||||
#define CREG2 (CREG_BASE + 0x10C)
|
||||
#define CREG2 MMIO32(CREG_BASE + 0x10C)
|
||||
|
||||
/* Chip configuration register 3 */
|
||||
#define CREG3 (CREG_BASE + 0x110)
|
||||
#define CREG3 MMIO32(CREG_BASE + 0x110)
|
||||
|
||||
/* Chip configuration register 4 */
|
||||
#define CREG4 (CREG_BASE + 0x114)
|
||||
#define CREG4 MMIO32(CREG_BASE + 0x114)
|
||||
|
||||
/* Chip configuration register 5 */
|
||||
#define CREG5 (CREG_BASE + 0x118)
|
||||
#define CREG5 MMIO32(CREG_BASE + 0x118)
|
||||
|
||||
/* DMA muxing control */
|
||||
#define DMAMUX (CREG_BASE + 0x11C)
|
||||
#define DMAMUX MMIO32(CREG_BASE + 0x11C)
|
||||
|
||||
/* ETB RAM configuration */
|
||||
#define ETBCFG (CREG_BASE + 0x128)
|
||||
#define ETBCFG MMIO32(CREG_BASE + 0x128)
|
||||
|
||||
/*
|
||||
* Chip configuration register 6. Controls multiple functions: Ethernet
|
||||
* interface, SCT output, I2S0/1 inputs, EMC clock.
|
||||
*/
|
||||
#define CREG6 (CREG_BASE + 0x12C)
|
||||
#define CREG6 MMIO32(CREG_BASE + 0x12C)
|
||||
|
||||
/* Cortex-M4 TXEV event clear */
|
||||
#define M4TXEVENT (CREG_BASE + 0x130)
|
||||
#define M4TXEVENT MMIO32(CREG_BASE + 0x130)
|
||||
|
||||
/* Part ID */
|
||||
#define CHIPID (CREG_BASE + 0x200)
|
||||
#define CHIPID MMIO32(CREG_BASE + 0x200)
|
||||
|
||||
/* Cortex-M0 TXEV event clear */
|
||||
#define M0TXEVENT (CREG_BASE + 0x400)
|
||||
#define M0TXEVENT MMIO32(CREG_BASE + 0x400)
|
||||
|
||||
/* ARM Cortex-M0 memory mapping */
|
||||
#define M0APPMEMMAP (CREG_BASE + 0x404)
|
||||
#define M0APPMEMMAP MMIO32(CREG_BASE + 0x404)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -26,219 +26,219 @@
|
|||
/* --- RGU registers ------------------------------------------------------- */
|
||||
|
||||
/* Reset control register 0 */
|
||||
#define RESET_CTRL0 (RGU_BASE + 0x100)
|
||||
#define RESET_CTRL0 MMIO32(RGU_BASE + 0x100)
|
||||
|
||||
/* Reset control register 1 */
|
||||
#define RESET_CTRL1 (RGU_BASE + 0x104)
|
||||
#define RESET_CTRL1 MMIO32(RGU_BASE + 0x104)
|
||||
|
||||
/* Reset status register 0 */
|
||||
#define RESET_STATUS0 (RGU_BASE + 0x110)
|
||||
#define RESET_STATUS0 MMIO32(RGU_BASE + 0x110)
|
||||
|
||||
/* Reset status register 1 */
|
||||
#define RESET_STATUS1 (RGU_BASE + 0x114)
|
||||
#define RESET_STATUS1 MMIO32(RGU_BASE + 0x114)
|
||||
|
||||
/* Reset status register 2 */
|
||||
#define RESET_STATUS2 (RGU_BASE + 0x118)
|
||||
#define RESET_STATUS2 MMIO32(RGU_BASE + 0x118)
|
||||
|
||||
/* Reset status register 3 */
|
||||
#define RESET_STATUS3 (RGU_BASE + 0x11C)
|
||||
#define RESET_STATUS3 MMIO32(RGU_BASE + 0x11C)
|
||||
|
||||
/* Reset active status register 0 */
|
||||
#define RESET_ACTIVE_STATUS0 (RGU_BASE + 0x150)
|
||||
#define RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150)
|
||||
|
||||
/* Reset active status register 1 */
|
||||
#define RESET_ACTIVE_STATUS1 (RGU_BASE + 0x154)
|
||||
#define RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154)
|
||||
|
||||
/* Reset external status register 0 for CORE_RST */
|
||||
#define RESET_EXT_STAT0 (RGU_BASE + 0x400)
|
||||
#define RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400)
|
||||
|
||||
/* Reset external status register 1 for PERIPH_RST */
|
||||
#define RESET_EXT_STAT1 (RGU_BASE + 0x404)
|
||||
#define RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404)
|
||||
|
||||
/* Reset external status register 2 for MASTER_RST */
|
||||
#define RESET_EXT_STAT2 (RGU_BASE + 0x408)
|
||||
#define RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT3 (RGU_BASE + 0x40C)
|
||||
#define RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C)
|
||||
|
||||
/* Reset external status register 4 for WWDT_RST */
|
||||
#define RESET_EXT_STAT4 (RGU_BASE + 0x410)
|
||||
#define RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410)
|
||||
|
||||
/* Reset external status register 5 for CREG_RST */
|
||||
#define RESET_EXT_STAT5 (RGU_BASE + 0x414)
|
||||
#define RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT6 (RGU_BASE + 0x418)
|
||||
#define RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT7 (RGU_BASE + 0x41C)
|
||||
#define RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C)
|
||||
|
||||
/* Reset external status register 8 for BUS_RST */
|
||||
#define RESET_EXT_STAT8 (RGU_BASE + 0x420)
|
||||
#define RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420)
|
||||
|
||||
/* Reset external status register 9 for SCU_RST */
|
||||
#define RESET_EXT_STAT9 (RGU_BASE + 0x424)
|
||||
#define RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT10 (RGU_BASE + 0x428)
|
||||
#define RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT11 (RGU_BASE + 0x42C)
|
||||
#define RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT12 (RGU_BASE + 0x430)
|
||||
#define RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430)
|
||||
|
||||
/* Reset external status register 13 for M4_RST */
|
||||
#define RESET_EXT_STAT13 (RGU_BASE + 0x434)
|
||||
#define RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT14 (RGU_BASE + 0x438)
|
||||
#define RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT15 (RGU_BASE + 0x43C)
|
||||
#define RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C)
|
||||
|
||||
/* Reset external status register 16 for LCD_RST */
|
||||
#define RESET_EXT_STAT16 (RGU_BASE + 0x440)
|
||||
#define RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440)
|
||||
|
||||
/* Reset external status register 17 for USB0_RST */
|
||||
#define RESET_EXT_STAT17 (RGU_BASE + 0x444)
|
||||
#define RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444)
|
||||
|
||||
/* Reset external status register 18 for USB1_RST */
|
||||
#define RESET_EXT_STAT18 (RGU_BASE + 0x448)
|
||||
#define RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448)
|
||||
|
||||
/* Reset external status register 19 for DMA_RST */
|
||||
#define RESET_EXT_STAT19 (RGU_BASE + 0x44C)
|
||||
#define RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C)
|
||||
|
||||
/* Reset external status register 20 for SDIO_RST */
|
||||
#define RESET_EXT_STAT20 (RGU_BASE + 0x450)
|
||||
#define RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450)
|
||||
|
||||
/* Reset external status register 21 for EMC_RST */
|
||||
#define RESET_EXT_STAT21 (RGU_BASE + 0x454)
|
||||
#define RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454)
|
||||
|
||||
/* Reset external status register 22 for ETHERNET_RST */
|
||||
#define RESET_EXT_STAT22 (RGU_BASE + 0x458)
|
||||
#define RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT23 (RGU_BASE + 0x45C)
|
||||
#define RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT24 (RGU_BASE + 0x460)
|
||||
#define RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT25 (RGU_BASE + 0x464)
|
||||
#define RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT26 (RGU_BASE + 0x468)
|
||||
#define RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT27 (RGU_BASE + 0x46C)
|
||||
#define RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C)
|
||||
|
||||
/* Reset external status register 28 for GPIO_RST */
|
||||
#define RESET_EXT_STAT28 (RGU_BASE + 0x470)
|
||||
#define RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT29 (RGU_BASE + 0x474)
|
||||
#define RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT30 (RGU_BASE + 0x478)
|
||||
#define RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT31 (RGU_BASE + 0x47C)
|
||||
#define RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C)
|
||||
|
||||
/* Reset external status register 32 for TIMER0_RST */
|
||||
#define RESET_EXT_STAT32 (RGU_BASE + 0x480)
|
||||
#define RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480)
|
||||
|
||||
/* Reset external status register 33 for TIMER1_RST */
|
||||
#define RESET_EXT_STAT33 (RGU_BASE + 0x484)
|
||||
#define RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484)
|
||||
|
||||
/* Reset external status register 34 for TIMER2_RST */
|
||||
#define RESET_EXT_STAT34 (RGU_BASE + 0x488)
|
||||
#define RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488)
|
||||
|
||||
/* Reset external status register 35 for TIMER3_RST */
|
||||
#define RESET_EXT_STAT35 (RGU_BASE + 0x48C)
|
||||
#define RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C)
|
||||
|
||||
/* Reset external status register 36 for RITIMER_RST */
|
||||
#define RESET_EXT_STAT36 (RGU_BASE + 0x490)
|
||||
#define RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490)
|
||||
|
||||
/* Reset external status register 37 for SCT_RST */
|
||||
#define RESET_EXT_STAT37 (RGU_BASE + 0x494)
|
||||
#define RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494)
|
||||
|
||||
/* Reset external status register 38 for MOTOCONPWM_RST */
|
||||
#define RESET_EXT_STAT38 (RGU_BASE + 0x498)
|
||||
#define RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498)
|
||||
|
||||
/* Reset external status register 39 for QEI_RST */
|
||||
#define RESET_EXT_STAT39 (RGU_BASE + 0x49C)
|
||||
#define RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C)
|
||||
|
||||
/* Reset external status register 40 for ADC0_RST */
|
||||
#define RESET_EXT_STAT40 (RGU_BASE + 0x4A0)
|
||||
#define RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0)
|
||||
|
||||
/* Reset external status register 41 for ADC1_RST */
|
||||
#define RESET_EXT_STAT41 (RGU_BASE + 0x4A4)
|
||||
#define RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4)
|
||||
|
||||
/* Reset external status register 42 for DAC_RST */
|
||||
#define RESET_EXT_STAT42 (RGU_BASE + 0x4A8)
|
||||
#define RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT43 (RGU_BASE + 0x4AC)
|
||||
#define RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC)
|
||||
|
||||
/* Reset external status register 44 for UART0_RST */
|
||||
#define RESET_EXT_STAT44 (RGU_BASE + 0x4B0)
|
||||
#define RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0)
|
||||
|
||||
/* Reset external status register 45 for UART1_RST */
|
||||
#define RESET_EXT_STAT45 (RGU_BASE + 0x4B4)
|
||||
#define RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4)
|
||||
|
||||
/* Reset external status register 46 for UART2_RST */
|
||||
#define RESET_EXT_STAT46 (RGU_BASE + 0x4B8)
|
||||
#define RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8)
|
||||
|
||||
/* Reset external status register 47 for UART3_RST */
|
||||
#define RESET_EXT_STAT47 (RGU_BASE + 0x4BC)
|
||||
#define RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC)
|
||||
|
||||
/* Reset external status register 48 for I2C0_RST */
|
||||
#define RESET_EXT_STAT48 (RGU_BASE + 0x4C0)
|
||||
#define RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0)
|
||||
|
||||
/* Reset external status register 49 for I2C1_RST */
|
||||
#define RESET_EXT_STAT49 (RGU_BASE + 0x4C4)
|
||||
#define RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4)
|
||||
|
||||
/* Reset external status register 50 for SSP0_RST */
|
||||
#define RESET_EXT_STAT50 (RGU_BASE + 0x4C8)
|
||||
#define RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8)
|
||||
|
||||
/* Reset external status register 51 for SSP1_RST */
|
||||
#define RESET_EXT_STAT51 (RGU_BASE + 0x4CC)
|
||||
#define RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC)
|
||||
|
||||
/* Reset external status register 52 for I2S_RST */
|
||||
#define RESET_EXT_STAT52 (RGU_BASE + 0x4D0)
|
||||
#define RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0)
|
||||
|
||||
/* Reset external status register 53 for SPIFI_RST */
|
||||
#define RESET_EXT_STAT53 (RGU_BASE + 0x4D4)
|
||||
#define RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4)
|
||||
|
||||
/* Reset external status register 54 for CAN1_RST */
|
||||
#define RESET_EXT_STAT54 (RGU_BASE + 0x4D8)
|
||||
#define RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8)
|
||||
|
||||
/* Reset external status register 55 for CAN0_RST */
|
||||
#define RESET_EXT_STAT55 (RGU_BASE + 0x4DC)
|
||||
#define RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC)
|
||||
|
||||
/* Reset external status register 56 for M0APP_RST */
|
||||
#define RESET_EXT_STAT56 (RGU_BASE + 0x4E0)
|
||||
#define RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0)
|
||||
|
||||
/* Reset external status register 57 for SGPIO_RST */
|
||||
#define RESET_EXT_STAT57 (RGU_BASE + 0x4E4)
|
||||
#define RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4)
|
||||
|
||||
/* Reset external status register 58 for SPI_RST */
|
||||
#define RESET_EXT_STAT58 (RGU_BASE + 0x4E8)
|
||||
#define RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT59 (RGU_BASE + 0x4EC)
|
||||
#define RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT60 (RGU_BASE + 0x4F0)
|
||||
#define RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT61 (RGU_BASE + 0x4F4)
|
||||
#define RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT62 (RGU_BASE + 0x4F8)
|
||||
#define RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT63 (RGU_BASE + 0x4FC)
|
||||
#define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -26,246 +26,246 @@
|
|||
/* --- SGPIO registers ----------------------------------------------------- */
|
||||
|
||||
/* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */
|
||||
#define SGPIO_OUT_MUX_CFG0 (SGPIO_PORT_BASE + 0x00)
|
||||
#define SGPIO_OUT_MUX_CFG1 (SGPIO_PORT_BASE + 0x04)
|
||||
#define SGPIO_OUT_MUX_CFG2 (SGPIO_PORT_BASE + 0x08)
|
||||
#define SGPIO_OUT_MUX_CFG3 (SGPIO_PORT_BASE + 0x0C)
|
||||
#define SGPIO_OUT_MUX_CFG4 (SGPIO_PORT_BASE + 0x10)
|
||||
#define SGPIO_OUT_MUX_CFG5 (SGPIO_PORT_BASE + 0x14)
|
||||
#define SGPIO_OUT_MUX_CFG6 (SGPIO_PORT_BASE + 0x18)
|
||||
#define SGPIO_OUT_MUX_CFG7 (SGPIO_PORT_BASE + 0x1C)
|
||||
#define SGPIO_OUT_MUX_CFG8 (SGPIO_PORT_BASE + 0x20)
|
||||
#define SGPIO_OUT_MUX_CFG9 (SGPIO_PORT_BASE + 0x24)
|
||||
#define SGPIO_OUT_MUX_CFG10 (SGPIO_PORT_BASE + 0x28)
|
||||
#define SGPIO_OUT_MUX_CFG11 (SGPIO_PORT_BASE + 0x2C)
|
||||
#define SGPIO_OUT_MUX_CFG12 (SGPIO_PORT_BASE + 0x30)
|
||||
#define SGPIO_OUT_MUX_CFG13 (SGPIO_PORT_BASE + 0x34)
|
||||
#define SGPIO_OUT_MUX_CFG14 (SGPIO_PORT_BASE + 0x38)
|
||||
#define SGPIO_OUT_MUX_CFG15 (SGPIO_PORT_BASE + 0x3C)
|
||||
#define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00)
|
||||
#define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04)
|
||||
#define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08)
|
||||
#define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C)
|
||||
#define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10)
|
||||
#define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14)
|
||||
#define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18)
|
||||
#define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C)
|
||||
#define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20)
|
||||
#define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24)
|
||||
#define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28)
|
||||
#define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C)
|
||||
#define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30)
|
||||
#define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34)
|
||||
#define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38)
|
||||
#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C)
|
||||
|
||||
/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */
|
||||
#define SGPIO_MUX_CFG0 (SGPIO_PORT_BASE + 0x40)
|
||||
#define SGPIO_MUX_CFG1 (SGPIO_PORT_BASE + 0x44)
|
||||
#define SGPIO_MUX_CFG2 (SGPIO_PORT_BASE + 0x48)
|
||||
#define SGPIO_MUX_CFG3 (SGPIO_PORT_BASE + 0x4C)
|
||||
#define SGPIO_MUX_CFG4 (SGPIO_PORT_BASE + 0x50)
|
||||
#define SGPIO_MUX_CFG5 (SGPIO_PORT_BASE + 0x54)
|
||||
#define SGPIO_MUX_CFG6 (SGPIO_PORT_BASE + 0x58)
|
||||
#define SGPIO_MUX_CFG7 (SGPIO_PORT_BASE + 0x5C)
|
||||
#define SGPIO_MUX_CFG8 (SGPIO_PORT_BASE + 0x60)
|
||||
#define SGPIO_MUX_CFG9 (SGPIO_PORT_BASE + 0x64)
|
||||
#define SGPIO_MUX_CFG10 (SGPIO_PORT_BASE + 0x68)
|
||||
#define SGPIO_MUX_CFG11 (SGPIO_PORT_BASE + 0x6C)
|
||||
#define SGPIO_MUX_CFG12 (SGPIO_PORT_BASE + 0x70)
|
||||
#define SGPIO_MUX_CFG13 (SGPIO_PORT_BASE + 0x74)
|
||||
#define SGPIO_MUX_CFG14 (SGPIO_PORT_BASE + 0x78)
|
||||
#define SGPIO_MUX_CFG15 (SGPIO_PORT_BASE + 0x7C)
|
||||
#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40)
|
||||
#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44)
|
||||
#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48)
|
||||
#define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C)
|
||||
#define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50)
|
||||
#define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54)
|
||||
#define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58)
|
||||
#define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C)
|
||||
#define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60)
|
||||
#define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64)
|
||||
#define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68)
|
||||
#define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C)
|
||||
#define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70)
|
||||
#define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74)
|
||||
#define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78)
|
||||
#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C)
|
||||
|
||||
/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */
|
||||
#define SGPIO_SLICE_MUX_CFG0 (SGPIO_PORT_BASE + 0x80)
|
||||
#define SGPIO_SLICE_MUX_CFG1 (SGPIO_PORT_BASE + 0x84)
|
||||
#define SGPIO_SLICE_MUX_CFG2 (SGPIO_PORT_BASE + 0x88)
|
||||
#define SGPIO_SLICE_MUX_CFG3 (SGPIO_PORT_BASE + 0x8C)
|
||||
#define SGPIO_SLICE_MUX_CFG4 (SGPIO_PORT_BASE + 0x90)
|
||||
#define SGPIO_SLICE_MUX_CFG5 (SGPIO_PORT_BASE + 0x94)
|
||||
#define SGPIO_SLICE_MUX_CFG6 (SGPIO_PORT_BASE + 0x98)
|
||||
#define SGPIO_SLICE_MUX_CFG7 (SGPIO_PORT_BASE + 0x9C)
|
||||
#define SGPIO_SLICE_MUX_CFG8 (SGPIO_PORT_BASE + 0xA0)
|
||||
#define SGPIO_SLICE_MUX_CFG9 (SGPIO_PORT_BASE + 0xA4)
|
||||
#define SGPIO_SLICE_MUX_CFG10 (SGPIO_PORT_BASE + 0xA8)
|
||||
#define SGPIO_SLICE_MUX_CFG11 (SGPIO_PORT_BASE + 0xAC)
|
||||
#define SGPIO_SLICE_MUX_CFG12 (SGPIO_PORT_BASE + 0xB0)
|
||||
#define SGPIO_SLICE_MUX_CFG13 (SGPIO_PORT_BASE + 0xB4)
|
||||
#define SGPIO_SLICE_MUX_CFG14 (SGPIO_PORT_BASE + 0xB8)
|
||||
#define SGPIO_SLICE_MUX_CFG15 (SGPIO_PORT_BASE + 0xBC)
|
||||
#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80)
|
||||
#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84)
|
||||
#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88)
|
||||
#define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C)
|
||||
#define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90)
|
||||
#define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94)
|
||||
#define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98)
|
||||
#define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C)
|
||||
#define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0)
|
||||
#define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4)
|
||||
#define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8)
|
||||
#define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC)
|
||||
#define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0)
|
||||
#define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4)
|
||||
#define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8)
|
||||
#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC)
|
||||
|
||||
/* Slice data registers (REG0 to 15) */
|
||||
#define SGPIO_REG0 (SGPIO_PORT_BASE + 0xC0)
|
||||
#define SGPIO_REG1 (SGPIO_PORT_BASE + 0xC4)
|
||||
#define SGPIO_REG2 (SGPIO_PORT_BASE + 0xC8)
|
||||
#define SGPIO_REG3 (SGPIO_PORT_BASE + 0xCC)
|
||||
#define SGPIO_REG4 (SGPIO_PORT_BASE + 0xD0)
|
||||
#define SGPIO_REG5 (SGPIO_PORT_BASE + 0xD4)
|
||||
#define SGPIO_REG6 (SGPIO_PORT_BASE + 0xD8)
|
||||
#define SGPIO_REG7 (SGPIO_PORT_BASE + 0xDC)
|
||||
#define SGPIO_REG8 (SGPIO_PORT_BASE + 0xE0)
|
||||
#define SGPIO_REG9 (SGPIO_PORT_BASE + 0xE4)
|
||||
#define SGPIO_REG10 (SGPIO_PORT_BASE + 0xE8)
|
||||
#define SGPIO_REG11 (SGPIO_PORT_BASE + 0xEC)
|
||||
#define SGPIO_REG12 (SGPIO_PORT_BASE + 0xF0)
|
||||
#define SGPIO_REG13 (SGPIO_PORT_BASE + 0xF4)
|
||||
#define SGPIO_REG14 (SGPIO_PORT_BASE + 0xF8)
|
||||
#define SGPIO_REG15 (SGPIO_PORT_BASE + 0xFC)
|
||||
#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0)
|
||||
#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4)
|
||||
#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8)
|
||||
#define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC)
|
||||
#define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0)
|
||||
#define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4)
|
||||
#define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8)
|
||||
#define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC)
|
||||
#define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0)
|
||||
#define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4)
|
||||
#define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8)
|
||||
#define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC)
|
||||
#define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0)
|
||||
#define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4)
|
||||
#define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8)
|
||||
#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC)
|
||||
|
||||
/* Slice data shadow registers (REG_SS0 to 15) */
|
||||
#define SGPIO_REG_SS0 (SGPIO_PORT_BASE + 0x100)
|
||||
#define SGPIO_REG_SS1 (SGPIO_PORT_BASE + 0x104)
|
||||
#define SGPIO_REG_SS2 (SGPIO_PORT_BASE + 0x108)
|
||||
#define SGPIO_REG_SS3 (SGPIO_PORT_BASE + 0x10C)
|
||||
#define SGPIO_REG_SS4 (SGPIO_PORT_BASE + 0x110)
|
||||
#define SGPIO_REG_SS5 (SGPIO_PORT_BASE + 0x114)
|
||||
#define SGPIO_REG_SS6 (SGPIO_PORT_BASE + 0x118)
|
||||
#define SGPIO_REG_SS7 (SGPIO_PORT_BASE + 0x11C)
|
||||
#define SGPIO_REG_SS8 (SGPIO_PORT_BASE + 0x120)
|
||||
#define SGPIO_REG_SS9 (SGPIO_PORT_BASE + 0x124)
|
||||
#define SGPIO_REG_SS10 (SGPIO_PORT_BASE + 0x128)
|
||||
#define SGPIO_REG_SS11 (SGPIO_PORT_BASE + 0x12C)
|
||||
#define SGPIO_REG_SS12 (SGPIO_PORT_BASE + 0x130)
|
||||
#define SGPIO_REG_SS13 (SGPIO_PORT_BASE + 0x134)
|
||||
#define SGPIO_REG_SS14 (SGPIO_PORT_BASE + 0x138)
|
||||
#define SGPIO_REG_SS15 (SGPIO_PORT_BASE + 0x13C)
|
||||
#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100)
|
||||
#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104)
|
||||
#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108)
|
||||
#define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C)
|
||||
#define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110)
|
||||
#define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114)
|
||||
#define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118)
|
||||
#define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C)
|
||||
#define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120)
|
||||
#define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124)
|
||||
#define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128)
|
||||
#define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C)
|
||||
#define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130)
|
||||
#define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134)
|
||||
#define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138)
|
||||
#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C)
|
||||
|
||||
/* Reload registers (PRESET0 to 15) */
|
||||
#define SGPIO_PRESET0 (SGPIO_PORT_BASE + 0x140)
|
||||
#define SGPIO_PRESET1 (SGPIO_PORT_BASE + 0x144)
|
||||
#define SGPIO_PRESET2 (SGPIO_PORT_BASE + 0x148)
|
||||
#define SGPIO_PRESET3 (SGPIO_PORT_BASE + 0x14C)
|
||||
#define SGPIO_PRESET4 (SGPIO_PORT_BASE + 0x150)
|
||||
#define SGPIO_PRESET5 (SGPIO_PORT_BASE + 0x154)
|
||||
#define SGPIO_PRESET6 (SGPIO_PORT_BASE + 0x158)
|
||||
#define SGPIO_PRESET7 (SGPIO_PORT_BASE + 0x15C)
|
||||
#define SGPIO_PRESET8 (SGPIO_PORT_BASE + 0x160)
|
||||
#define SGPIO_PRESET9 (SGPIO_PORT_BASE + 0x164)
|
||||
#define SGPIO_PRESET10 (SGPIO_PORT_BASE + 0x168)
|
||||
#define SGPIO_PRESET11 (SGPIO_PORT_BASE + 0x16C)
|
||||
#define SGPIO_PRESET12 (SGPIO_PORT_BASE + 0x170)
|
||||
#define SGPIO_PRESET13 (SGPIO_PORT_BASE + 0x174)
|
||||
#define SGPIO_PRESET14 (SGPIO_PORT_BASE + 0x178)
|
||||
#define SGPIO_PRESET15 (SGPIO_PORT_BASE + 0x17C)
|
||||
#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140)
|
||||
#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144)
|
||||
#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148)
|
||||
#define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C)
|
||||
#define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150)
|
||||
#define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154)
|
||||
#define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158)
|
||||
#define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C)
|
||||
#define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160)
|
||||
#define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164)
|
||||
#define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168)
|
||||
#define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C)
|
||||
#define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170)
|
||||
#define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174)
|
||||
#define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178)
|
||||
#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C)
|
||||
|
||||
/* Down counter registers (COUNT0 to 15) */
|
||||
#define SGPIO_COUNT0 (SGPIO_PORT_BASE + 0x180)
|
||||
#define SGPIO_COUNT1 (SGPIO_PORT_BASE + 0x184)
|
||||
#define SGPIO_COUNT2 (SGPIO_PORT_BASE + 0x188)
|
||||
#define SGPIO_COUNT3 (SGPIO_PORT_BASE + 0x18C)
|
||||
#define SGPIO_COUNT4 (SGPIO_PORT_BASE + 0x190)
|
||||
#define SGPIO_COUNT5 (SGPIO_PORT_BASE + 0x194)
|
||||
#define SGPIO_COUNT6 (SGPIO_PORT_BASE + 0x198)
|
||||
#define SGPIO_COUNT7 (SGPIO_PORT_BASE + 0x19C)
|
||||
#define SGPIO_COUNT8 (SGPIO_PORT_BASE + 0x1A0)
|
||||
#define SGPIO_COUNT9 (SGPIO_PORT_BASE + 0x1A4)
|
||||
#define SGPIO_COUNT10 (SGPIO_PORT_BASE + 0x1A8)
|
||||
#define SGPIO_COUNT11 (SGPIO_PORT_BASE + 0x1AC)
|
||||
#define SGPIO_COUNT12 (SGPIO_PORT_BASE + 0x1B0)
|
||||
#define SGPIO_COUNT13 (SGPIO_PORT_BASE + 0x1B4)
|
||||
#define SGPIO_COUNT14 (SGPIO_PORT_BASE + 0x1B8)
|
||||
#define SGPIO_COUNT15 (SGPIO_PORT_BASE + 0x1BC)
|
||||
#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180)
|
||||
#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184)
|
||||
#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188)
|
||||
#define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C)
|
||||
#define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190)
|
||||
#define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194)
|
||||
#define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198)
|
||||
#define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C)
|
||||
#define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0)
|
||||
#define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4)
|
||||
#define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8)
|
||||
#define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC)
|
||||
#define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0)
|
||||
#define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4)
|
||||
#define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8)
|
||||
#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC)
|
||||
|
||||
/* Position registers (POS0 to 15) */
|
||||
#define SGPIO_POS0 (SGPIO_PORT_BASE + 0x1C0)
|
||||
#define SGPIO_POS1 (SGPIO_PORT_BASE + 0x1C4)
|
||||
#define SGPIO_POS2 (SGPIO_PORT_BASE + 0x1C8)
|
||||
#define SGPIO_POS3 (SGPIO_PORT_BASE + 0x1CC)
|
||||
#define SGPIO_POS4 (SGPIO_PORT_BASE + 0x1D0)
|
||||
#define SGPIO_POS5 (SGPIO_PORT_BASE + 0x1D4)
|
||||
#define SGPIO_POS6 (SGPIO_PORT_BASE + 0x1D8)
|
||||
#define SGPIO_POS7 (SGPIO_PORT_BASE + 0x1DC)
|
||||
#define SGPIO_POS8 (SGPIO_PORT_BASE + 0x1E0)
|
||||
#define SGPIO_POS9 (SGPIO_PORT_BASE + 0x1E4)
|
||||
#define SGPIO_POS10 (SGPIO_PORT_BASE + 0x1E8)
|
||||
#define SGPIO_POS11 (SGPIO_PORT_BASE + 0x1EC)
|
||||
#define SGPIO_POS12 (SGPIO_PORT_BASE + 0x1F0)
|
||||
#define SGPIO_POS13 (SGPIO_PORT_BASE + 0x1F4)
|
||||
#define SGPIO_POS14 (SGPIO_PORT_BASE + 0x1F8)
|
||||
#define SGPIO_POS15 (SGPIO_PORT_BASE + 0x1FC)
|
||||
#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0)
|
||||
#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4)
|
||||
#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8)
|
||||
#define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC)
|
||||
#define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0)
|
||||
#define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4)
|
||||
#define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8)
|
||||
#define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC)
|
||||
#define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0)
|
||||
#define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4)
|
||||
#define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8)
|
||||
#define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC)
|
||||
#define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0)
|
||||
#define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4)
|
||||
#define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8)
|
||||
#define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC)
|
||||
|
||||
/* Mask for pattern match function of slice A */
|
||||
#define SGPIO_MASK_A (SGPIO_PORT_BASE + 0x200)
|
||||
#define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200)
|
||||
|
||||
/* Mask for pattern match function of slice H */
|
||||
#define SGPIO_MASK_H (SGPIO_PORT_BASE + 0x204)
|
||||
#define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204)
|
||||
|
||||
/* Mask for pattern match function of slice I */
|
||||
#define SGPIO_MASK_I (SGPIO_PORT_BASE + 0x208)
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||||
#define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208)
|
||||
|
||||
/* Mask for pattern match function of slice P */
|
||||
#define SGPIO_MASK_P (SGPIO_PORT_BASE + 0x20C)
|
||||
#define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C)
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||||
|
||||
/* GPIO input status register */
|
||||
#define SGPIO_GPIO_INREG (SGPIO_PORT_BASE + 0x210)
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||||
#define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210)
|
||||
|
||||
/* GPIO output control register */
|
||||
#define SGPIO_GPIO_OUTREG (SGPIO_PORT_BASE + 0x214)
|
||||
#define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214)
|
||||
|
||||
/* GPIO OE control register */
|
||||
#define SGPIO_GPIO_OENREG (SGPIO_PORT_BASE + 0x218)
|
||||
#define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218)
|
||||
|
||||
/* Enables the slice COUNT counter */
|
||||
#define SGPIO_CTRL_ENABLE (SGPIO_PORT_BASE + 0x21C)
|
||||
#define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C)
|
||||
|
||||
/* Disables the slice COUNT counter */
|
||||
#define SGPIO_CTRL_DISABLE (SGPIO_PORT_BASE + 0x220)
|
||||
#define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220)
|
||||
|
||||
/* Shift clock interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_0 (SGPIO_PORT_BASE + 0xF00)
|
||||
#define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00)
|
||||
|
||||
/* Shift clock interrupt set mask */
|
||||
#define SGPIO_SET_EN_0 (SGPIO_PORT_BASE + 0xF04)
|
||||
#define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04)
|
||||
|
||||
/* Shift clock interrupt enable */
|
||||
#define SGPIO_ENABLE_0 (SGPIO_PORT_BASE + 0xF08)
|
||||
#define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08)
|
||||
|
||||
/* Shift clock interrupt status */
|
||||
#define SGPIO_STATUS_0 (SGPIO_PORT_BASE + 0xF0C)
|
||||
#define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C)
|
||||
|
||||
/* Shift clock interrupt clear status */
|
||||
#define SGPIO_CTR_STAT_0 (SGPIO_PORT_BASE + 0xF10)
|
||||
#define SGPIO_CTR_STAT_0 MMIO32(SGPIO_PORT_BASE + 0xF10)
|
||||
|
||||
/* Shift clock interrupt set status */
|
||||
#define SGPIO_SET_STAT_0 (SGPIO_PORT_BASE + 0xF14)
|
||||
#define SGPIO_SET_STAT_0 MMIO32(SGPIO_PORT_BASE + 0xF14)
|
||||
|
||||
/* Capture clock interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_1 (SGPIO_PORT_BASE + 0xF20)
|
||||
#define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20)
|
||||
|
||||
/* Capture clock interrupt set mask */
|
||||
#define SGPIO_SET_EN_1 (SGPIO_PORT_BASE + 0xF24)
|
||||
#define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24)
|
||||
|
||||
/* Capture clock interrupt enable */
|
||||
#define SGPIO_ENABLE_1 (SGPIO_PORT_BASE + 0xF28)
|
||||
#define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28)
|
||||
|
||||
/* Capture clock interrupt status */
|
||||
#define SGPIO_STATUS_1 (SGPIO_PORT_BASE + 0xF2C)
|
||||
#define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C)
|
||||
|
||||
/* Capture clock interrupt clear status */
|
||||
#define SGPIO_CTR_STAT_1 (SGPIO_PORT_BASE + 0xF30)
|
||||
#define SGPIO_CTR_STAT_1 MMIO32(SGPIO_PORT_BASE + 0xF30)
|
||||
|
||||
/* Capture clock interrupt set status */
|
||||
#define SGPIO_SET_STAT_1 (SGPIO_PORT_BASE + 0xF34)
|
||||
#define SGPIO_SET_STAT_1 MMIO32(SGPIO_PORT_BASE + 0xF34)
|
||||
|
||||
/* Pattern match interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_2 (SGPIO_PORT_BASE + 0xF40)
|
||||
#define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40)
|
||||
|
||||
/* Pattern match interrupt set mask */
|
||||
#define SGPIO_SET_EN_2 (SGPIO_PORT_BASE + 0xF44)
|
||||
#define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44)
|
||||
|
||||
/* Pattern match interrupt enable */
|
||||
#define SGPIO_ENABLE_2 (SGPIO_PORT_BASE + 0xF48)
|
||||
#define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48)
|
||||
|
||||
/* Pattern match interrupt status */
|
||||
#define SGPIO_STATUS_2 (SGPIO_PORT_BASE + 0xF4C)
|
||||
#define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C)
|
||||
|
||||
/* Pattern match interrupt clear status */
|
||||
#define SGPIO_CTR_STAT_2 (SGPIO_PORT_BASE + 0xF50)
|
||||
#define SGPIO_CTR_STAT_2 MMIO32(SGPIO_PORT_BASE + 0xF50)
|
||||
|
||||
/* Pattern match interrupt set status */
|
||||
#define SGPIO_SET_STAT_2 (SGPIO_PORT_BASE + 0xF54)
|
||||
#define SGPIO_SET_STAT_2 MMIO32(SGPIO_PORT_BASE + 0xF54)
|
||||
|
||||
/* Input interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_3 (SGPIO_PORT_BASE + 0xF60)
|
||||
#define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60)
|
||||
|
||||
/* Input bit match interrupt set mask */
|
||||
#define SGPIO_SET_EN_3 (SGPIO_PORT_BASE + 0xF64)
|
||||
#define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64)
|
||||
|
||||
/* Input bit match interrupt enable */
|
||||
#define SGPIO_ENABLE_3 (SGPIO_PORT_BASE + 0xF68)
|
||||
#define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68)
|
||||
|
||||
/* Input bit match interrupt status */
|
||||
#define SGPIO_STATUS_3 (SGPIO_PORT_BASE + 0xF6C)
|
||||
#define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C)
|
||||
|
||||
/* Input bit match interrupt clear status */
|
||||
#define SGPIO_CTR_STAT_3 (SGPIO_PORT_BASE + 0xF70)
|
||||
#define SGPIO_CTR_STAT_3 MMIO32(SGPIO_PORT_BASE + 0xF70)
|
||||
|
||||
/* Input bit match interrupt set status */
|
||||
#define SGPIO_SET_STAT_3 (SGPIO_PORT_BASE + 0xF74)
|
||||
#define SGPIO_SET_STAT_3 MMIO32(SGPIO_PORT_BASE + 0xF74)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue