stm32: dac: doxygenize the registers and values
Not 100% complete, but far closer, mostly just tagging the existing information properly to get it included.
This commit is contained in:
Karl Palsson
parent
03cfd6b1ac
commit
4fe5103851
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@ -39,45 +39,46 @@ specific memorymap.h header before including this header file.*/
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#ifndef LIBOPENCM3_DAC_COMMON_ALL_H
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#define LIBOPENCM3_DAC_COMMON_ALL_H
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/* --- DAC registers ------------------------------------------------------- */
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/**@defgroup dac_registers DAC Registers
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@{*/
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/* DAC control register (DAC_CR) */
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/** DAC control register (DAC_CR) */
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#define DAC_CR(dac) MMIO32((dac) + 0x00)
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/* DAC software trigger register (DAC_SWTRIGR) */
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/** DAC software trigger register (DAC_SWTRIGR) */
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#define DAC_SWTRIGR(dac) MMIO32((dac) + 0x04)
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/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
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/** DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
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#define DAC_DHR12R1(dac) MMIO32((dac) + 0x08)
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/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
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/** DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
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#define DAC_DHR12L1(dac) MMIO32((dac) + 0x0C)
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/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
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/** DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
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#define DAC_DHR8R1(dac) MMIO32((dac) + 0x10)
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/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
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/** DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
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#define DAC_DHR12R2(dac) MMIO32((dac) + 0x14)
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/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
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/** DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
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#define DAC_DHR12L2(dac) MMIO32((dac) + 0x18)
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/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
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/** DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
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#define DAC_DHR8R2(dac) MMIO32((dac) + 0x1C)
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/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
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/** Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
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#define DAC_DHR12RD(dac) MMIO32((dac) + 0x20)
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/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
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/** DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
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#define DAC_DHR12LD(dac) MMIO32((dac) + 0x24)
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/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
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/** DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
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#define DAC_DHR8RD(dac) MMIO32((dac) + 0x28)
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/* DAC channel1 data output register (DAC_DOR1) */
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/** DAC channel1 data output register (DAC_DOR1) */
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#define DAC_DOR1(dac) MMIO32((dac) + 0x2C)
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/* DAC channel2 data output register (DAC_DOR2) */
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/** DAC channel2 data output register (DAC_DOR2) */
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#define DAC_DOR2(dac) MMIO32((dac) + 0x30)
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/** DAC status register.
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@ -85,52 +86,63 @@ specific memorymap.h header before including this header file.*/
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*/
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#define DAC_SR(dac) MMIO32((dac) + 0x34)
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/* --- DAC_CR values ------------------------------------------------------- */
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/**@}*/
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/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
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/* doesn't exist in most members of the STM32F1 family */
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/** @defgroup dac_cr_values DAC_CR values
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* @{
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*/
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/** DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
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* @note doesn't exist in most members of the STM32F1 family
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*/
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#define DAC_CR_DMAUDRIE2 (1 << 29)
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/* DMAEN2: DAC channel2 DMA enable */
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/** DMAEN2: DAC channel2 DMA enable */
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#define DAC_CR_DMAEN2 (1 << 28)
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/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
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/** MAMP2[3:0]: DAC channel2 mask/amplitude selector */
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#define DAC_CR_MAMP2_SHIFT 24
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/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
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/** WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
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#define DAC_CR_WAVE2_SHIFT 22
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#define DAC_CR_WAVE2_MASK 0x3
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/* EN2: DAC channel2 enable */
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/** EN2: DAC channel2 enable */
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#define DAC_CR_EN2 (1 << 16)
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/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
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/* doesn't exist in most members of the STM32F1 family */
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/** DMAUDRIE1: DAC channel1 DMA underrun interrupt enable
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* @note doesn't exist in most members of the STM32F1 family
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*/
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#define DAC_CR_DMAUDRIE1 (1 << 13)
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/* DMAEN1: DAC channel1 DMA enable */
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/** DMAEN1: DAC channel1 DMA enable */
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#define DAC_CR_DMAEN1 (1 << 12)
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/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
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/** MAMP1[3:0]: DAC channel1 mask/amplitude selector */
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#define DAC_CR_MAMP1_SHIFT 8
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/* WAVEn[1:0]: DAC channel1 noise/triangle wave generation enable */
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/** WAVEn[1:0]: DAC channel1 noise/triangle wave generation enable */
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#define DAC_CR_WAVE1_SHIFT 6
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#define DAC_CR_WAVE1_MASK 0x3
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/* EN1: DAC channel1 enable */
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/** EN1: DAC channel1 enable */
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#define DAC_CR_EN1 (1 << 0)
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/**@}*/
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/* --- DAC_SWTRIGR values -------------------------------------------------- */
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/* SWTRIG2: DAC channel2 software trigger */
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/**@defgroup dac_swtrigr_values DAC_SWTRIGR Values
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* @{
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*/
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/** SWTRIG2: DAC channel2 software trigger */
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#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
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/* SWTRIG1: DAC channel1 software trigger */
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/** SWTRIG1: DAC channel1 software trigger */
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#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
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/**@}*/
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/**@defgroup dac_dhrxxx_values DAC_DHRxxx Values
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* @{
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*/
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/* --- DAC_DHR12R1 values -------------------------------------------------- */
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#define DAC_DHR12R1_DACC1DHR_SHIFT 0
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#define DAC_DHR12R1_DACC1DHR_MASK 0xFFF
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@ -180,8 +192,12 @@ specific memorymap.h header before including this header file.*/
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#define DAC_DHR8RD_DACC2DHR_MSK 0xFF
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#define DAC_DHR8RD_DACC1DHR_SHIFT 0
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#define DAC_DHR8RD_DACC1DHR_MSK 0xFF
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/**@}*/
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/**@defgroup dac_dorx_values DAC_DORx Values
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* @{
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*/
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/* --- DAC_DOR1 values ----------------------------------------------------- */
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#define DAC_DOR1_DACC1DOR_SHIFT 0
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#define DAC_DOR1_DACC1DOR_MSK 0xFFF
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@ -191,20 +207,27 @@ specific memorymap.h header before including this header file.*/
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#define DAC_DOR2_DACC2DOR_SHIFT 0
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#define DAC_DOR2_DACC2DOR_MSK 0xFFF
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/* --- DAC_SR values ------------------------------------------------------- */
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/**@}*/
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/**@defgroup dac_sr_values DAC_SR Values
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* @{
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*/
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/** DAC channel 1 DMA underrun flag */
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#define DAC_SR_DMAUDR1 (1 << 13)
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/** DAC channel 2 DMA underrun flag */
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#define DAC_SR_DMAUDR2 (1 << 29)
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/**@}*/
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/* --- Function prototypes ------------------------------------------------- */
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/** DAC channel identifier */
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/** @defgroup dac_channel_id DAC Channel Identifier
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* @{
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*/
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#define DAC_CHANNEL1 (1 << 0)
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#define DAC_CHANNEL2 (1 << 1)
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#define DAC_CHANNEL_BOTH (DAC_CHANNEL1 | DAC_CHANNEL2)
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/**@}*/
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/** DAC data size (8/12 bits), alignment (right/left) */
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enum dac_align {
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@ -213,7 +236,7 @@ enum dac_align {
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DAC_ALIGN_LEFT12,
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};
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/* DAC waveform generation options. */
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/** DAC waveform generation options. */
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enum dac_wave {
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DAC_WAVE_DISABLE = 0,
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DAC_WAVE_NOISE = 1,
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@ -38,9 +38,11 @@ specific memorymap.h header before including this header file.*/
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#include <libopencm3/stm32/common/dac_common_all.h>
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/* --- DAC_CR values ------------------------------------------------------- */
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/**@addtogroup dac_cr_values
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* @{
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*/
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/* TSEL2[2:0]: DAC channel2 trigger selection */
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/** TSEL2[2:0]: DAC channel2 trigger selection */
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#define DAC_CR_TSEL2_SHIFT 19
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/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
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@ingroup dac_defines
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@ -118,6 +120,7 @@ specific memorymap.h header before including this header file.*/
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/* BOFF1: DAC channel1 output buffer disable */
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#define DAC_CR_BOFF1 (1 << 1)
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/**@}*/
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/* --- Function prototypes ------------------------------------------------- */
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@ -38,38 +38,42 @@ specific memorymap.h header before including this header file.*/
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#include <libopencm3/stm32/common/dac_common_all.h>
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/* --- DAC registers ------------------------------------------------------- */
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/**@addtogroup dac_registers
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@{*/
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/* DAC calibration control register (DAC_CCR) */
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/** DAC calibration control register (DAC_CCR) */
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#define DAC_CCR(dac) MMIO32((dac) + 0x38)
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/* DAC mode control register (DAC_MCR) */
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/** DAC mode control register (DAC_MCR) */
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#define DAC_MCR(dac) MMIO32((dac) + 0x3C)
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/* DAC channel1 sample and hold sample time register (DAC_SHSR1) */
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/** DAC channel1 sample and hold sample time register (DAC_SHSR1) */
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#define DAC_SHSR1(dac) MMIO32((dac) + 0x40)
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/* DAC channel2 sample and hold sample time register (DAC_SHSR2) */
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/** DAC channel2 sample and hold sample time register (DAC_SHSR2) */
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#define DAC_SHSR2(dac) MMIO32((dac) + 0x44)
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/* DAC sample and hold time register (DAC_SHHR) */
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/** DAC sample and hold time register (DAC_SHHR) */
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#define DAC_SHHR(dac) MMIO32((dac) + 0x48)
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/* DAC sample and hold refresh time register (DAC_SHRR) */
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/** DAC sample and hold refresh time register (DAC_SHRR) */
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#define DAC_SHRR(dac) MMIO32((dac) + 0x4C)
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/* DAC channel1 sawtooth register (DAC_STR1) */
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/** DAC channel1 sawtooth register (DAC_STR1) */
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#define DAC_STR1(dac) MMIO32((dac) + 0x58)
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/* DAC channel2 sawtooth register (DAC_STR2) */
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/** DAC channel2 sawtooth register (DAC_STR2) */
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#define DAC_STR2(dac) MMIO32((dac) + 0x5C)
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/* DAC sawtooth mode register (DAC_STMODR) */
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/** DAC sawtooth mode register (DAC_STMODR) */
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#define DAC_STMODR(dac) MMIO32((dac) + 0x60)
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/**@}*/
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/* --- DAC_CR values ------------------------------------------------------- */
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/**@addtogroup dac_cr_values
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* @{
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*/
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/* CEN2: DAC channel2 calibration enable */
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/** CEN2: DAC channel2 calibration enable */
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#define DAC_CR_CEN2 (1 << 30)
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/* TSEL2[3:0]: DAC channel2 trigger selection */
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@ -162,19 +166,24 @@ specific memorymap.h header before including this header file.*/
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#define DAC_CR_TSEL1_HR3 (0xF << DAC_CR_TSEL1_SHIFT)
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/**@}*/
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/* TEN1: DAC channel1 trigger enable */
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/** TEN1: DAC channel1 trigger enable */
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#define DAC_CR_TEN1 (1 << 1)
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/**@}*/
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/* --- DAC_SWTRIGR values -------------------------------------------------- */
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/* SWTRIG2: DAC channel2 software trigger B */
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/** @addtogroup dac_swtrigr_values
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* @{
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*/
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/** SWTRIG2: DAC channel2 software trigger B */
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#define DAC_SWTRIGR_SWTRIGB2 (1 << 17)
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/* SWTRIG1: DAC channel1 software trigger B */
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/** SWTRIG1: DAC channel1 software trigger B */
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#define DAC_SWTRIGR_SWTRIGB1 (1 << 16)
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/**@}*/
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/** @addtogroup dac_dorx_values
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* @{
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*/
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/* --- DAC_DOR1 values ----------------------------------------------------- */
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#define DAC_DOR1_DACC1DORB_SHIFT 16
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#define DAC_DOR1_DACC1DORB_MASK 0xFFF
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@ -183,41 +192,46 @@ specific memorymap.h header before including this header file.*/
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/* --- DAC_DOR2 values ----------------------------------------------------- */
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#define DAC_DOR2_DACC2DORB_SHIFT 16
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#define DAC_DOR2_DACC2DORB_MASK 0xFFF
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/**@}*/
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/* --- DAC_SR values ----------------------------------------------------- */
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/* DAC channel2 busy writing sample time flag */
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/** @addtogroup dac_sr_values
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* @{
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*/
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/** DAC channel2 busy writing sample time flag */
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#define DAC_SR_BWST2 (1 << 31)
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/* DAC channel2 calibration offset status */
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/** DAC channel2 calibration offset status */
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#define DAC_SR_CAL_FLAG2 (1 << 30)
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/** DAC channel2 DMA underrun flag */
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#define DAC_SR_DMAUDR2 (1 << 29)
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/* DAC channel2 output register status bit */
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/** DAC channel2 output register status bit */
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#define DAC_SR_DORSTAT2 (1 << 28)
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/* DAC channel2 ready status bit */
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/** DAC channel2 ready status bit */
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#define DAC_SR_DAC2RDY (1 << 27)
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/* DAC channel1 busy writing sample time flag */
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/** DAC channel1 busy writing sample time flag */
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#define DAC_SR_BWST1 (1 << 15)
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/* DAC channel1 calibration offset status */
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/** DAC channel1 calibration offset status */
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#define DAC_SR_CAL_FLAG1 (1 << 14)
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/** DAC channel1 DMA underrun flag */
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#define DAC_SR_DMAUDR1 (1 << 13)
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/* DAC channel1 output register status bit */
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/** DAC channel1 output register status bit */
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#define DAC_SR_DORSTAT1 (1 << 12)
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/* DAC channel1 ready status bit */
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/** DAC channel1 ready status bit */
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#define DAC_SR_DAC1RDY (1 << 11)
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/**@}*/
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/* --- DAC_CCR values ----------------------------------------------------- */
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/**@defgroup dac_ccr_values DAC_CCR values
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* @{
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*/
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/* DAC channel2 offset trimming value */
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#define DAC_CCR_OTRIM2_SHIFT 16
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#define DAC_CCR_OTRIM2_MASK 0x1F
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@ -225,16 +239,20 @@ specific memorymap.h header before including this header file.*/
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/* DAC channel1 offset trimming value */
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#define DAC_CCR_OTRIM1_SHIFT 0
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#define DAC_CCR_OTRIM1_MASK 0x1F
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/**@}*/
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/* --- DAC_MCR values ----------------------------------------------------- */
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/* Enable signed format for DAC channel2 */
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/**@defgroup dac_mcr_values DAC_MCR values
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* @{
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*/
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/** Enable signed format for DAC channel2 */
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#define DAC_MCR_SINFORMAT2 (1 << 25)
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/* DAC channel2 DMA double data mode */
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/** DAC channel2 DMA double data mode */
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#define DAC_MCR_DMADOUBLE2 (1 << 24)
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/* MODE2[2:0]: DAC channel2 mode */
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/** MODE2[2:0]: DAC channel2 mode */
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#define DAC_MCR_MODE2_SHIFT 16
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/** @defgroup dac_mode2_sel DAC Channel 2 Mode Selection
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@ingroup dac_defines
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@ -277,10 +295,10 @@ specific memorymap.h header before including this header file.*/
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#define DAC_MCR_HFSEL_AHB160 (0x2 << DAC_MCR_HFSEL_SHIFT)
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/**@}*/
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/* Enable signed format for DAC channel1 */
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/** Enable signed format for DAC channel1 */
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#define DAC_MCR_SINFORMAT1 (1 << 9)
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/* DAC channel1 DMA double data mode */
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/** DAC channel1 DMA double data mode */
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#define DAC_MCR_DMADOUBLE1 (1 << 8)
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/* MODE1[2:0]: DAC channel1 mode */
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@ -310,6 +328,7 @@ specific memorymap.h header before including this header file.*/
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#define DAC_MCR_MODE1_PERIPHERAL (0x1 << DAC_MCR_MODE1_SHIFT)
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#define DAC_MCR_MODE1_UNBUFFERED (0x2 << DAC_MCR_MODE1_SHIFT)
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#define DAC_MCR_MODE1_SAMPLEHOLD (0x4 << DAC_MCR_MODE1_SHIFT)
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/**@}*/
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/* --- DAC_SHSR1 values ----------------------------------------------------- */
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