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Merge pull request #4 from TitanMKD/master 

LPC43xx SSP driver fixed (tested with Write)
This commit is contained in:
Michael Ossmann 2012-06-05 20:04:15 -07:00
parent 416f633dbb 8adc873e84
commit 4de126f6e0
5 changed files with 51 additions and 12 deletions
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28
examples/lpc43xx/hackrf-jellybean/ssp/README
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@ -18,3 +18,31 @@ SSP1_MOSI: Jellybean P9 SPI Pin4
SSP1_SCK: Jellybean P9 SPI Pin2
SSP1_SSEL: Jellybean P9 SPI Pin3
GND: Can be connected to P12 SD Pin1
PCLK clock source is PLL1 288MHz (from IRC 96MHz boot from SPIFI)
Freq = PCLK / (CPSDVSR * [SCR+1]).
By default (CPSDVSR=0 => Means MAX Divisor)
SSP1->CR0->SCR = 0x00 => CLK Freq 1.126MHz
SSP1->CR0->SCR = 0x01 => MOSI Freq 566.9KHz
...
Test Oscilloscpe:
SCR=0, CPSDVSR=32 => CLK 9.025MHz
SCR=1, CPSDVSR=2 => CLK 73MHz
SCR=2, CPSDVSR=2 => CLK 49MHz
SCR=4, CPSDVSR=2 => CLK 29MHz
SCR=8, CPSDVSR=2 => CLK 16MHz
SCR=16, CPSDVSR=2 => CLK 8.5MHz
SCR=32, CPSDVSR=2 => CLK 4.386MHz
SCR=64, CPSDVSR=2 => CLK 2.227MHz
SCR=1, CPSDVSR=64 => CLK 2.262MHz
Theory:
SCR=0, CPSDVSR=32 => 288MHz / (32*(0+1) = 9MHz
SCR=1, CPSDVSR=2 => 288MHz / (2*(1+1) = 72MHz
SCR=4, CPSDVSR=2 => 288MHz / (2*(4+1) = 28.8MHz
SCR=32, CPSDVSR=2 => 288MHz / (2*(32+1) = 4.364MHz
SCR=64, CPSDVSR=2 => 288MHz / (2*(64+1)) = 2.2154MHz
SCR=128, CPSDVSR=2 => 288MHz / (2*(128+1)) = 1.116MHz
SCR=1, CPSDVSR=64 => 288MHz / (64*(1+1)) = 2.25MHz

25
examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c
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@ -26,6 +26,16 @@
void gpio_setup(void)
{
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;
GPIO2_DIR = 0;
GPIO3_DIR = 0;
GPIO4_DIR = 0;
GPIO5_DIR = 0;
GPIO6_DIR = 0;
GPIO7_DIR = 0;
/* Configure SCU Pin Mux as GPIO */
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
@ -44,16 +54,6 @@ void gpio_setup(void)
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;
GPIO2_DIR = 0;
GPIO3_DIR = 0;
GPIO4_DIR = 0;
GPIO5_DIR = 0;
GPIO6_DIR = 0;
GPIO7_DIR = 0;
/* Configure GPIO as Output */
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
@ -64,10 +64,12 @@ int main(void)
int i;
u8 ssp_val;
u8 serial_clock_rate;
u8 clock_prescale_rate;
gpio_setup();
/* FIX Me freq */
/* Freq About 1.12MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=288MHz */
clock_prescale_rate = 2;
serial_clock_rate = 128;
ssp_init(SSP1_NUM,
@ -75,6 +77,7 @@ int main(void)
SSP_FRAME_SPI,
SSP_CPOL_0_CPHA_0,
serial_clock_rate,
clock_prescale_rate,
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);

2
include/libopencm3/lpc43xx/scu.h
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@ -723,7 +723,7 @@ typedef enum {
#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf);

6
include/libopencm3/lpc43xx/ssp.h
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@ -159,11 +159,17 @@ typedef enum {
void ssp_disable(ssp_num_t ssp_num);
/*
* SSP Init
* clk_prescale shall be in range 2 to 254 (even number only).
* Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, SCR=serial_clock_rate
*/
void ssp_init(ssp_num_t ssp_num,
ssp_datasize_t data_size,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
u8 serial_clock_rate,
u8 clk_prescale,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option);

2
lib/lpc43xx/ssp.c
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@ -62,6 +62,7 @@ void ssp_init(ssp_num_t ssp_num,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
u8 serial_clock_rate,
u8 clk_prescale,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option)
@ -85,6 +86,7 @@ void ssp_init(ssp_num_t ssp_num,
/* Configure SSP */
clock = serial_clock_rate;
SSP_CPSR(ssp_port) = clk_prescale;
SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) );
/* Enable SSP */