Proposed deduplication of peripherals, GPIO example
See rambling post on dev list for justification
This commit is contained in:
Ken Sarkies
Ken Sarkies
parent
d08d366e75
commit
4ab5c94b90
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@ -17,19 +17,19 @@ WARN_LOGFILE = doxygen_stm32f1.log
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INPUT = ../../include/libopencm3/license.dox \
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../../include/libopencm3/stm32/f1 \
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../../include/libopencm3/stm32/common \
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../../lib/stm32/f1 \
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../../lib/stm32/common
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../../include/libopencm3/stm32/common/gpio_common_all.h
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INPUT += ../../lib/stm32/f1 \
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../../lib/stm32/common/gpio_common_all.c
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EXCLUDE = ../../include/libopencm3/stm32/f1/usb.h \
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../../include/libopencm3/stm32/f1/usb_desc.h \
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../../include/libopencm3/stm32/f1/nvic_f1.h
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../../include/libopencm3/stm32/f1/usb_desc.h
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EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c
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LAYOUT_FILE = DoxygenLayout_stm32f1.xml
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TAGFILES = ../cm3/cm3.tag=../../cm3/html \
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TAGFILES = ../cm3/cm3.tag=../../cm3/html
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GENERATE_TAGFILE = stm32f1.tag
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@ -17,15 +17,18 @@ WARN_LOGFILE = doxygen_stm32f2.log
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INPUT = ../../include/libopencm3/license.dox \
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../../include/libopencm3/stm32/f2 \
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../../include/libopencm3/stm32/common \
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../../lib/stm32/f2 \
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../../lib/stm32/common
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../../include/libopencm3/stm32/common/gpio_common_all.h \
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../../include/libopencm3/stm32/common/gpio_common_f24.h
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INPUT += ../../lib/stm32/f2 \
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../../lib/stm32/common/gpio_common_all.c \
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../../lib/stm32/common/gpio_common_f24.c
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EXCLUDE =
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LAYOUT_FILE = DoxygenLayout_stm32f2.xml
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TAGFILES = ../cm3/cm3.tag=../../cm3/html \
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TAGFILES = ../cm3/cm3.tag=../../cm3/html
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GENERATE_TAGFILE = stm32f2.tag
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@ -17,15 +17,18 @@ WARN_LOGFILE = doxygen_stm32f4.log
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INPUT = ../../include/libopencm3/license.dox \
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../../include/libopencm3/stm32/f4 \
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../../include/libopencm3/stm32/common \
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../../lib/stm32/f4 \
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../../lib/stm32/common
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../../include/libopencm3/stm32/common/gpio_common_all.h \
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../../include/libopencm3/stm32/common/gpio_common_f24.h
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INPUT += ../../lib/stm32/f4 \
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../../lib/stm32/common/gpio_common_all.c \
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../../lib/stm32/common/gpio_common_f24.c
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EXCLUDE =
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LAYOUT_FILE = DoxygenLayout_stm32f4.xml
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TAGFILES = ../cm3/cm3.tag=../../cm3/html \
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TAGFILES = ../cm3/cm3.tag=../../cm3/html
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GENERATE_TAGFILE = stm32f4.tag
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@ -1,4 +1,4 @@
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/** @defgroup STM32F1xx_gpio_defines GPIO Defines
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/** @defgroup gpio_defines GPIO Defines
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@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
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@ -8,6 +8,7 @@
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
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@date 1 July 2012
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@ -18,6 +19,7 @@ LGPL License Terms @ref lgpl_license
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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@ -32,21 +34,23 @@ LGPL License Terms @ref lgpl_license
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_GPIO_H
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#define LIBOPENCM3_GPIO_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/f1/memorymap.h>
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#include <libopencm3/stm32/common/gpio_common_all.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* GPIO port base addresses (for convenience) */
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/** @defgroup gpio_port_id GPIO Port IDs
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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/* GPIO port base addresses (for convenience) */
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#define GPIOA GPIO_PORT_A_BASE
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#define GPIOB GPIO_PORT_B_BASE
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#define GPIOC GPIO_PORT_C_BASE
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@ -56,30 +60,6 @@ LGPL License Terms @ref lgpl_license
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#define GPIOG GPIO_PORT_G_BASE
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/**@}*/
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/* GPIO number definitions (for convenience) */
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/** @defgroup gpio_pin_id GPIO Pin Identifiers
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@ingroup STM32F1xx_gpio_defines
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@{*/
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO8 (1 << 8)
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#define GPIO9 (1 << 9)
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#define GPIO10 (1 << 10)
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#define GPIO11 (1 << 11)
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#define GPIO12 (1 << 12)
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#define GPIO13 (1 << 13)
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#define GPIO14 (1 << 14)
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#define GPIO15 (1 << 15)
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#define GPIO_ALL 0xffff
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/**@}*/
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/* --- Alternate function GPIOs -------------------------------------------- */
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/* Default alternate functions of some pins (with and without remapping) */
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@ -620,7 +600,7 @@ LGPL License Terms @ref lgpl_license
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/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
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/** @defgroup gpio_cnf GPIO Pin Configuration
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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If mode specifies input, configuration can be
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@li Analog input
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@li Floating input
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@ -652,7 +632,7 @@ If mode specifies output, configuration can be
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/* Pin mode (MODE[1:0]) values */
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/** @defgroup gpio_mode GPIO Pin Mode
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@li Input (default after reset)
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@li Output mode at 10 MHz maximum speed
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@li Output mode at 2 MHz maximum speed
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@ -681,11 +661,6 @@ If mode specifies output, configuration can be
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/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */
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/* --- GPIO_LCKR values ---------------------------------------------------- */
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#define GPIO_LCKK (1 << 16)
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/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
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/* --- AFIO registers ------------------------------------------------------ */
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/* Event control register (AFIO_EVCR) */
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@ -716,7 +691,7 @@ If mode specifies output, configuration can be
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/* PORT[2:0]: Port selection */
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/** @defgroup afio_evcr_port EVENTOUT Port selection
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_EVCR_PORT_PA (0x0 << 4)
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@ -728,7 +703,7 @@ If mode specifies output, configuration can be
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/* PIN[3:0]: Pin selection */
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/** @defgroup afio_evcr_pin EVENTOUT Pin selection
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
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@ -755,7 +730,7 @@ If mode specifies output, configuration can be
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/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
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Line Devices only
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
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@ -788,7 +763,7 @@ Line Devices only
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/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
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/** @defgroup afio_swj_disable Serial Wire JTAG disables
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
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/**@}*/
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/** @defgroup afio_remap Alternate Function Remap Controls
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
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@ -846,7 +821,7 @@ Line Devices only
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/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
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/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
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@ -856,7 +831,7 @@ Line Devices only
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/* TIM3_REMAP[1:0]: TIM3 remapping */
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/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
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/* TIM2_REMAP[1:0]: TIM2 remapping */
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/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
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/* TIM1_REMAP[1:0]: TIM1 remapping */
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/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
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/* USART3_REMAP[1:0]: USART3 remapping */
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/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
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@ -896,7 +871,7 @@ Line Devices only
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/**@}*/
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/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
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@ -925,7 +900,7 @@ Line Devices only
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/* --- AFIO_EXTICR4 values ------------------------------------------------- */
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/** @defgroup afio_exti Alternate Function EXTI pin number
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@ingroup STM32F1xx_gpio_defines
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@ingroup gpio_defines
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@{*/
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@ -953,13 +928,6 @@ Line Devices only
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BEGIN_DECLS
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void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
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void gpio_set(u32 gpioport, u16 gpios);
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void gpio_clear(u32 gpioport, u16 gpios);
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u16 gpio_get(u32 gpioport, u16 gpios);
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void gpio_toggle(u32 gpioport, u16 gpios);
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u16 gpio_port_read(u32 gpioport);
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void gpio_port_write(u32 gpioport, u16 data);
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void gpio_port_config_lock(u32 gpioport, u16 gpios);
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void gpio_set_eventout(u8 evoutport, u8 evoutpin);
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void gpio_primary_remap(u8 swjenable, u32 maps);
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void gpio_secondary_remap(u32 maps);
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@ -1,8 +1,23 @@
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/** @defgroup gpio_defines GPIO Defines
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@brief <b>Defined Constants and Types for the STM32F2xx General Purpose I/O</b>
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@ingroup STM32F2xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
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@date 1 July 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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@ -20,263 +35,8 @@
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#ifndef LIBOPENCM3_GPIO_H
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#define LIBOPENCM3_GPIO_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* GPIO port base addresses (for convenience) */
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#define GPIOA GPIO_PORT_A_BASE
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#define GPIOB GPIO_PORT_B_BASE
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#define GPIOC GPIO_PORT_C_BASE
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#define GPIOD GPIO_PORT_D_BASE
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#define GPIOE GPIO_PORT_E_BASE
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#define GPIOF GPIO_PORT_F_BASE
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#define GPIOG GPIO_PORT_G_BASE
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#define GPIOH GPIO_PORT_H_BASE
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#define GPIOI GPIO_PORT_I_BASE
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/* GPIO number definitions (for convenience) */
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO8 (1 << 8)
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#define GPIO9 (1 << 9)
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#define GPIO10 (1 << 10)
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#define GPIO11 (1 << 11)
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#define GPIO12 (1 << 12)
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#define GPIO13 (1 << 13)
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#define GPIO14 (1 << 14)
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#define GPIO15 (1 << 15)
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#define GPIO_ALL 0xffff
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/* --- GPIO registers ------------------------------------------------------ */
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/* Port mode register (GPIOx_MODER) */
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#define GPIO_MODER(port) MMIO32(port + 0x00)
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#define GPIOA_MODER GPIO_MODER(GPIOA)
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#define GPIOB_MODER GPIO_MODER(GPIOB)
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#define GPIOC_MODER GPIO_MODER(GPIOC)
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#define GPIOD_MODER GPIO_MODER(GPIOD)
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#define GPIOE_MODER GPIO_MODER(GPIOE)
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#define GPIOF_MODER GPIO_MODER(GPIOF)
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#define GPIOG_MODER GPIO_MODER(GPIOG)
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#define GPIOH_MODER GPIO_MODER(GPIOH)
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#define GPIOI_MODER GPIO_MODER(GPIOI)
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/* Port output type register (GPIOx_OTYPER) */
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#define GPIO_OTYPER(port) MMIO32(port + 0x04)
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#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
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#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
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#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
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#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
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#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
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#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
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#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
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#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
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#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
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/* Port output speed register (GPIOx_OSPEEDR) */
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#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
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#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
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#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
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#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
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#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
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#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
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#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
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#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
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#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
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#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
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/* Port pull-up/pull-down register (GPIOx_PUPDR) */
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||||
#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
|
||||
#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
|
||||
#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
|
||||
#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
|
||||
#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
|
||||
#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
|
||||
#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
|
||||
#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
|
||||
#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
|
||||
#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
|
||||
|
||||
/* Port input data register (GPIOx_IDR) */
|
||||
#define GPIO_IDR(port) MMIO32(port + 0x10)
|
||||
#define GPIOA_IDR GPIO_IDR(GPIOA)
|
||||
#define GPIOB_IDR GPIO_IDR(GPIOB)
|
||||
#define GPIOC_IDR GPIO_IDR(GPIOC)
|
||||
#define GPIOD_IDR GPIO_IDR(GPIOD)
|
||||
#define GPIOE_IDR GPIO_IDR(GPIOE)
|
||||
#define GPIOF_IDR GPIO_IDR(GPIOF)
|
||||
#define GPIOG_IDR GPIO_IDR(GPIOG)
|
||||
#define GPIOH_IDR GPIO_IDR(GPIOH)
|
||||
#define GPIOI_IDR GPIO_IDR(GPIOI)
|
||||
|
||||
/* Port output data register (GPIOx_ODR) */
|
||||
#define GPIO_ODR(port) MMIO32(port + 0x14)
|
||||
#define GPIOA_ODR GPIO_ODR(GPIOA)
|
||||
#define GPIOB_ODR GPIO_ODR(GPIOB)
|
||||
#define GPIOC_ODR GPIO_ODR(GPIOC)
|
||||
#define GPIOD_ODR GPIO_ODR(GPIOD)
|
||||
#define GPIOE_ODR GPIO_ODR(GPIOE)
|
||||
#define GPIOF_ODR GPIO_ODR(GPIOF)
|
||||
#define GPIOG_ODR GPIO_ODR(GPIOG)
|
||||
#define GPIOH_ODR GPIO_ODR(GPIOH)
|
||||
#define GPIOI_ODR GPIO_ODR(GPIOI)
|
||||
|
||||
/* Port bit set/reset register (GPIOx_BSRR) */
|
||||
#define GPIO_BSRR(port) MMIO32(port + 0x18)
|
||||
#define GPIOA_BSRR GPIO_BSRR(GPIOA)
|
||||
#define GPIOB_BSRR GPIO_BSRR(GPIOB)
|
||||
#define GPIOC_BSRR GPIO_BSRR(GPIOC)
|
||||
#define GPIOD_BSRR GPIO_BSRR(GPIOD)
|
||||
#define GPIOE_BSRR GPIO_BSRR(GPIOE)
|
||||
#define GPIOF_BSRR GPIO_BSRR(GPIOF)
|
||||
#define GPIOG_BSRR GPIO_BSRR(GPIOG)
|
||||
#define GPIOH_BSRR GPIO_BSRR(GPIOH)
|
||||
#define GPIOI_BSRR GPIO_BSRR(GPIOI)
|
||||
|
||||
/* Port configuration lock register (GPIOx_LCKR) */
|
||||
#define GPIO_LCKR(port) MMIO32(port + 0x1c)
|
||||
#define GPIOA_LCKR GPIO_LCKR(GPIOA)
|
||||
#define GPIOB_LCKR GPIO_LCKR(GPIOB)
|
||||
#define GPIOC_LCKR GPIO_LCKR(GPIOC)
|
||||
#define GPIOD_LCKR GPIO_LCKR(GPIOD)
|
||||
#define GPIOE_LCKR GPIO_LCKR(GPIOE)
|
||||
#define GPIOF_LCKR GPIO_LCKR(GPIOF)
|
||||
#define GPIOG_LCKR GPIO_LCKR(GPIOG)
|
||||
#define GPIOH_LCKR GPIO_LCKR(GPIOH)
|
||||
#define GPIOI_LCKR GPIO_LCKR(GPIOI)
|
||||
|
||||
/* Alternate function low register (GPIOx_AFRL) */
|
||||
#define GPIO_AFRL(port) MMIO32(port + 0x20)
|
||||
#define GPIOA_AFRL GPIO_AFRL(GPIOA)
|
||||
#define GPIOB_AFRL GPIO_AFRL(GPIOB)
|
||||
#define GPIOC_AFRL GPIO_AFRL(GPIOC)
|
||||
#define GPIOD_AFRL GPIO_AFRL(GPIOD)
|
||||
#define GPIOE_AFRL GPIO_AFRL(GPIOE)
|
||||
#define GPIOF_AFRL GPIO_AFRL(GPIOF)
|
||||
#define GPIOG_AFRL GPIO_AFRL(GPIOG)
|
||||
#define GPIOH_AFRL GPIO_AFRL(GPIOH)
|
||||
#define GPIOI_AFRL GPIO_AFRL(GPIOI)
|
||||
|
||||
/* Alternate function high register (GPIOx_AFRH) */
|
||||
#define GPIO_AFRH(port) MMIO32(port + 0x24)
|
||||
#define GPIOA_AFRH GPIO_AFRH(GPIOA)
|
||||
#define GPIOB_AFRH GPIO_AFRH(GPIOB)
|
||||
#define GPIOC_AFRH GPIO_AFRH(GPIOC)
|
||||
#define GPIOD_AFRH GPIO_AFRH(GPIOD)
|
||||
#define GPIOE_AFRH GPIO_AFRH(GPIOE)
|
||||
#define GPIOF_AFRH GPIO_AFRH(GPIOF)
|
||||
#define GPIOG_AFRH GPIO_AFRH(GPIOG)
|
||||
#define GPIOH_AFRH GPIO_AFRH(GPIOH)
|
||||
#define GPIOI_AFRH GPIO_AFRH(GPIOI)
|
||||
|
||||
/* --- GPIOx_MODER values -------------------------------------------------- */
|
||||
|
||||
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
|
||||
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_MODE_INPUT 0x0
|
||||
#define GPIO_MODE_OUTPUT 0x1
|
||||
#define GPIO_MODE_AF 0x2
|
||||
#define GPIO_MODE_ANALOG 0x3
|
||||
|
||||
/* --- GPIOx_OTYPER values ------------------------------------------------- */
|
||||
|
||||
#define GPIO_OTYPE_PP 0x0
|
||||
#define GPIO_OTYPE_OD 0x1
|
||||
|
||||
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
|
||||
|
||||
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
|
||||
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_OSPEED_2MHZ 0x0
|
||||
#define GPIO_OSPEED_25MHZ 0x1
|
||||
#define GPIO_OSPEED_50MHZ 0x2
|
||||
#define GPIO_OSPEED_100MHZ 0x3
|
||||
|
||||
/* --- GPIOx_PUPDR values -------------------------------------------------- */
|
||||
|
||||
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
|
||||
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_PUPD_NONE 0x0
|
||||
#define GPIO_PUPD_PULLUP 0x1
|
||||
#define GPIO_PUPD_PULLDOWN 0x2
|
||||
|
||||
/* --- GPIOx_IDR values ---------------------------------------------------- */
|
||||
|
||||
/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_ODR values ---------------------------------------------------- */
|
||||
|
||||
/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_BSRR values --------------------------------------------------- */
|
||||
|
||||
/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
|
||||
/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_LCKR values --------------------------------------------------- */
|
||||
|
||||
#define GPIO_LCKK (1 << 16)
|
||||
/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_AFRL/H values ------------------------------------------------- */
|
||||
|
||||
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
|
||||
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
|
||||
|
||||
#define GPIO_AFR(n, af) (af << ((n) * 4))
|
||||
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
|
||||
#define GPIO_AF0 0x0
|
||||
#define GPIO_AF1 0x1
|
||||
#define GPIO_AF2 0x2
|
||||
#define GPIO_AF3 0x3
|
||||
#define GPIO_AF4 0x4
|
||||
#define GPIO_AF5 0x5
|
||||
#define GPIO_AF6 0x6
|
||||
#define GPIO_AF7 0x7
|
||||
#define GPIO_AF8 0x8
|
||||
#define GPIO_AF9 0x9
|
||||
#define GPIO_AF10 0xa
|
||||
#define GPIO_AF11 0xb
|
||||
#define GPIO_AF12 0xc
|
||||
#define GPIO_AF13 0xd
|
||||
#define GPIO_AF14 0xe
|
||||
#define GPIO_AF15 0xf
|
||||
|
||||
/* Note: EXTI source selection is now in the SYSCFG peripheral. */
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
/*
|
||||
* Note: The F2 series has a completely new GPIO peripheral with different
|
||||
* configuration options. Here we implement a different API partly to more
|
||||
* closely match the peripheral capabilities and also to deliberately break
|
||||
* compatibility with old F1 code so there is no confusion with similar
|
||||
* sounding functions that have very different functionality.
|
||||
*/
|
||||
|
||||
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
|
||||
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
|
||||
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
|
||||
|
||||
/* This part of the API is compatible with the F1 series ------------------- */
|
||||
void gpio_set(u32 gpioport, u16 gpios);
|
||||
void gpio_clear(u32 gpioport, u16 gpios);
|
||||
u16 gpio_get(u32 gpioport, u16 gpios);
|
||||
void gpio_toggle(u32 gpioport, u16 gpios);
|
||||
u16 gpio_port_read(u32 gpioport);
|
||||
void gpio_port_write(u32 gpioport, u16 data);
|
||||
void gpio_port_config_lock(u32 gpioport, u16 gpios);
|
||||
|
||||
END_DECLS
|
||||
#include <libopencm3/stm32/f2/memorymap.h>
|
||||
#include <libopencm3/stm32/common/gpio_common_f24.h>
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,23 @@
|
|||
/** @defgroup gpio_defines GPIO Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F4xx General Purpose I/O</b>
|
||||
|
||||
@ingroup STM32F4xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
@author @htmlonly © @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 1 July 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
|
|
@ -20,263 +35,8 @@
|
|||
#ifndef LIBOPENCM3_GPIO_H
|
||||
#define LIBOPENCM3_GPIO_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* GPIO port base addresses (for convenience) */
|
||||
#define GPIOA GPIO_PORT_A_BASE
|
||||
#define GPIOB GPIO_PORT_B_BASE
|
||||
#define GPIOC GPIO_PORT_C_BASE
|
||||
#define GPIOD GPIO_PORT_D_BASE
|
||||
#define GPIOE GPIO_PORT_E_BASE
|
||||
#define GPIOF GPIO_PORT_F_BASE
|
||||
#define GPIOG GPIO_PORT_G_BASE
|
||||
#define GPIOH GPIO_PORT_H_BASE
|
||||
#define GPIOI GPIO_PORT_I_BASE
|
||||
|
||||
/* GPIO number definitions (for convenience) */
|
||||
#define GPIO0 (1 << 0)
|
||||
#define GPIO1 (1 << 1)
|
||||
#define GPIO2 (1 << 2)
|
||||
#define GPIO3 (1 << 3)
|
||||
#define GPIO4 (1 << 4)
|
||||
#define GPIO5 (1 << 5)
|
||||
#define GPIO6 (1 << 6)
|
||||
#define GPIO7 (1 << 7)
|
||||
#define GPIO8 (1 << 8)
|
||||
#define GPIO9 (1 << 9)
|
||||
#define GPIO10 (1 << 10)
|
||||
#define GPIO11 (1 << 11)
|
||||
#define GPIO12 (1 << 12)
|
||||
#define GPIO13 (1 << 13)
|
||||
#define GPIO14 (1 << 14)
|
||||
#define GPIO15 (1 << 15)
|
||||
#define GPIO_ALL 0xffff
|
||||
|
||||
/* --- GPIO registers ------------------------------------------------------ */
|
||||
|
||||
/* Port mode register (GPIOx_MODER) */
|
||||
#define GPIO_MODER(port) MMIO32(port + 0x00)
|
||||
#define GPIOA_MODER GPIO_MODER(GPIOA)
|
||||
#define GPIOB_MODER GPIO_MODER(GPIOB)
|
||||
#define GPIOC_MODER GPIO_MODER(GPIOC)
|
||||
#define GPIOD_MODER GPIO_MODER(GPIOD)
|
||||
#define GPIOE_MODER GPIO_MODER(GPIOE)
|
||||
#define GPIOF_MODER GPIO_MODER(GPIOF)
|
||||
#define GPIOG_MODER GPIO_MODER(GPIOG)
|
||||
#define GPIOH_MODER GPIO_MODER(GPIOH)
|
||||
#define GPIOI_MODER GPIO_MODER(GPIOI)
|
||||
|
||||
/* Port output type register (GPIOx_OTYPER) */
|
||||
#define GPIO_OTYPER(port) MMIO32(port + 0x04)
|
||||
#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
|
||||
#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
|
||||
#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
|
||||
#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
|
||||
#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
|
||||
#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
|
||||
#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
|
||||
#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
|
||||
#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
|
||||
|
||||
/* Port output speed register (GPIOx_OSPEEDR) */
|
||||
#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
|
||||
#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
|
||||
#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
|
||||
#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
|
||||
#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
|
||||
#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
|
||||
#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
|
||||
#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
|
||||
#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
|
||||
#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
|
||||
|
||||
/* Port pull-up/pull-down register (GPIOx_PUPDR) */
|
||||
#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
|
||||
#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
|
||||
#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
|
||||
#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
|
||||
#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
|
||||
#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
|
||||
#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
|
||||
#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
|
||||
#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
|
||||
#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
|
||||
|
||||
/* Port input data register (GPIOx_IDR) */
|
||||
#define GPIO_IDR(port) MMIO32(port + 0x10)
|
||||
#define GPIOA_IDR GPIO_IDR(GPIOA)
|
||||
#define GPIOB_IDR GPIO_IDR(GPIOB)
|
||||
#define GPIOC_IDR GPIO_IDR(GPIOC)
|
||||
#define GPIOD_IDR GPIO_IDR(GPIOD)
|
||||
#define GPIOE_IDR GPIO_IDR(GPIOE)
|
||||
#define GPIOF_IDR GPIO_IDR(GPIOF)
|
||||
#define GPIOG_IDR GPIO_IDR(GPIOG)
|
||||
#define GPIOH_IDR GPIO_IDR(GPIOH)
|
||||
#define GPIOI_IDR GPIO_IDR(GPIOI)
|
||||
|
||||
/* Port output data register (GPIOx_ODR) */
|
||||
#define GPIO_ODR(port) MMIO32(port + 0x14)
|
||||
#define GPIOA_ODR GPIO_ODR(GPIOA)
|
||||
#define GPIOB_ODR GPIO_ODR(GPIOB)
|
||||
#define GPIOC_ODR GPIO_ODR(GPIOC)
|
||||
#define GPIOD_ODR GPIO_ODR(GPIOD)
|
||||
#define GPIOE_ODR GPIO_ODR(GPIOE)
|
||||
#define GPIOF_ODR GPIO_ODR(GPIOF)
|
||||
#define GPIOG_ODR GPIO_ODR(GPIOG)
|
||||
#define GPIOH_ODR GPIO_ODR(GPIOH)
|
||||
#define GPIOI_ODR GPIO_ODR(GPIOI)
|
||||
|
||||
/* Port bit set/reset register (GPIOx_BSRR) */
|
||||
#define GPIO_BSRR(port) MMIO32(port + 0x18)
|
||||
#define GPIOA_BSRR GPIO_BSRR(GPIOA)
|
||||
#define GPIOB_BSRR GPIO_BSRR(GPIOB)
|
||||
#define GPIOC_BSRR GPIO_BSRR(GPIOC)
|
||||
#define GPIOD_BSRR GPIO_BSRR(GPIOD)
|
||||
#define GPIOE_BSRR GPIO_BSRR(GPIOE)
|
||||
#define GPIOF_BSRR GPIO_BSRR(GPIOF)
|
||||
#define GPIOG_BSRR GPIO_BSRR(GPIOG)
|
||||
#define GPIOH_BSRR GPIO_BSRR(GPIOH)
|
||||
#define GPIOI_BSRR GPIO_BSRR(GPIOI)
|
||||
|
||||
/* Port configuration lock register (GPIOx_LCKR) */
|
||||
#define GPIO_LCKR(port) MMIO32(port + 0x1c)
|
||||
#define GPIOA_LCKR GPIO_LCKR(GPIOA)
|
||||
#define GPIOB_LCKR GPIO_LCKR(GPIOB)
|
||||
#define GPIOC_LCKR GPIO_LCKR(GPIOC)
|
||||
#define GPIOD_LCKR GPIO_LCKR(GPIOD)
|
||||
#define GPIOE_LCKR GPIO_LCKR(GPIOE)
|
||||
#define GPIOF_LCKR GPIO_LCKR(GPIOF)
|
||||
#define GPIOG_LCKR GPIO_LCKR(GPIOG)
|
||||
#define GPIOH_LCKR GPIO_LCKR(GPIOH)
|
||||
#define GPIOI_LCKR GPIO_LCKR(GPIOI)
|
||||
|
||||
/* Alternate function low register (GPIOx_AFRL) */
|
||||
#define GPIO_AFRL(port) MMIO32(port + 0x20)
|
||||
#define GPIOA_AFRL GPIO_AFRL(GPIOA)
|
||||
#define GPIOB_AFRL GPIO_AFRL(GPIOB)
|
||||
#define GPIOC_AFRL GPIO_AFRL(GPIOC)
|
||||
#define GPIOD_AFRL GPIO_AFRL(GPIOD)
|
||||
#define GPIOE_AFRL GPIO_AFRL(GPIOE)
|
||||
#define GPIOF_AFRL GPIO_AFRL(GPIOF)
|
||||
#define GPIOG_AFRL GPIO_AFRL(GPIOG)
|
||||
#define GPIOH_AFRL GPIO_AFRL(GPIOH)
|
||||
#define GPIOI_AFRL GPIO_AFRL(GPIOI)
|
||||
|
||||
/* Alternate function high register (GPIOx_AFRH) */
|
||||
#define GPIO_AFRH(port) MMIO32(port + 0x24)
|
||||
#define GPIOA_AFRH GPIO_AFRH(GPIOA)
|
||||
#define GPIOB_AFRH GPIO_AFRH(GPIOB)
|
||||
#define GPIOC_AFRH GPIO_AFRH(GPIOC)
|
||||
#define GPIOD_AFRH GPIO_AFRH(GPIOD)
|
||||
#define GPIOE_AFRH GPIO_AFRH(GPIOE)
|
||||
#define GPIOF_AFRH GPIO_AFRH(GPIOF)
|
||||
#define GPIOG_AFRH GPIO_AFRH(GPIOG)
|
||||
#define GPIOH_AFRH GPIO_AFRH(GPIOH)
|
||||
#define GPIOI_AFRH GPIO_AFRH(GPIOI)
|
||||
|
||||
/* --- GPIOx_MODER values -------------------------------------------------- */
|
||||
|
||||
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
|
||||
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_MODE_INPUT 0x0
|
||||
#define GPIO_MODE_OUTPUT 0x1
|
||||
#define GPIO_MODE_AF 0x2
|
||||
#define GPIO_MODE_ANALOG 0x3
|
||||
|
||||
/* --- GPIOx_OTYPER values ------------------------------------------------- */
|
||||
|
||||
#define GPIO_OTYPE_PP 0x0
|
||||
#define GPIO_OTYPE_OD 0x1
|
||||
|
||||
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
|
||||
|
||||
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
|
||||
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_OSPEED_2MHZ 0x0
|
||||
#define GPIO_OSPEED_25MHZ 0x1
|
||||
#define GPIO_OSPEED_50MHZ 0x2
|
||||
#define GPIO_OSPEED_100MHZ 0x3
|
||||
|
||||
/* --- GPIOx_PUPDR values -------------------------------------------------- */
|
||||
|
||||
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
|
||||
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_PUPD_NONE 0x0
|
||||
#define GPIO_PUPD_PULLUP 0x1
|
||||
#define GPIO_PUPD_PULLDOWN 0x2
|
||||
|
||||
/* --- GPIOx_IDR values ---------------------------------------------------- */
|
||||
|
||||
/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_ODR values ---------------------------------------------------- */
|
||||
|
||||
/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_BSRR values --------------------------------------------------- */
|
||||
|
||||
/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
|
||||
/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_LCKR values --------------------------------------------------- */
|
||||
|
||||
#define GPIO_LCKK (1 << 16)
|
||||
/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_AFRL/H values ------------------------------------------------- */
|
||||
|
||||
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
|
||||
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
|
||||
|
||||
#define GPIO_AFR(n, af) (af << ((n) * 4))
|
||||
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
|
||||
#define GPIO_AF0 0x0
|
||||
#define GPIO_AF1 0x1
|
||||
#define GPIO_AF2 0x2
|
||||
#define GPIO_AF3 0x3
|
||||
#define GPIO_AF4 0x4
|
||||
#define GPIO_AF5 0x5
|
||||
#define GPIO_AF6 0x6
|
||||
#define GPIO_AF7 0x7
|
||||
#define GPIO_AF8 0x8
|
||||
#define GPIO_AF9 0x9
|
||||
#define GPIO_AF10 0xa
|
||||
#define GPIO_AF11 0xb
|
||||
#define GPIO_AF12 0xc
|
||||
#define GPIO_AF13 0xd
|
||||
#define GPIO_AF14 0xe
|
||||
#define GPIO_AF15 0xf
|
||||
|
||||
/* Note: EXTI source selection is now in the SYSCFG peripheral. */
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
/*
|
||||
* Note: The F4 series has a completely new GPIO peripheral with different
|
||||
* configuration options. Here we implement a different API partly to more
|
||||
* closely match the peripheral capabilities and also to deliberately break
|
||||
* compatibility with old F1 code so there is no confusion with similar
|
||||
* sounding functions that have very different functionality.
|
||||
*/
|
||||
|
||||
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
|
||||
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
|
||||
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
|
||||
|
||||
/* This part of the API is compatible with the F1 series ------------------- */
|
||||
void gpio_set(u32 gpioport, u16 gpios);
|
||||
void gpio_clear(u32 gpioport, u16 gpios);
|
||||
u16 gpio_get(u32 gpioport, u16 gpios);
|
||||
void gpio_toggle(u32 gpioport, u16 gpios);
|
||||
u16 gpio_port_read(u32 gpioport);
|
||||
void gpio_port_write(u32 gpioport, u16 data);
|
||||
void gpio_port_config_lock(u32 gpioport, u16 gpios);
|
||||
|
||||
END_DECLS
|
||||
#include <libopencm3/stm32/f4/memorymap.h>
|
||||
#include <libopencm3/stm32/common/gpio_common_f24.h>
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -32,9 +32,10 @@ OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o \
|
|||
rtc.o i2c.o dma.o exti.o ethernet.o \
|
||||
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
|
||||
timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \
|
||||
usb_fx07_common.o
|
||||
usb_fx07_common.o \
|
||||
gpio_common_all.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
include ../../Makefile.include
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/** @defgroup STM32F1xx_gpio_file GPIO
|
||||
/** @defgroup gpio_file GPIO
|
||||
|
||||
@ingroup STM32F1xx
|
||||
|
||||
|
|
@ -11,9 +11,6 @@
|
|||
|
||||
@date 18 August 2012
|
||||
|
||||
This library supports the General Purpose I/O System in the STM32F1xx series
|
||||
of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
|
||||
Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO
|
||||
functionality with a number of alternate functions and must be configured to the
|
||||
alternate function mode if these are to be accessed. A feature is available to
|
||||
|
|
@ -55,7 +52,7 @@ Example 1: Digital input on port C12
|
|||
@endcode
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
|
|
@ -75,25 +72,10 @@ LGPL License Terms @ref lgpl_license
|
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Basic GPIO handling API.
|
||||
*
|
||||
* Examples:
|
||||
* gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ,
|
||||
* GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
|
||||
* gpio_set(GPIOB, GPIO4);
|
||||
* gpio_clear(GPIOG, GPIO2 | GPIO9);
|
||||
* gpio_get(GPIOC, GPIO1);
|
||||
* gpio_toggle(GPIOA, GPIO7 | GPIO8);
|
||||
* reg16 = gpio_port_read(GPIOD);
|
||||
* gpio_port_write(GPIOF, 0xc8fe);
|
||||
*
|
||||
* TODO:
|
||||
* - GPIO remapping support
|
||||
*/
|
||||
/**@{*/
|
||||
#include <libopencm3/stm32/gpio.h>
|
||||
#include <libopencm3/stm32/common/gpio_common_all.h>
|
||||
|
||||
#include <libopencm3/stm32/f1/gpio.h>
|
||||
/**@{*/
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Set GPIO Pin Mode
|
||||
|
|
@ -145,116 +127,6 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
|
|||
GPIO_CRH(gpioport) = crh;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Set a Group of Pins Atomic
|
||||
|
||||
Set one or more pins of the given GPIO port to 1 in an atomic operation.
|
||||
|
||||
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
|
||||
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
|
||||
If multiple pins are to be changed, use logical OR '|' to separate them.
|
||||
*/
|
||||
void gpio_set(u32 gpioport, u16 gpios)
|
||||
{
|
||||
GPIO_BSRR(gpioport) = gpios;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Clear a Group of Pins Atomic
|
||||
|
||||
Clear one or more pins of the given GPIO port to 0 in an atomic operation.
|
||||
|
||||
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
|
||||
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
|
||||
If multiple pins are to be changed, use logical OR '|' to separate them.
|
||||
*/
|
||||
void gpio_clear(u32 gpioport, u16 gpios)
|
||||
{
|
||||
GPIO_BRR(gpioport) = gpios;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Read a Group of Pins.
|
||||
|
||||
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
|
||||
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
|
||||
If multiple pins are to be read, use logical OR '|' to separate them.
|
||||
@return Unsigned int16 value of the pin values. The bit position of the pin value
|
||||
returned corresponds to the pin number.
|
||||
*/
|
||||
u16 gpio_get(u32 gpioport, u16 gpios)
|
||||
{
|
||||
return gpio_port_read(gpioport) & gpios;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Toggle a Group of Pins
|
||||
|
||||
Toggle one or more pins of the given GPIO port. This is not an atomic operation.
|
||||
|
||||
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
|
||||
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
|
||||
If multiple pins are to be changed, use logical OR '|' to separate them.
|
||||
*/
|
||||
void gpio_toggle(u32 gpioport, u16 gpios)
|
||||
{
|
||||
GPIO_ODR(gpioport) ^= gpios;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Read from a Port
|
||||
|
||||
Read the current value of the given GPIO port. Only the lower 16 bits contain
|
||||
valid pin data.
|
||||
|
||||
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
|
||||
@return Unsigned int16. The value held in the specified GPIO port.
|
||||
*/
|
||||
u16 gpio_port_read(u32 gpioport)
|
||||
{
|
||||
return (u16)GPIO_IDR(gpioport);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Write to a Port
|
||||
|
||||
Write a value to the given GPIO port.
|
||||
|
||||
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
|
||||
@param[in] data Unsigned int16. The value to be written to the GPIO port.
|
||||
*/
|
||||
void gpio_port_write(u32 gpioport, u16 data)
|
||||
{
|
||||
GPIO_ODR(gpioport) = data;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Lock the Configuration of a Group of Pins
|
||||
|
||||
The configuration of one or more pins of the given GPIO port is locked. There is
|
||||
no mechanism to unlock these via software. Unlocking occurs at the next reset.
|
||||
|
||||
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
|
||||
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
|
||||
If multiple pins are to be locked, use logical OR '|' to separate them.
|
||||
*/
|
||||
void gpio_port_config_lock(u32 gpioport, u16 gpios)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
/* Special "Lock Key Writing Sequence", see datasheet. */
|
||||
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
|
||||
GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */
|
||||
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
|
||||
reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
|
||||
reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
|
||||
|
||||
/* Tell the compiler the variable is actually used. It will get optimized out anyways. */
|
||||
reg32 = reg32;
|
||||
|
||||
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief Map the EVENTOUT signal
|
||||
|
||||
|
|
|
|||
|
|
@ -28,9 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
|||
-ffunction-sections -fdata-sections -MD -DSTM32F2
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
OBJS = rcc.o gpio2.o usart.o spi.o flash.o \
|
||||
i2c.o exti2.o timer.o
|
||||
OBJS = rcc.o gpio.o usart.o spi.o flash.o \
|
||||
i2c.o exti2.o timer.o \
|
||||
gpio_common_all.o gpio_common_f24.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
include ../../Makefile.include
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
/** @defgroup gpio_file GPIO
|
||||
|
||||
@ingroup STM32F2xx
|
||||
|
||||
@brief <b>libopencm3 STM32F2xx General Purpose I/O</b>
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/gpio.h>
|
||||
#include <libopencm3/stm32/common/gpio_common_f24.h>
|
||||
|
||||
|
|
@ -29,11 +29,12 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
|||
-ffunction-sections -fdata-sections -MD -DSTM32F4
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
OBJS = rcc.o gpio2.o usart.o spi.o flash.o \
|
||||
OBJS = rcc.o gpio.o usart.o spi.o flash.o \
|
||||
i2c.o exti2.o pwr.o timer.o \
|
||||
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
|
||||
usb_f207.o adc.o dma.o
|
||||
usb_f207.o adc.o dma.o \
|
||||
gpio_common_all.o gpio_common_f24.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
include ../../Makefile.include
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
/** @defgroup gpio_file GPIO
|
||||
|
||||
@ingroup STM32F4xx
|
||||
|
||||
@brief <b>libopencm3 STM32F4xx General Purpose I/O</b>
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/gpio.h>
|
||||
#include <libopencm3/stm32/common/gpio_common_f24.h>
|
||||
|
||||
|
|
@ -1,8 +1,14 @@
|
|||
/** @defgroup gpio_file GPIO
|
||||
|
||||
@ingroup STM32F2xx
|
||||
|
||||
@brief <b>libopencm3 STM32F2xx General Purpose I/O</b>
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
|
|
@ -148,3 +154,4 @@ void gpio_port_config_lock(u32 gpioport, u16 gpios)
|
|||
|
||||
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue