samd: overhaul doxygen
This commit is contained in:
Karl Palsson
parent
b57dbc5429
commit
458a0553a8
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/** @defgroup peripheral_apis Peripheral APIs
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* APIs for device peripherals
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*/
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/** @defgroup SAMD_defines SAMD Defines
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* Defined Constants and Types for the SAMD series.
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* @copyright SPDX: LGPL-3.0-or-later
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*/
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@ -1,29 +1,12 @@
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/** @defgroup gpio_defines
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/** @defgroup port_defines IO Port Definitions
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*
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* #ingroup SAMD_defines
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* @ingroup SAMD_defines
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*
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* @brief Defined Constants and Types for the SAMD Port controler
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* @brief Defined Constants and Types for the SAMD Port controller
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2016 Karl Palsson <karlp@tweak.net.au>
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* Copyright (C) 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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* @copyright SPDX: LGPL-3.0-or-later
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* @author 2016 Karl Palsson <karlp@tweak.net.au>
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* @author 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*/
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#pragma once
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@ -40,7 +23,6 @@
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/* GPIO number definitions (for convenience) */
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/** @defgroup gpio_pin_id GPIO Pin Identifiers
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@ingroup gpio_defines
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@{*/
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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@ -79,7 +61,6 @@
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/* GPIO mux definitions (for convenience) */
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/** @defgroup gpio_mux GPIO mux configuration
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@ingroup gpio_mux
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@{*/
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enum port_mux {
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PORT_PMUX_FUN_A = 0,
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@ -94,46 +75,48 @@ enum port_mux {
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};
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/**@}*/
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/* --- PORT registers ----------------------------------------------------- */
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/* Direction register */
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/** @defgroup port_registers PORT Registers
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* @{
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*/
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/** Direction register */
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#define PORT_DIR(port) MMIO32((port) + 0x0000)
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/* Direction clear register */
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/** Direction clear register */
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#define PORT_DIRCLR(port) MMIO32((port) + 0x0004)
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/* Direction set register */
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/** Direction set register */
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#define PORT_DIRSET(port) MMIO32((port) + 0x0008)
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/* Direction toggle register */
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/** Direction toggle register */
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#define PORT_DIRTGL(port) MMIO32((port) + 0x000c)
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/* output register */
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/** output register */
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#define PORT_OUT(port) MMIO32((port) + 0x0010)
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/* output clear register */
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/** output clear register */
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#define PORT_OUTCLR(port) MMIO32((port) + 0x0014)
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/* output set register */
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/** output set register */
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#define PORT_OUTSET(port) MMIO32((port) + 0x0018)
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/* output toggle register */
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/** output toggle register */
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#define PORT_OUTTGL(port) MMIO32((port) + 0x001c)
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/* input register */
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/** input register */
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#define PORT_IN(port) MMIO32((port) + 0x0020)
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/* Control register */
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/** Control register */
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#define PORT_CTRL(port) MMIO32((port) + 0x0024)
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/* Write configuration register */
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/** Write configuration register */
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#define PORT_WRCONFIG(port) MMIO32((port) + 0x0028)
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/* Peripheral multiplexing registers */
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/** Peripheral multiplexing registers */
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#define PORT_PMUX(port, n) MMIO8((port) + 0x0030 + (n))
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/* Pin configuration registers */
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/** Pin configuration registers */
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#define PORT_PINCFG(port, n) MMIO8((port) + 0x0040 + (n))
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/**@}*/
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/* --- PORTx_DIR values ---------------------------------------------------- */
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@ -175,77 +158,66 @@ enum port_mux {
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/* PORTx_CTRL[31:0]: CTRLy[31:0]: Port input sampling mode [y=0..31] */
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/* --- PORTx_WRCONFIG values ----------------------------------------------- */
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/* HWSEL: Half word select: 0 [15:0], 1 [31:16] */
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/**@defgroup port_wrconfig_values PortX WRCONFIG Values
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* @{
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*/
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/** HWSEL: Half word select: 0 [15:0], 1 [31:16] */
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#define PORT_WRCONFIG_HWSEL (1 << 31)
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/* WRPINCFG: Write PINCFG: 1 to update pins for selected by PINMASK */
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/** WRPINCFG: Write PINCFG: 1 to update pins for selected by PINMASK */
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#define PORT_WRCONFIG_WRPINCFG (1 << 30)
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/* Bit 29: Reserved */
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/* WRPMUX: Write PMUX: 1 to update pins pmux for selected by PINMASK */
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/** WRPMUX: Write PMUX: 1 to update pins pmux for selected by PINMASK */
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#define PORT_WRCONFIG_WRPMUX (1 << 28)
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/* PMUX: Peripheral Multiplexing: determine pmux for pins selected by PINMASK */
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/** PMUX: Peripheral Multiplexing: determine pmux for pins selected by PINMASK */
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#define PORT_WRCONFIG_PMUX(mux) ((0xf & (mux)) << 24)
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/* Bit 23: Reserved */
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/* DRVSTR: Output Driver Strength Selection: determine strength for pins in PINMASK */
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/** DRVSTR: Output Driver Strength Selection: determine strength for pins in PINMASK */
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#define PORT_WRCONFIG_DRVSTR (1 << 22)
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/* Bit [21:19]: Reserved */
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/* PULLEN: Pull Enable: enable PINCFGy.PULLEN for pins in PINMASK */
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/** PULLEN: Pull Enable: enable PINCFGy.PULLEN for pins in PINMASK */
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#define PORT_WRCONFIG_PULLEN (1 << 18)
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/* INEN: Input Enable: enable PINCFGy.INEN for pins in PINMASK */
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/** INEN: Input Enable: enable PINCFGy.INEN for pins in PINMASK */
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#define PORT_WRCONFIG_INEN (1 << 17)
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/* PMUXEN: Peripheral Multiplexer Enable: enable PINCFGy.PMUXEN for pins in PINMASK */
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/** PMUXEN: Peripheral Multiplexer Enable: enable PINCFGy.PMUXEN for pins in PINMASK */
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#define PORT_WRCONFIG_PMUXEN (1 << 16)
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/* PINMASK: Pin Mask for Multiple Pin Configuration: select pins to be configured
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/** PINMASK: Pin Mask for Multiple Pin Configuration: select pins to be configured
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* [31:16] if HWSET=1, [15:0] if HWSET=0
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*/
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#define PORT_WRCONFIG_PINMASK(pins) ((0xffff & (pins)) << 0)
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/**@}*/
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/* --- PORTx_PMUX values --------------------------------------------------- */
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/* PMUXO: Peripheral Multiplexing for Odd-Numbered Pin: 2*x+1 pin multiplexing */
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/** PMUXO: Peripheral Multiplexing for Odd-Numbered Pin: 2*x+1 pin multiplexing */
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#define PORT_PMUX_PMUXO(mux) ((0xf & (mux)) << 4)
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/* PMUXE: Peripheral Multiplexing for Even-Numbered Pin: 2*x pin multiplexing */
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/** PMUXE: Peripheral Multiplexing for Even-Numbered Pin: 2*x pin multiplexing */
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#define PORT_PMUX_PMUXE(mux) ((0xf & (mux)) << 0)
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/* --- PORTx_PINCFGy values ------------------------------------------------ */
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/* Bit 7: Reserved */
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/* DRVSTR: Output Driver Strength Selection */
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/** DRVSTR: Output Driver Strength Selection */
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#define PORT_PINCFG_DRVSTR (1 << 6)
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/* Bit [5:3]: Reserved */
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/* PULLEN: Pull Enable */
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/** PULLEN: Pull Enable */
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#define PORT_PINCFG_PULLEN (1 << 2)
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/* INEN: Input Enable */
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/** INEN: Input Enable */
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#define PORT_PINCFG_INEN (1 << 1)
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/* PMUXEN: Peripheral Multiplexer Enable */
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/** PMUXEN: Peripheral Multiplexer Enable */
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#define PORT_PINCFG_PMUXEN (1 << 0)
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/* --- Convenience enums --------------------------------------------------- */
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/* GPIO mode definitions (for convenience) */
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/** @defgroup gpio_direction GPIO Pin direction
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@ingroup gpio_defines
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@li Input
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@li Output
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@li InOut
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@{*/
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#define GPIO_MODE_INPUT 0x00
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#define GPIO_MODE_OUTPUT 0x01
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@ -253,7 +225,6 @@ enum port_mux {
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/**@}*/
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/** @defgroup gpio_cnf GPIO mode configuration
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@ingroup gpio_defines
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@li Float
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@li PullDown
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@li PullUp
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@ -265,16 +236,10 @@ enum port_mux {
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#define GPIO_CNF_AF 0x03
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/**@}*/
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint32_t gpios);
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void gpio_set_af(uint32_t gpioport, uint8_t af, uint32_t gpios);
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/** @ingroup gpio_control
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* @{ */
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void gpio_set(uint32_t gpioport, uint32_t gpios);
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void gpio_clear(uint32_t gpioport, uint32_t gpios);
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uint32_t gpio_get(uint32_t gpioport, uint32_t gpios);
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@ -1,32 +1,9 @@
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/** @defgroup gpio_defines
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*
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* @ingroup SAMD
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*
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/** @addtogroup port_file IO Port API
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* @ingroup peripheral_apis
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* @brief <b>Access functions for the SAMD I/O Controller</b>
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*
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* @date 10 April 2020
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*
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* LGPL License Terms @ref lgpl_license
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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* @copyright SPDX: LGPL-3.0-or-later
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* @author 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*/
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/**@{*/
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@ -43,7 +20,6 @@
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* @param[in] gpios Any combinaison of pins may be
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* specified by OR'ing then together.
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*/
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void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint32_t gpios)
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{
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uint32_t reg = PORT_WRCONFIG_WRPINCFG;
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