Cosmetic and coding style changes.
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dd0548ee2b
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4390abfd95
125
lib/rcc.c
125
lib/rcc.c
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@ -5,7 +5,6 @@
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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@ -329,95 +328,99 @@ u32 rcc_system_clock_source(void)
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* These functions are setting up the whole clock system for the most common
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* input clock and output clock configurations.
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*/
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void rcc_clock_setup_in_hsi_out_64mhz(void){
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void rcc_clock_setup_in_hsi_out_64mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* enable Internal High Speed Oscillator */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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/*
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* set prescalers for AHB, ADC, ABP1, ABP2
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* make this before touching the PLL (why?)
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(HPRE_SYSCLK_NODIV); /* Max 72MHz */
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rcc_set_adcpre(ADCPRE_PLCK2_DIV8); /* Max 14MHz */
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rcc_set_ppre1(PPRE1_HCLK_DIV2); /* Max 36MHz */
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rcc_set_ppre2(PPRE2_HCLK_NODIV); /* Max 72MHz */
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rcc_set_hpre(HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(ADCPRE_PLCK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/* sysclk is running with 64MHz -> 2 Waitstates
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/*
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* Sysclk is running with 64MHz -> 2 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_2WS);
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flash_set_ws(FLASH_LATENCY_2WS);
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/* Set the PLL multiplication factor to 16.
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* -> 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz
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/*
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* Set the PLL multiplication factor to 16.
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* 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz
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*/
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL16);
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL16);
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/* Select HSI/2 as PLL source. */
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rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2);
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/* Select HSI/2 as PLL source. */
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rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void){
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* enable Internal High Speed Oscillator */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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/* Enable external high-speed oscillator 8MHz. */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
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/* enable External High Speed Oscillator 8MHz */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
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/* set prescalers for AHB, ADC, ABP1, ABP2
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* do this before touching the PLL (why?)
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(HPRE_SYSCLK_NODIV); // Max 72MHz
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rcc_set_adcpre(ADCPRE_PLCK2_DIV8); // Max 14MHz
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rcc_set_ppre1(PPRE1_HCLK_DIV2); // Max 36MHz
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rcc_set_ppre2(PPRE2_HCLK_NODIV); // Max 72MHz
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rcc_set_hpre(HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(ADCPRE_PLCK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/* sysclk runs with 72MHz -> 2 Waitstates
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_2WS);
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flash_set_ws(FLASH_LATENCY_2WS);
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/* Set the PLL multiplication factor to 9.
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* -> 8MHz (external) * 9 (multiplier) = 72MHz
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/*
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* Set the PLL multiplication factor to 9.
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* 8MHz (external) * 9 (multiplier) = 72MHz
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*/
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL10);
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL10);
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/* Select HSE as PLL source. */
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rcc_set_pll_source(PLLSRC_HSE_CLK);
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/* Select HSE as PLL source. */
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rcc_set_pll_source(PLLSRC_HSE_CLK);
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/* external frequency undivided before entering pll
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* (only valid/needed for HSE)
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/*
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* External frequency undivided before entering PLL
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* (only valid/needed for HSE).
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*/
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rcc_set_pllxtpre(PLLXTPRE_HSE_CLK);
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rcc_set_pllxtpre(PLLXTPRE_HSE_CLK);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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}
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