Merge remote-tracking branch 'mossman/master'
Merging Pull request #9 by mossman and co. Adding preliminary support for LPC43xx.
This commit is contained in:
commit
40e0e675ca
4
Makefile
4
Makefile
|
@ -25,7 +25,7 @@ LIBDIR = $(DESTDIR)/$(PREFIX)/lib
|
|||
SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts
|
||||
INSTALL = install
|
||||
|
||||
TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lm3s
|
||||
TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s
|
||||
|
||||
# Be silent per default, but 'make V=1' will show all compiler calls.
|
||||
ifneq ($(V),1)
|
||||
|
@ -62,8 +62,10 @@ install: lib
|
|||
$(Q)cp -r include/libopencm3/* $(INCDIR)/libopencm3
|
||||
@printf " INSTALL libs\n"
|
||||
$(Q)$(INSTALL) -m 0644 lib/*/*/*.a $(LIBDIR)
|
||||
$(Q)$(INSTALL) -m 0644 lib/*/*.a $(LIBDIR)
|
||||
@printf " INSTALL ldscripts\n"
|
||||
$(Q)$(INSTALL) -m 0644 lib/*/*/*.ld $(LIBDIR)
|
||||
$(Q)$(INSTALL) -m 0644 lib/*/*.ld $(LIBDIR)
|
||||
@printf " INSTALL scripts\n"
|
||||
$(Q)$(INSTALL) -m 0644 scripts/* $(SHAREDIR)
|
||||
|
||||
|
|
|
@ -0,0 +1,127 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
## Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||
## Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
## Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
PREFIX ?= arm-none-eabi
|
||||
#PREFIX ?= arm-elf
|
||||
CC = $(PREFIX)-gcc
|
||||
LD = $(PREFIX)-gcc
|
||||
OBJCOPY = $(PREFIX)-objcopy
|
||||
OBJDUMP = $(PREFIX)-objdump
|
||||
GDB = $(PREFIX)-gdb
|
||||
# Uncomment this line if you want to use the installed (not local) library.
|
||||
# TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX)
|
||||
TOOLCHAIN_DIR = ../../../..
|
||||
CFLAGS += -O2 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
|
||||
-mcpu=cortex-m4 -mthumb -MD \
|
||||
-mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||
LDSCRIPT ?= $(BINARY).ld
|
||||
LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lpc43xx \
|
||||
-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections -Xlinker -Map=$(BINARY).map
|
||||
OBJS += $(BINARY).o
|
||||
|
||||
OOCD ?= openocd
|
||||
OOCD_INTERFACE ?= flossjtag
|
||||
OOCD_BOARD ?= olimex_stm32_h103
|
||||
|
||||
# Be silent per default, but 'make V=1' will show all compiler calls.
|
||||
ifneq ($(V),1)
|
||||
Q := @
|
||||
NULL := 2>/dev/null
|
||||
else
|
||||
LDFLAGS += -Wl,--print-gc-sections
|
||||
endif
|
||||
|
||||
.SUFFIXES: .elf .bin .hex .srec .list .images
|
||||
.SECONDEXPANSION:
|
||||
.SECONDARY:
|
||||
|
||||
all: images
|
||||
|
||||
images: $(BINARY).images
|
||||
flash: $(BINARY).flash
|
||||
|
||||
%.images: %.bin %.hex %.srec %.list
|
||||
@#echo "*** $* images generated ***"
|
||||
|
||||
%.bin: %.elf
|
||||
@#printf " OBJCOPY $(*).bin\n"
|
||||
$(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin
|
||||
|
||||
%.hex: %.elf
|
||||
@#printf " OBJCOPY $(*).hex\n"
|
||||
$(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex
|
||||
|
||||
%.srec: %.elf
|
||||
@#printf " OBJCOPY $(*).srec\n"
|
||||
$(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec
|
||||
|
||||
%.list: %.elf
|
||||
@#printf " OBJDUMP $(*).list\n"
|
||||
$(Q)$(OBJDUMP) -S $(*).elf > $(*).list
|
||||
|
||||
%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/lpc43xx/libopencm3_lpc43xx.a
|
||||
@#printf " LD $(subst $(shell pwd)/,,$(@))\n"
|
||||
$(Q)$(LD) $(LDFLAGS) -o $(*).elf $(OBJS) -lopencm3_lpc43xx
|
||||
|
||||
%.o: %.c Makefile
|
||||
@#printf " CC $(subst $(shell pwd)/,,$(@))\n"
|
||||
$(Q)$(CC) $(CFLAGS) -o $@ -c $<
|
||||
|
||||
clean:
|
||||
$(Q)rm -f *.o
|
||||
$(Q)rm -f *.d
|
||||
$(Q)rm -f *.elf
|
||||
$(Q)rm -f *.bin
|
||||
$(Q)rm -f *.hex
|
||||
$(Q)rm -f *.srec
|
||||
$(Q)rm -f *.list
|
||||
$(Q)rm -f *.map
|
||||
|
||||
# FIXME: Replace STM32 stuff with proper LPC43XX OpenOCD support later.
|
||||
ifeq ($(OOCD_SERIAL),)
|
||||
%.flash: %.hex
|
||||
@printf " FLASH $<\n"
|
||||
@# IMPORTANT: Don't use "resume", only "reset" will work correctly!
|
||||
$(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \
|
||||
-f board/$(OOCD_BOARD).cfg \
|
||||
-c "init" -c "reset init" \
|
||||
-c "stm32x mass_erase 0" \
|
||||
-c "flash write_image $(*).hex" \
|
||||
-c "reset" \
|
||||
-c "shutdown" $(NULL)
|
||||
else
|
||||
%.flash: %.hex
|
||||
@printf " FLASH $<\n"
|
||||
@# IMPORTANT: Don't use "resume", only "reset" will work correctly!
|
||||
$(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \
|
||||
-f board/$(OOCD_BOARD).cfg \
|
||||
-c "ft2232_serial $(OOCD_SERIAL)" \
|
||||
-c "init" -c "reset init" \
|
||||
-c "stm32x mass_erase 0" \
|
||||
-c "flash write_image $(*).hex" \
|
||||
-c "reset" \
|
||||
-c "shutdown" $(NULL)
|
||||
endif
|
||||
|
||||
.PHONY: images clean
|
||||
|
||||
-include $(OBJS:.o=.d)
|
|
@ -0,0 +1,3 @@
|
|||
These example programs are written for the Diolan LPC-4350-DB1:
|
||||
|
||||
http://www.diolan.com/lpc4350-features.html
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 64K SRAM). */
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
/* rom is really the shadow region that points to SPI flash or elsewhere */
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M
|
||||
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||
/* there are some additional RAM regions */
|
||||
}
|
||||
|
||||
/* Include the common ld script. */
|
||||
INCLUDE libopencm3_lpc43xx.ld
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
BINARY = miniblink
|
||||
|
||||
LDSCRIPT = ../diolan-lpc-4350-db1.ld
|
||||
|
||||
include ../../Makefile.include
|
|
@ -0,0 +1,11 @@
|
|||
------------------------------------------------------------------------------
|
||||
README
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
This is the smallest-possible example program using libopencm3.
|
||||
|
||||
It's intended for the Diolan LPC-4350-DB1:
|
||||
|
||||
http://www.diolan.com/lpc4350-features.html
|
||||
|
||||
It should blink D2 on the board.
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
|
||||
void gpio_setup(void)
|
||||
{
|
||||
GPIO0_DIR |= (1 << 5); /* Configure GPIO0[5] (P6_6) as output. */
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
gpio_setup();
|
||||
|
||||
/* Blink D2 on the board. */
|
||||
while (1) {
|
||||
|
||||
gpio_set(GPIO0, GPIOPIN5); /* LED on */
|
||||
for (i = 0; i < 800000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
gpio_clear(GPIO0, GPIOPIN5); /* LED off */
|
||||
for (i = 0; i < 800000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,4 @@
|
|||
These example programs are written for the Jellybean development board from the
|
||||
HackRF project:
|
||||
|
||||
https://github.com/mossmann/hackrf
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
BINARY = i2cdemo
|
||||
|
||||
LDSCRIPT = ../jellybean-lpc4330.ld
|
||||
|
||||
include ../../Makefile.include
|
|
@ -0,0 +1,15 @@
|
|||
------------------------------------------------------------------------------
|
||||
README
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
This program exercises the I2C peripheral on Jellybean's LPC43xx. You can
|
||||
scope SCL on P6 pin 3 and SDA on P6 pin 5. If Lemondrop is connected, LED1
|
||||
will illuminate if I2C communication to the Si5351C on Lemondrop is successful.
|
||||
|
||||
Required Lemondrop -> Jellybean connections:
|
||||
|
||||
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
|
||||
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
|
||||
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
|
||||
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
|
||||
GND: Lemondrop P5 -> Jellybean P13
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
#include <libopencm3/lpc43xx/i2c.h>
|
||||
|
||||
#include "../jellybean_conf.h"
|
||||
|
||||
void gpio_setup(void)
|
||||
{
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure all GPIO as Input (safe state) */
|
||||
GPIO0_DIR = 0;
|
||||
GPIO1_DIR = 0;
|
||||
GPIO2_DIR = 0;
|
||||
GPIO3_DIR = 0;
|
||||
GPIO4_DIR = 0;
|
||||
GPIO5_DIR = 0;
|
||||
GPIO6_DIR = 0;
|
||||
GPIO7_DIR = 0;
|
||||
|
||||
/* Configure GPIO as Output */
|
||||
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
||||
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
|
||||
}
|
||||
|
||||
#define SI5351C_I2C_ADDR (0x60 << 1)
|
||||
|
||||
/* write to single register */
|
||||
void si5351c_write_reg(uint8_t reg, uint8_t val)
|
||||
{
|
||||
i2c0_tx_start();
|
||||
i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
|
||||
i2c0_tx_byte(reg);
|
||||
i2c0_tx_byte(val);
|
||||
i2c0_stop();
|
||||
}
|
||||
|
||||
/* read single register */
|
||||
uint8_t si5351c_read_reg(uint8_t reg)
|
||||
{
|
||||
uint8_t val;
|
||||
|
||||
/* set register address with write */
|
||||
i2c0_tx_start();
|
||||
i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
|
||||
i2c0_tx_byte(reg);
|
||||
|
||||
/* read the value */
|
||||
i2c0_tx_start();
|
||||
i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_READ);
|
||||
val = i2c0_rx_byte();
|
||||
i2c0_stop();
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
gpio_setup();
|
||||
i2c0_init();
|
||||
|
||||
gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
|
||||
|
||||
while (1) {
|
||||
if (si5351c_read_reg(0) == 0x10)
|
||||
gpio_set(GPIO2, GPIOPIN1); /* LED on */
|
||||
else
|
||||
gpio_clear(GPIO2, GPIOPIN1); /* LED off */
|
||||
|
||||
for (i = 0; i < 1000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 264K SRAM). */
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
/* rom is really the shadow region that points to SPI flash or elsewhere */
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M
|
||||
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||
/* there are some additional RAM regions */
|
||||
}
|
||||
|
||||
/* Include the common ld script. */
|
||||
INCLUDE libopencm3_lpc43xx.ld
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 264K SRAM). */
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
/* Physical address in Flash used to copy Code from Flash to RAM */
|
||||
rom_flash (rx) : ORIGIN = 0x80000000, LENGTH = 1M
|
||||
/* rom is really the shadow region that points to SPI flash or elsewhere */
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M
|
||||
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||
/* there are some additional RAM regions for data */
|
||||
ram_data (rw) : ORIGIN = 0x10080000, LENGTH = 72K
|
||||
}
|
||||
|
||||
/* Include the common ld script. */
|
||||
INCLUDE libopencm3_lpc43xx_rom_to_ram.ld
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __JELLYBEAN_CONF_H
|
||||
#define __JELLYBEAN_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
|
||||
/*
|
||||
* JellyBean SCU PinMux
|
||||
*/
|
||||
|
||||
/* GPIO Output PinMux */
|
||||
#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */
|
||||
#define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */
|
||||
#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */
|
||||
|
||||
#define SCU_PINMUX_EN1V8 (P6_10) /* GPIO3[6] on P6_10 */
|
||||
|
||||
/* GPIO Input PinMux */
|
||||
#define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */
|
||||
#define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */
|
||||
#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
|
||||
#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
|
||||
|
||||
/* SSP1 Peripheral PinMux */
|
||||
#define SCU_SSP1_MISO (P1_3) /* P1_3 */
|
||||
#define SCU_SSP1_MOSI (P1_4) /* P1_4 */
|
||||
#define SCU_SSP1_SCK (P1_19) /* P1_19 */
|
||||
#define SCU_SSP1_SSEL (P1_20) /* P1_20 */
|
||||
|
||||
/* TODO add other Pins */
|
||||
|
||||
/*
|
||||
* JellyBean GPIO Pin
|
||||
*/
|
||||
/* GPIO Output */
|
||||
#define PIN_LED1 (BIT1) /* GPIO2[1] on P4_1 */
|
||||
#define PIN_LED2 (BIT2) /* GPIO2[2] on P4_2 */
|
||||
#define PIN_LED3 (BIT8) /* GPIO2[8] on P6_12 */
|
||||
#define PORT_LED1_3 (GPIO2) /* PORT for LED1, 2 & 3 */
|
||||
|
||||
#define PIN_EN1V8 (BIT6) /* GPIO3[6] on P6_10 */
|
||||
#define PORT_EN1V8 (GPIO3)
|
||||
|
||||
/* GPIO Input */
|
||||
#define PIN_BOOT0 (BIT8) /* GPIO0[8] on P1_1 */
|
||||
#define PIN_BOOT1 (BIT9) /* GPIO0[9] on P1_2 */
|
||||
#define PIN_BOOT2 (BIT7) /* GPIO5[7] on P2_8 */
|
||||
#define PIN_BOOT3 (BIT10) /* GPIO1[10] on P2_9 */
|
||||
|
||||
/* Read GPIO Pin */
|
||||
#define BOOT0_STATE ( (GPIO0_PIN & PIN_BOOT0)==PIN_BOOT0 )
|
||||
#define BOOT1_STATE ( (GPIO0_PIN & PIN_BOOT1)==PIN_BOOT1 )
|
||||
#define BOOT2_STATE ( (GPIO5_PIN & PIN_BOOT2)==PIN_BOOT2 )
|
||||
#define BOOT3_STATE ( (GPIO1_PIN & PIN_BOOT3)==PIN_BOOT3 )
|
||||
|
||||
/* TODO add other Pins */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
BINARY = miniblink
|
||||
|
||||
LDSCRIPT = ../jellybean-lpc4330.ld
|
||||
|
||||
include ../../Makefile.include
|
|
@ -0,0 +1,11 @@
|
|||
------------------------------------------------------------------------------
|
||||
README
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
This is the smallest-possible example program using libopencm3.
|
||||
|
||||
It's intended for the Jellybean development board from the HackRF project:
|
||||
|
||||
https://github.com/mossmann/hackrf
|
||||
|
||||
It should blink LED1 on the board.
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
|
||||
#include "../jellybean_conf.h"
|
||||
|
||||
void gpio_setup(void)
|
||||
{
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure all GPIO as Input (safe state) */
|
||||
GPIO0_DIR = 0;
|
||||
GPIO1_DIR = 0;
|
||||
GPIO2_DIR = 0;
|
||||
GPIO3_DIR = 0;
|
||||
GPIO4_DIR = 0;
|
||||
GPIO5_DIR = 0;
|
||||
GPIO6_DIR = 0;
|
||||
GPIO7_DIR = 0;
|
||||
|
||||
/* Configure GPIO as Output */
|
||||
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
||||
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
|
||||
}
|
||||
|
||||
u32 boot0, boot1, boot2, boot3;
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int i;
|
||||
gpio_setup();
|
||||
|
||||
/* Set 1V8 */
|
||||
gpio_set(PORT_EN1V8, PIN_EN1V8);
|
||||
|
||||
/* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */
|
||||
while (1)
|
||||
{
|
||||
boot0 = BOOT0_STATE;
|
||||
boot1 = BOOT1_STATE;
|
||||
boot2 = BOOT2_STATE;
|
||||
boot3 = BOOT3_STATE;
|
||||
|
||||
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
|
||||
for (i = 0; i < 2000000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */
|
||||
for (i = 0; i < 2000000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
BINARY = miniblink
|
||||
|
||||
LDSCRIPT = ../jellybean-lpc4330_rom_to_ram.ld
|
||||
|
||||
include ../../Makefile.include
|
|
@ -0,0 +1,12 @@
|
|||
------------------------------------------------------------------------------
|
||||
README
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
This is the smallest-possible example program using libopencm3.
|
||||
|
||||
It's intended for the Jellybean development board from the HackRF project:
|
||||
|
||||
https://github.com/mossmann/hackrf
|
||||
|
||||
It should blink LED1 on the board.
|
||||
This example copy the Code from ROM to RAM and execute code from RAM.
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
|
||||
#include "../jellybean_conf.h"
|
||||
|
||||
void gpio_setup(void)
|
||||
{
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure all GPIO as Input (safe state) */
|
||||
GPIO0_DIR = 0;
|
||||
GPIO1_DIR = 0;
|
||||
GPIO2_DIR = 0;
|
||||
GPIO3_DIR = 0;
|
||||
GPIO4_DIR = 0;
|
||||
GPIO5_DIR = 0;
|
||||
GPIO6_DIR = 0;
|
||||
GPIO7_DIR = 0;
|
||||
|
||||
/* Configure GPIO as Output */
|
||||
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
||||
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
|
||||
}
|
||||
|
||||
u32 boot0, boot1, boot2, boot3;
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int i;
|
||||
gpio_setup();
|
||||
|
||||
/* Set 1V8 */
|
||||
gpio_set(PORT_EN1V8, PIN_EN1V8);
|
||||
|
||||
/* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */
|
||||
while (1)
|
||||
{
|
||||
boot0 = BOOT0_STATE;
|
||||
boot1 = BOOT1_STATE;
|
||||
boot2 = BOOT2_STATE;
|
||||
boot3 = BOOT3_STATE;
|
||||
|
||||
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
|
||||
for (i = 0; i < 2000000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */
|
||||
for (i = 0; i < 2000000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
BINARY = sspdemo
|
||||
|
||||
LDSCRIPT = ../jellybean-lpc4330.ld
|
||||
|
||||
include ../../Makefile.include
|
|
@ -0,0 +1,48 @@
|
|||
------------------------------------------------------------------------------
|
||||
README
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
This program exercises the SSP1 peripheral on Jellybean's LPC43xx.
|
||||
|
||||
Jellybean (connector)
|
||||
P9 SPI
|
||||
|-----------------|
|
||||
| Pin2 Pin4 Pin6 |
|
||||
||------| |
|
||||
|| Pin1 |Pin3 Pin5 |
|
||||
||------|----------|
|
||||
|-------|
|
||||
|
||||
SSP1_MISO: Jellybean P9 SPI Pin6
|
||||
SSP1_MOSI: Jellybean P9 SPI Pin4
|
||||
SSP1_SCK: Jellybean P9 SPI Pin2
|
||||
SSP1_SSEL: Jellybean P9 SPI Pin3
|
||||
GND: Can be connected to P12 SD Pin1
|
||||
|
||||
PCLK clock source is PLL1 288MHz (from IRC 96MHz boot from SPIFI)
|
||||
Freq = PCLK / (CPSDVSR * [SCR+1]).
|
||||
|
||||
By default (CPSDVSR=0 => Means MAX Divisor)
|
||||
SSP1->CR0->SCR = 0x00 => CLK Freq 1.126MHz
|
||||
SSP1->CR0->SCR = 0x01 => MOSI Freq 566.9KHz
|
||||
...
|
||||
|
||||
Test Oscilloscpe:
|
||||
SCR=0, CPSDVSR=32 => CLK 9.025MHz
|
||||
SCR=1, CPSDVSR=2 => CLK 73MHz
|
||||
SCR=2, CPSDVSR=2 => CLK 49MHz
|
||||
SCR=4, CPSDVSR=2 => CLK 29MHz
|
||||
SCR=8, CPSDVSR=2 => CLK 16MHz
|
||||
SCR=16, CPSDVSR=2 => CLK 8.5MHz
|
||||
SCR=32, CPSDVSR=2 => CLK 4.386MHz
|
||||
SCR=64, CPSDVSR=2 => CLK 2.227MHz
|
||||
SCR=1, CPSDVSR=64 => CLK 2.262MHz
|
||||
|
||||
Theory:
|
||||
SCR=0, CPSDVSR=32 => 288MHz / (32*(0+1) = 9MHz
|
||||
SCR=1, CPSDVSR=2 => 288MHz / (2*(1+1) = 72MHz
|
||||
SCR=4, CPSDVSR=2 => 288MHz / (2*(4+1) = 28.8MHz
|
||||
SCR=32, CPSDVSR=2 => 288MHz / (2*(32+1) = 4.364MHz
|
||||
SCR=64, CPSDVSR=2 => 288MHz / (2*(64+1)) = 2.2154MHz
|
||||
SCR=128, CPSDVSR=2 => 288MHz / (2*(128+1)) = 1.116MHz
|
||||
SCR=1, CPSDVSR=64 => 288MHz / (64*(1+1)) = 2.25MHz
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include <libopencm3/lpc43xx/cgu.h>
|
||||
#include <libopencm3/lpc43xx/ssp.h>
|
||||
|
||||
#include "../jellybean_conf.h"
|
||||
|
||||
void gpio_setup(void)
|
||||
{
|
||||
/* Configure all GPIO as Input (safe state) */
|
||||
GPIO0_DIR = 0;
|
||||
GPIO1_DIR = 0;
|
||||
GPIO2_DIR = 0;
|
||||
GPIO3_DIR = 0;
|
||||
GPIO4_DIR = 0;
|
||||
GPIO5_DIR = 0;
|
||||
GPIO6_DIR = 0;
|
||||
GPIO7_DIR = 0;
|
||||
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
|
||||
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
|
||||
/* Configure GPIO as Output */
|
||||
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
||||
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int i;
|
||||
u8 ssp_val;
|
||||
u8 serial_clock_rate;
|
||||
u8 clock_prescale_rate;
|
||||
|
||||
gpio_setup();
|
||||
|
||||
/* Freq About 1.12MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=288MHz */
|
||||
clock_prescale_rate = 2;
|
||||
serial_clock_rate = 128;
|
||||
|
||||
ssp_init(SSP1_NUM,
|
||||
SSP_DATA_8BITS,
|
||||
SSP_FRAME_SPI,
|
||||
SSP_CPOL_0_CPHA_0,
|
||||
serial_clock_rate,
|
||||
clock_prescale_rate,
|
||||
SSP_MODE_NORMAL,
|
||||
SSP_MASTER,
|
||||
SSP_SLAVE_OUT_ENABLE);
|
||||
|
||||
ssp_val = 0x0;
|
||||
|
||||
while (1) {
|
||||
|
||||
ssp_write(SSP1_NUM, (u16)ssp_val);
|
||||
|
||||
gpio_set(GPIO2, GPIOPIN1); /* LED on */
|
||||
|
||||
for (i = 0; i < 1000; i++) /* Wait a bit. */
|
||||
__asm__("nop");
|
||||
|
||||
gpio_clear(GPIO2, GPIOPIN1); /* LED off */
|
||||
|
||||
ssp_val++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
BINARY = systickdemo
|
||||
|
||||
LDSCRIPT = ../jellybean-lpc4330.ld
|
||||
|
||||
include ../../Makefile.include
|
|
@ -0,0 +1,8 @@
|
|||
------------------------------------------------------------------------------
|
||||
README
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
This program exercises the SysTick Interrupt of ARM CortexM4 on Jellybean's LPC43xx.
|
||||
It also enable Cycle Counter to be used for accurate delay independant from Clock Frequency.
|
||||
The Demo Use Cycle Counter and SysTick Interrupt to compute number of cycles executed per second.
|
||||
The result is LED1/2 & 3 Blink with an accurate 1s Period (using SysTick) (Checked visualy and with Oscilloscope).
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include <libopencm3/lpc43xx/cgu.h>
|
||||
#include <libopencm3/lpc43xx/nvic.h>
|
||||
#include <libopencm3/lpc43xx/systick.h>
|
||||
#include <libopencm3/cm3/scs.h>
|
||||
|
||||
#include "../jellybean_conf.h"
|
||||
|
||||
/* Global counter incremented by SysTick Interrupt each millisecond */
|
||||
volatile u32 g_ulSysTickCount;
|
||||
u32 g_NbCyclePerSecond;
|
||||
|
||||
void gpio_setup(void)
|
||||
{
|
||||
/* Configure all GPIO as Input (safe state) */
|
||||
GPIO0_DIR = 0;
|
||||
GPIO1_DIR = 0;
|
||||
GPIO2_DIR = 0;
|
||||
GPIO3_DIR = 0;
|
||||
GPIO4_DIR = 0;
|
||||
GPIO5_DIR = 0;
|
||||
GPIO6_DIR = 0;
|
||||
GPIO7_DIR = 0;
|
||||
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
|
||||
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
|
||||
/* Configure GPIO as Output */
|
||||
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
||||
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
|
||||
}
|
||||
|
||||
void systick_setup(void)
|
||||
{
|
||||
u32 systick_reload_val;
|
||||
g_ulSysTickCount = 0;
|
||||
|
||||
/* Disable IRQ globally */
|
||||
asm volatile ("cpsid i");
|
||||
|
||||
/* Set processor Clock as Source Clock */
|
||||
systick_set_clocksource(STK_CTRL_CLKSOURCE);
|
||||
|
||||
/* Get SysTick calibration value to obtain by default 1 tick = 10ms */
|
||||
systick_reload_val = systick_get_calib();
|
||||
/*
|
||||
* Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*8=96MHz
|
||||
* Fix the Calibration value bu multiplication by 8
|
||||
*/
|
||||
systick_reload_val = (systick_reload_val*8);
|
||||
|
||||
/* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */
|
||||
systick_reload_val = systick_reload_val/10;
|
||||
systick_set_reload(systick_reload_val);
|
||||
|
||||
systick_interrupt_enable();
|
||||
|
||||
/* Start counting. */
|
||||
systick_counter_enable();
|
||||
|
||||
/* Set SysTick Priority to maximum */
|
||||
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
|
||||
|
||||
/* Enable IRQ globally */
|
||||
asm volatile ("cpsie i");
|
||||
}
|
||||
|
||||
void scs_dwt_cycle_counter_enabled(void)
|
||||
{
|
||||
SCS_DEMCR |= SCS_DEMCR_TRCENA;
|
||||
SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA;
|
||||
}
|
||||
|
||||
u32 sys_tick_get_time_ms(void)
|
||||
{
|
||||
return g_ulSysTickCount;
|
||||
}
|
||||
|
||||
u32 sys_tick_delta_time_ms(u32 start, u32 end)
|
||||
{
|
||||
#define MAX_T_U32 ((2^32)-1)
|
||||
u32 diff;
|
||||
|
||||
if(end > start)
|
||||
{
|
||||
diff=end-start;
|
||||
}else
|
||||
{
|
||||
diff=MAX_T_U32-(start-end)+1;
|
||||
}
|
||||
|
||||
return diff;
|
||||
}
|
||||
|
||||
void sys_tick_wait_time_ms(u32 wait_ms)
|
||||
{
|
||||
u32 start, end;
|
||||
u32 tickms;
|
||||
|
||||
start = sys_tick_get_time_ms();
|
||||
|
||||
do
|
||||
{
|
||||
end = sys_tick_get_time_ms();
|
||||
tickms = sys_tick_delta_time_ms(start, end);
|
||||
}while(tickms < wait_ms);
|
||||
}
|
||||
|
||||
/* Called each 1ms/1000Hz by interrupt
|
||||
1) Count the number of cycle per second.
|
||||
2) Increment g_ulSysTickCount counter.
|
||||
*/
|
||||
void sys_tick_handler(void)
|
||||
{
|
||||
if(g_ulSysTickCount==0)
|
||||
{
|
||||
/* Clear Cycle Counter*/
|
||||
SCS_DWT_CYCCNT = 0;
|
||||
}else if(g_ulSysTickCount==1000)
|
||||
{
|
||||
/* Capture number of cycle elapsed during 1 second */
|
||||
g_NbCyclePerSecond = SCS_DWT_CYCCNT;
|
||||
}
|
||||
|
||||
g_ulSysTickCount++;
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
systick_setup();
|
||||
|
||||
gpio_setup();
|
||||
|
||||
/* SCS & Cycle Counter enabled (used to count number of cycles executed per second see g_NbCyclePerSecond */
|
||||
scs_dwt_cycle_counter_enabled();
|
||||
|
||||
while (1)
|
||||
{
|
||||
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
|
||||
|
||||
sys_tick_wait_time_ms(500);
|
||||
|
||||
gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */
|
||||
|
||||
sys_tick_wait_time_ms(500);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -38,6 +38,40 @@ typedef uint64_t u64;
|
|||
#define MMIO32(addr) (*(volatile u32 *)(addr))
|
||||
#define MMIO64(addr) (*(volatile u64 *)(addr))
|
||||
|
||||
/* Generic bit definition */
|
||||
#define BIT0 (1<<0)
|
||||
#define BIT1 (1<<1)
|
||||
#define BIT2 (1<<2)
|
||||
#define BIT3 (1<<3)
|
||||
#define BIT4 (1<<4)
|
||||
#define BIT5 (1<<5)
|
||||
#define BIT6 (1<<6)
|
||||
#define BIT7 (1<<7)
|
||||
#define BIT8 (1<<8)
|
||||
#define BIT9 (1<<9)
|
||||
#define BIT10 (1<<10)
|
||||
#define BIT11 (1<<11)
|
||||
#define BIT12 (1<<12)
|
||||
#define BIT13 (1<<13)
|
||||
#define BIT14 (1<<14)
|
||||
#define BIT15 (1<<15)
|
||||
#define BIT16 (1<<16)
|
||||
#define BIT17 (1<<17)
|
||||
#define BIT18 (1<<18)
|
||||
#define BIT19 (1<<19)
|
||||
#define BIT20 (1<<20)
|
||||
#define BIT21 (1<<21)
|
||||
#define BIT22 (1<<22)
|
||||
#define BIT23 (1<<23)
|
||||
#define BIT24 (1<<24)
|
||||
#define BIT25 (1<<25)
|
||||
#define BIT26 (1<<26)
|
||||
#define BIT27 (1<<27)
|
||||
#define BIT28 (1<<28)
|
||||
#define BIT29 (1<<29)
|
||||
#define BIT30 (1<<30)
|
||||
#define BIT31 (1<<31)
|
||||
|
||||
/* Main page for the doxygen-generated documentation: */
|
||||
|
||||
/**
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
|
@ -20,9 +21,85 @@
|
|||
#ifndef LIBOPENCM3_CM3_SCS_H
|
||||
#define LIBOPENCM3_CM3_SCS_H
|
||||
|
||||
/*
|
||||
* All the definition hereafter are generic for CortexMx ARMv7-M
|
||||
* See ARM document "ARMv7-M Architecture Reference Manual" for more details.
|
||||
* See also ARM document "ARM Compiler toolchain Developing Software for ARM Processors" for details on System Timer/SysTick.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for
|
||||
* configuration, status reporting and control. The SCS registers divide into the following groups:
|
||||
* - system control and identification
|
||||
* - the CPUID processor identification space
|
||||
* - system configuration and status
|
||||
* - fault reporting
|
||||
* - a system timer, SysTick
|
||||
* - a Nested Vectored Interrupt Controller (NVIC)
|
||||
* - a Protected Memory System Architecture (PMSA)
|
||||
* - system debug.
|
||||
*/
|
||||
|
||||
/* System Handler Priority 8 bits Registers, SHPR1/2/3 */
|
||||
/* Note: 12 8bit Registers */
|
||||
#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id)
|
||||
|
||||
/*
|
||||
* Debug Halting Control and Status Register (DHCSR).
|
||||
*
|
||||
* Purpose Controls halting debug.
|
||||
* Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system
|
||||
* is running with halting debug enabled is UNPREDICTABLE.
|
||||
* Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0.
|
||||
* - When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register.
|
||||
* - For more information about the use of DHCSR see Debug stepping on
|
||||
* page C1-824.
|
||||
* Configurations Always implemented.
|
||||
*/
|
||||
/* SCS_DHCSR register */
|
||||
#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
|
||||
/*
|
||||
* Debug Core Register Selector Register (DCRSR).
|
||||
*
|
||||
* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers,
|
||||
* special-purpose registers, and Floating-point extension registers. A write to DCRSR
|
||||
* specifies the register to transfer, whether the transfer is a read or a write, and starts
|
||||
* the transfer.
|
||||
* Usage constraints: Only accessible in Debug state.
|
||||
* Configurations Always implemented.
|
||||
*
|
||||
*/
|
||||
/* SCS_DCRS register */
|
||||
#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
|
||||
/*
|
||||
* Debug Core Register Data Register (DCRDR)
|
||||
*
|
||||
* Purpose With the DCRSR, see Debug Core Register Selector Register,
|
||||
* the DCRDR provides debug access to the ARM core registers,
|
||||
* special-purpose registers, and Floating-point extension registers. The
|
||||
* DCRDR is the data register for these accesses.
|
||||
* - Used on its own, the DCRDR provides a message passing resource between
|
||||
* an external debugger and a debug agent running on the processor.
|
||||
* Note:
|
||||
* The architecture does not define any handshaking mechanism for this use of DCRDR.
|
||||
* Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
|
||||
* particular transfers using the DCRSR and DCRDR.
|
||||
* Configurations Always implemented.
|
||||
*
|
||||
*/
|
||||
/* SCS_DCRDR register */
|
||||
#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
|
||||
/*
|
||||
* Debug Exception and Monitor Control Register (DEMCR).
|
||||
*
|
||||
* Purpose Manages vector catch behavior and DebugMonitor handling when debugging.
|
||||
* Usage constraints:
|
||||
* - Bits [23:16] provide DebugMonitor exception control.
|
||||
* - Bits [15:0] provide Debug state, halting debug, control.
|
||||
* Configurations Always implemented.
|
||||
*
|
||||
*/
|
||||
/* SCS_DEMCR register */
|
||||
#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
|
||||
|
||||
/* Debug Halting Control and Status Register (DHCSR) */
|
||||
|
@ -64,4 +141,169 @@
|
|||
/* Bits 3:1 - Reserved */
|
||||
#define SCS_DEMCR_VC_CORERESET (1 << 0)
|
||||
|
||||
/*
|
||||
* System Control Space (SCS) => System timer register support in the SCS.
|
||||
* To configure SysTick, load the interval required between SysTick events to the SysTick Reload
|
||||
* Value register. The timer interrupt, or COUNTFLAG bit in the SysTick Control and Status
|
||||
* register, is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks.
|
||||
* If you require a period of 100, write 99 to the SysTick Reload Value register. The SysTick Reload
|
||||
* Value register supports values between 0x1 and 0x00FFFFFF.
|
||||
*
|
||||
* If you want to use SysTick to generate an event at a timed interval, for example 1ms, you can
|
||||
* use the SysTick Calibration Value Register to scale your value for the Reload register. The
|
||||
* SysTick Calibration Value Register is a read-only register that contains the number of pulses for
|
||||
* a period of 10ms, in the TENMS field, bits[23:0].
|
||||
*
|
||||
* This register also has a SKEW bit. Bit[30] == 1 indicates that the calibration for 10ms in the
|
||||
* TENMS section is not exactly 10ms due to clock frequency. Bit[31] == 1 indicates that the
|
||||
* reference clock is not provided.
|
||||
*/
|
||||
/*
|
||||
* SysTick Control and Status Register (CSR).
|
||||
* Purpose Controls the system timer and provides status data.
|
||||
* Usage constraints: There are no usage constraints.
|
||||
* Configurations Always implemented.
|
||||
*/
|
||||
#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10)
|
||||
|
||||
/* SysTick Reload Value Register (CVR).
|
||||
* Purpose Reads or clears the current counter value.
|
||||
* Usage constraints:
|
||||
* - Any write to the register clears the register to zero.
|
||||
* - The counter does not provide read-modify-write protection.
|
||||
* - Unsupported bits are read as zero
|
||||
* Configurations Always implemented.
|
||||
*/
|
||||
#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14)
|
||||
|
||||
/* SysTick Current Value Register (RVR).
|
||||
* Purpose Holds the reload value of the SYST_CVR.
|
||||
* Usage constraints There are no usage constraints.
|
||||
* Configurations Always implemented.
|
||||
*/
|
||||
#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18)
|
||||
|
||||
/*
|
||||
* SysTick Calibration value Register(Read Only) (CALIB)
|
||||
* Purpose Reads the calibration value and parameters for SysTick.
|
||||
* Usage constraints: There are no usage constraints.
|
||||
* Configurations Always implemented.
|
||||
*/
|
||||
#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C)
|
||||
|
||||
/* --- SCS_SYST_CSR values ----------------------------------------------- */
|
||||
/* Counter is operating. */
|
||||
#define SCS_SYST_CSR_ENABLE (BIT0)
|
||||
/* Count to 0 changes the SysTick exception status to pending. */
|
||||
#define SCS_SYST_CSR_TICKINT (BIT1)
|
||||
/* SysTick uses the processor clock. */
|
||||
#define SCS_SYST_CSR_CLKSOURCE (BIT2)
|
||||
/*
|
||||
* Indicates whether the counter has counted to 0 since the last read of this register:
|
||||
* 0 = Timer has not counted to 0
|
||||
* 1 = Timer has counted to 0.
|
||||
*/
|
||||
#define SCS_SYST_CSR_COUNTFLAG (BIT16)
|
||||
|
||||
/* --- CM_SCS_SYST_RVR values ----------------------------------------------- */
|
||||
/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter reaches 0. */
|
||||
/* Bit 24 to 31 are Reserved */
|
||||
|
||||
/* --- CM_SCS_SYST_CVR values ----------------------------------------------- */
|
||||
/* Bit0 to 31 => Reads or clears the current counter value. */
|
||||
|
||||
/* --- CM_SCS_SYST_CALIB values ----------------------------------------------- */
|
||||
/*
|
||||
* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock
|
||||
* skew errors. If this field is zero, the calibration value is not known.
|
||||
*/
|
||||
#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1)
|
||||
|
||||
/*
|
||||
* Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
|
||||
* 0 = 10ms calibration value is exact.
|
||||
* 1 = 10ms calibration value is inexact, because of the clock frequency
|
||||
*/
|
||||
#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30)
|
||||
/*
|
||||
* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented:
|
||||
* 0 = The reference clock is implemented.
|
||||
* 1 = The reference clock is not implemented.
|
||||
* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot
|
||||
* be cleared to 0.
|
||||
*/
|
||||
#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31)
|
||||
|
||||
/*
|
||||
* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
|
||||
* See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html (ARMv7-M Architecture Reference Manual)
|
||||
* The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling
|
||||
* for the processor.
|
||||
*/
|
||||
/*
|
||||
* DWT Control register
|
||||
* Purpose Provides configuration and status information for the DWT block, and used to control features of the block
|
||||
* Usage constraints: There are no usage constraints.
|
||||
* Configurations Always implemented.
|
||||
*/
|
||||
#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00)
|
||||
/*
|
||||
* DWT_CYCCNT register
|
||||
* Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT)
|
||||
* When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero.
|
||||
*
|
||||
* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
|
||||
* Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state.
|
||||
* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL.
|
||||
* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP.
|
||||
*/
|
||||
#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
|
||||
|
||||
/* DWT_CPICNT register
|
||||
* Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls.
|
||||
* Usage constraints: The counter initializes to 0 when software enables its counter overflow event by
|
||||
* setting the DWT_CTRL.CPIEVTENA bit to 1.
|
||||
* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL.
|
||||
* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
|
||||
* include the profiling counters, this register is UNK/SBZP.
|
||||
*/
|
||||
#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08)
|
||||
|
||||
/* DWT_EXCCNT register */
|
||||
#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
|
||||
|
||||
/* DWT_EXCCNT register */
|
||||
#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
|
||||
|
||||
/* DWT_EXCCNT register */
|
||||
#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
|
||||
|
||||
/* DWT_EXCCNT register */
|
||||
#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
|
||||
|
||||
/* DWT_PCSR register */
|
||||
#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18)
|
||||
|
||||
/* --- SCS_DWT_CTRL values ----------------------------------------------- */
|
||||
/*
|
||||
* Enables CYCCNT:
|
||||
* 0 = Disabled, 1 = Enabled
|
||||
* This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
|
||||
*/
|
||||
#define SCS_DWT_CTRL_CYCCNTENA (BIT0)
|
||||
|
||||
/* TODO bit definition values for other DWT_XXX register */
|
||||
|
||||
/* Macro to be called at startup to enable SCS & Cycle Counter */
|
||||
#define SCS_DWT_CYCLE_COUNTER_ENABLED() ( (SCS_DEMCR |= SCS_DEMCR_TRCENA)\
|
||||
(SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA) )
|
||||
|
||||
#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR=0)
|
||||
|
||||
/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not enabled) */
|
||||
#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE))
|
||||
|
||||
/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */
|
||||
#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE | SCS_SYST_CSR_TICKINT))
|
||||
|
||||
#endif
|
||||
|
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_ADC_H
|
||||
#define LPC43XX_ADC_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* ADC port base addresses (for convenience) */
|
||||
#define ADC0 ADC0_BASE
|
||||
#define ADC1 ADC1_BASE
|
||||
|
||||
|
||||
/* --- ADC registers ------------------------------------------------------- */
|
||||
|
||||
/* A/D Control Register */
|
||||
#define ADC_CR(port) MMIO32(port + 0x000)
|
||||
#define ADC0_CR ADC_CR(ADC0)
|
||||
#define ADC1_CR ADC_CR(ADC1)
|
||||
|
||||
/* A/D Global Data Register */
|
||||
#define ADC_GDR(port) MMIO32(port + 0x004)
|
||||
#define ADC0_GDR ADC_GDR(ADC0)
|
||||
#define ADC1_GDR ADC_GDR(ADC1)
|
||||
|
||||
/* A/D Interrupt Enable Register */
|
||||
#define ADC_INTEN(port) MMIO32(port + 0x00C)
|
||||
#define ADC0_INTEN ADC_INTEN(ADC0)
|
||||
#define ADC1_INTEN ADC_INTEN(ADC1)
|
||||
|
||||
/* A/D Channel 0 Data Register */
|
||||
#define ADC_DR0(port) MMIO32(port + 0x010)
|
||||
#define ADC0_DR0 ADC_DR0(ADC0)
|
||||
#define ADC1_DR0 ADC_DR0(ADC1)
|
||||
|
||||
/* A/D Channel 1 Data Register */
|
||||
#define ADC_DR1(port) MMIO32(port + 0x014)
|
||||
#define ADC0_DR1 ADC_DR1(ADC0)
|
||||
#define ADC1_DR1 ADC_DR1(ADC1)
|
||||
|
||||
/* A/D Channel 2 Data Register */
|
||||
#define ADC_DR2(port) MMIO32(port + 0x018)
|
||||
#define ADC0_DR2 ADC_DR2(ADC0)
|
||||
#define ADC1_DR2 ADC_DR2(ADC1)
|
||||
|
||||
/* A/D Channel 3 Data Register */
|
||||
#define ADC_DR3(port) MMIO32(port + 0x01C)
|
||||
#define ADC0_DR3 ADC_DR3(ADC0)
|
||||
#define ADC1_DR3 ADC_DR3(ADC1)
|
||||
|
||||
/* A/D Channel 4 Data Register */
|
||||
#define ADC_DR4(port) MMIO32(port + 0x020)
|
||||
#define ADC0_DR4 ADC_DR4(ADC0)
|
||||
#define ADC1_DR4 ADC_DR4(ADC1)
|
||||
|
||||
/* A/D Channel 5 Data Register */
|
||||
#define ADC_DR5(port) MMIO32(port + 0x024)
|
||||
#define ADC0_DR5 ADC_DR5(ADC0)
|
||||
#define ADC1_DR5 ADC_DR5(ADC1)
|
||||
|
||||
/* A/D Channel 6 Data Register */
|
||||
#define ADC_DR6(port) MMIO32(port + 0x028)
|
||||
#define ADC0_DR6 ADC_DR6(ADC0)
|
||||
#define ADC1_DR6 ADC_DR6(ADC1)
|
||||
|
||||
/* A/D Channel 7 Data Register */
|
||||
#define ADC_DR7(port) MMIO32(port + 0x02C)
|
||||
#define ADC0_DR7 ADC_DR7(ADC0)
|
||||
#define ADC1_DR7 ADC_DR7(ADC1)
|
||||
|
||||
/* A/D Status Register */
|
||||
#define ADC_STAT(port) MMIO32(port + 0x030)
|
||||
#define ADC0_STAT ADC_STAT(ADC0)
|
||||
#define ADC1_STAT ADC_STAT(ADC1)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_ATIMER_H
|
||||
#define LPC43XX_ATIMER_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Alarm Timer registers ----------------------------------------------- */
|
||||
|
||||
/* Downcounter register */
|
||||
#define ATIMER_DOWNCOUNTER MMIO32(ATIMER_BASE + 0x000)
|
||||
|
||||
/* Preset value register */
|
||||
#define ATIMER_PRESET MMIO32(ATIMER_BASE + 0x004)
|
||||
|
||||
/* Interrupt clear enable register */
|
||||
#define ATIMER_CLR_EN MMIO32(ATIMER_BASE + 0xFD8)
|
||||
|
||||
/* Interrupt set enable register */
|
||||
#define ATIMER_SET_EN MMIO32(ATIMER_BASE + 0xFDC)
|
||||
|
||||
/* Status register */
|
||||
#define ATIMER_STATUS MMIO32(ATIMER_BASE + 0xFE0)
|
||||
|
||||
/* Enable register */
|
||||
#define ATIMER_ENABLE MMIO32(ATIMER_BASE + 0xFE4)
|
||||
|
||||
/* Clear register */
|
||||
#define ATIMER_CLR_STAT MMIO32(ATIMER_BASE + 0xFE8)
|
||||
|
||||
/* Set register */
|
||||
#define ATIMER_SET_STAT MMIO32(ATIMER_BASE + 0xFEC)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,384 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_CCU_H
|
||||
#define LPC43XX_CCU_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- CCU1 registers ------------------------------------------------------ */
|
||||
|
||||
/* CCU1 power mode register */
|
||||
#define CCU1_PM MMIO32(CCU1_BASE + 0x000)
|
||||
|
||||
/* CCU1 base clock status register */
|
||||
#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)
|
||||
|
||||
/* CLK_APB3_BUS clock configuration register */
|
||||
#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)
|
||||
|
||||
/* CLK_APB3_BUS clock status register */
|
||||
#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)
|
||||
|
||||
/* CLK_APB3_I2C1 configuration register */
|
||||
#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)
|
||||
|
||||
/* CLK_APB3_I2C1 status register */
|
||||
#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)
|
||||
|
||||
/* CLK_APB3_DAC configuration register */
|
||||
#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)
|
||||
|
||||
/* CLK_APB3_DAC status register */
|
||||
#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)
|
||||
|
||||
/* CLK_APB3_ADC0 configuration register */
|
||||
#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)
|
||||
|
||||
/* CLK_APB3_ADC0 status register */
|
||||
#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)
|
||||
|
||||
/* CLK_APB3_ADC1 configuration register */
|
||||
#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)
|
||||
|
||||
/* CLK_APB3_ADC1 status register */
|
||||
#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)
|
||||
|
||||
/* CLK_APB3_CAN0 configuration register */
|
||||
#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)
|
||||
|
||||
/* CLK_APB3_CAN0 status register */
|
||||
#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)
|
||||
|
||||
/* CLK_APB1_BUS configuration register */
|
||||
#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)
|
||||
|
||||
/* CLK_APB1_BUS status register */
|
||||
#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)
|
||||
|
||||
/* CLK_APB1_MOTOCON configuration register */
|
||||
#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)
|
||||
|
||||
/* CLK_APB1_MOTOCON status register */
|
||||
#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)
|
||||
|
||||
/* CLK_APB1_I2C0 configuration register */
|
||||
#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)
|
||||
|
||||
/* CLK_APB1_I2C0 status register */
|
||||
#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)
|
||||
|
||||
/* CLK_APB1_I2S configuration register */
|
||||
#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)
|
||||
|
||||
/* CLK_APB1_I2S status register */
|
||||
#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)
|
||||
|
||||
/* CLK_APB3_CAN1 configuration register */
|
||||
#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)
|
||||
|
||||
/* CLK_APB3_CAN1 status register */
|
||||
#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)
|
||||
|
||||
/* CLK_SPIFI configuration register */
|
||||
#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)
|
||||
|
||||
/* CLK_SPIFI status register */
|
||||
#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)
|
||||
|
||||
/* CLK_M4_BUS configuration register */
|
||||
#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)
|
||||
|
||||
/* CLK_M4_BUS status register */
|
||||
#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)
|
||||
|
||||
/* CLK_M4_SPIFI configuration register */
|
||||
#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)
|
||||
|
||||
/* CLK_M4_SPIFI status register */
|
||||
#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)
|
||||
|
||||
/* CLK_M4_GPIO configuration register */
|
||||
#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)
|
||||
|
||||
/* CLK_M4_GPIO status register */
|
||||
#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)
|
||||
|
||||
/* CLK_M4_LCD configuration register */
|
||||
#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)
|
||||
|
||||
/* CLK_M4_LCD status register */
|
||||
#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)
|
||||
|
||||
/* CLK_M4_ETHERNET configuration register */
|
||||
#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)
|
||||
|
||||
/* CLK_M4_ETHERNET status register */
|
||||
#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)
|
||||
|
||||
/* CLK_M4_USB0 configuration register */
|
||||
#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)
|
||||
|
||||
/* CLK_M4_USB0 status register */
|
||||
#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)
|
||||
|
||||
/* CLK_M4_EMC configuration register */
|
||||
#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)
|
||||
|
||||
/* CLK_M4_EMC status register */
|
||||
#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)
|
||||
|
||||
/* CLK_M4_SDIO configuration register */
|
||||
#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)
|
||||
|
||||
/* CLK_M4_SDIO status register */
|
||||
#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)
|
||||
|
||||
/* CLK_M4_DMA configuration register */
|
||||
#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)
|
||||
|
||||
/* CLK_M4_DMA status register */
|
||||
#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)
|
||||
|
||||
/* CLK_M4_M4CORE configuration register */
|
||||
#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)
|
||||
|
||||
/* CLK_M4_M4CORE status register */
|
||||
#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)
|
||||
|
||||
/* CLK_M4_SCT configuration register */
|
||||
#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)
|
||||
|
||||
/* CLK_M4_SCT status register */
|
||||
#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)
|
||||
|
||||
/* CLK_M4_USB1 configuration register */
|
||||
#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)
|
||||
|
||||
/* CLK_M4_USB1 status register */
|
||||
#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)
|
||||
|
||||
/* CLK_M4_EMCDIV configuration register */
|
||||
#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)
|
||||
|
||||
/* CLK_M4_EMCDIV status register */
|
||||
#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)
|
||||
|
||||
/* CLK_M4_M0_CFG configuration register */
|
||||
#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)
|
||||
|
||||
/* CLK_M4_M0_STAT status register */
|
||||
#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)
|
||||
|
||||
/* CLK_M4_VADC_CFG configuration register */
|
||||
#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)
|
||||
|
||||
/* CLK_M4_VADC_STAT configuration register */
|
||||
#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)
|
||||
|
||||
/* CLK_M4_WWDT configuration register */
|
||||
#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)
|
||||
|
||||
/* CLK_M4_WWDT status register */
|
||||
#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)
|
||||
|
||||
/* CLK_M4_UART0 configuration register */
|
||||
#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)
|
||||
|
||||
/* CLK_M4_UART0 status register */
|
||||
#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)
|
||||
|
||||
/* CLK_M4_UART1 configuration register */
|
||||
#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)
|
||||
|
||||
/* CLK_M4_UART1 status register */
|
||||
#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)
|
||||
|
||||
/* CLK_M4_SSP0 configuration register */
|
||||
#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)
|
||||
|
||||
/* CLK_M4_SSP0 status register */
|
||||
#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)
|
||||
|
||||
/* CLK_M4_TIMER0 configuration register */
|
||||
#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)
|
||||
|
||||
/* CLK_M4_TIMER0 status register */
|
||||
#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)
|
||||
|
||||
/* CLK_M4_TIMER1 configuration register */
|
||||
#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)
|
||||
|
||||
/* CLK_M4_TIMER1 status register */
|
||||
#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)
|
||||
|
||||
/* CLK_M4_SCU configuration register */
|
||||
#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)
|
||||
|
||||
/* CLK_M4_SCU status register */
|
||||
#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)
|
||||
|
||||
/* CLK_M4_CREG configuration register */
|
||||
#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)
|
||||
|
||||
/* CLK_M4_CREG status register */
|
||||
#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)
|
||||
|
||||
/* CLK_M4_RITIMER configuration register */
|
||||
#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)
|
||||
|
||||
/* CLK_M4_RITIMER status register */
|
||||
#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)
|
||||
|
||||
/* CLK_M4_UART2 configuration register */
|
||||
#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)
|
||||
|
||||
/* CLK_M4_UART2 status register */
|
||||
#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)
|
||||
|
||||
/* CLK_M4_UART3 configuration register */
|
||||
#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)
|
||||
|
||||
/* CLK_M4_UART3 status register */
|
||||
#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)
|
||||
|
||||
/* CLK_M4_TIMER2 configuration register */
|
||||
#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)
|
||||
|
||||
/* CLK_M4_TIMER2 status register */
|
||||
#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)
|
||||
|
||||
/* CLK_M4_TIMER3 configuration register */
|
||||
#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)
|
||||
|
||||
/* CLK_M4_TIMER3 status register */
|
||||
#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)
|
||||
|
||||
/* CLK_M4_SSP1 configuration register */
|
||||
#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)
|
||||
|
||||
/* CLK_M4_SSP1 status register */
|
||||
#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)
|
||||
|
||||
/* CLK_M4_QEI configuration register */
|
||||
#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)
|
||||
|
||||
/* CLK_M4_QEI status register */
|
||||
#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)
|
||||
|
||||
/* CLK_PERIPH_BUS configuration register */
|
||||
#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)
|
||||
|
||||
/* CLK_PERIPH_BUS status register */
|
||||
#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)
|
||||
|
||||
/* CLK_PERIPH_CORE configuration register */
|
||||
#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)
|
||||
|
||||
/* CLK_PERIPH_CORE status register */
|
||||
#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)
|
||||
|
||||
/* CLK_PERIPH_SGPIO configuration register */
|
||||
#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)
|
||||
|
||||
/* CLK_PERIPH_SGPIO status register */
|
||||
#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)
|
||||
|
||||
/* CLK_USB0 configuration register */
|
||||
#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)
|
||||
|
||||
/* CLK_USB0 status register */
|
||||
#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)
|
||||
|
||||
/* CLK_USB1 configuration register */
|
||||
#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)
|
||||
|
||||
/* CLK_USB1 status register */
|
||||
#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)
|
||||
|
||||
/* CLK_SPI configuration register */
|
||||
#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)
|
||||
|
||||
/* CLK_SPI status register */
|
||||
#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)
|
||||
|
||||
/* CLK_VADC configuration register */
|
||||
#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)
|
||||
|
||||
/* CLK_VADC status register */
|
||||
#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)
|
||||
|
||||
/* --- CCU2 registers ------------------------------------------------------ */
|
||||
|
||||
/* CCU2 power mode register */
|
||||
#define CCU2_PM MMIO32(CCU2_BASE + 0x000)
|
||||
|
||||
/* CCU2 base clocks status register */
|
||||
#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)
|
||||
|
||||
/* CLK_APLL configuration register */
|
||||
#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)
|
||||
|
||||
/* CLK_APLL status register */
|
||||
#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)
|
||||
|
||||
/* CLK_APB2_UART3 configuration register */
|
||||
#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)
|
||||
|
||||
/* CLK_APB2_UART3 status register */
|
||||
#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)
|
||||
|
||||
/* CLK_APB2_UART2 configuration register */
|
||||
#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)
|
||||
|
||||
/* CLK_APB2_UART2 status register */
|
||||
#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)
|
||||
|
||||
/* CLK_APB0_UART1 configuration register */
|
||||
#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)
|
||||
|
||||
/* CLK_APB0_UART1 status register */
|
||||
#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)
|
||||
|
||||
/* CLK_APB0_UART0 configuration register */
|
||||
#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)
|
||||
|
||||
/* CLK_APB0_UART0 status register */
|
||||
#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)
|
||||
|
||||
/* CLK_APB2_SSP1 configuration register */
|
||||
#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)
|
||||
|
||||
/* CLK_APB2_SSP1 status register */
|
||||
#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)
|
||||
|
||||
/* CLK_APB0_SSP0 configuration register */
|
||||
#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)
|
||||
|
||||
/* CLK_APB0_SSP0 status register */
|
||||
#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)
|
||||
|
||||
/* CLK_SDIO configuration register (for SD/MMC) */
|
||||
#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)
|
||||
|
||||
/* CLK_SDIO status register (for SD/MMC) */
|
||||
#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_CGU_H
|
||||
#define CGU_LPC43XX_CGU_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- CGU registers ------------------------------------------------------- */
|
||||
|
||||
/* Frequency monitor register */
|
||||
#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)
|
||||
|
||||
/* Crystal oscillator control register */
|
||||
#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)
|
||||
|
||||
/* PLL0USB status register */
|
||||
#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)
|
||||
|
||||
/* PLL0USB control register */
|
||||
#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)
|
||||
|
||||
/* PLL0USB M-divider register */
|
||||
#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)
|
||||
|
||||
/* PLL0USB N/P-divider register */
|
||||
#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
|
||||
|
||||
/* PLL0AUDIO status register */
|
||||
#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
|
||||
|
||||
/* PLL0AUDIO control register */
|
||||
#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
|
||||
|
||||
/* PLL0AUDIO M-divider register */
|
||||
#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
|
||||
|
||||
/* PLL0AUDIO N/P-divider register */
|
||||
#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
|
||||
|
||||
/* PLL0AUDIO fractional divider register */
|
||||
#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
|
||||
|
||||
/* PLL1 status register */
|
||||
#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)
|
||||
|
||||
/* PLL1 control register */
|
||||
#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)
|
||||
|
||||
/* Integer divider A control register */
|
||||
#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
|
||||
|
||||
/* Integer divider B control register */
|
||||
#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
|
||||
|
||||
/* Integer divider C control register */
|
||||
#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
|
||||
|
||||
/* Integer divider D control register */
|
||||
#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
|
||||
|
||||
/* Integer divider E control register */
|
||||
#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
|
||||
|
||||
/* Output stage 0 control register */
|
||||
#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
|
||||
|
||||
/* Output stage 1 control register for base clock */
|
||||
#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
|
||||
|
||||
/* Output stage 2 control register for base clock */
|
||||
#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
|
||||
|
||||
/* Output stage 3 control register for base clock */
|
||||
#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
|
||||
|
||||
/* Output stage 4 control register for base clock */
|
||||
#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
|
||||
|
||||
/* Output stage 5 control register for base clock */
|
||||
#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
|
||||
|
||||
/* Output stage 6 control register for base clock */
|
||||
#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
|
||||
|
||||
/* Output stage 7 control register for base clock */
|
||||
#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
|
||||
|
||||
/* Output stage 8 control register for base clock */
|
||||
#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
|
||||
|
||||
/* Output stage 9 control register for base clock */
|
||||
#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
|
||||
|
||||
/* Output stage 10 control register for base clock */
|
||||
#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
|
||||
|
||||
/* Output stage 11 control register for base clock */
|
||||
#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
|
||||
|
||||
/* Output stage 12 control register for base clock */
|
||||
#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
|
||||
|
||||
/* Output stage 13 control register for base clock */
|
||||
#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
|
||||
|
||||
/* Output stage 14 control register for base clock */
|
||||
#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
|
||||
|
||||
/* Output stage 15 control register for base clock */
|
||||
#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
|
||||
|
||||
/* Output stage 16 control register for base clock */
|
||||
#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
|
||||
|
||||
/* Output stage 17 control register for base clock */
|
||||
#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
|
||||
|
||||
/* Output stage 18 control register for base clock */
|
||||
#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
|
||||
|
||||
/* Output stage 19 control register for base clock */
|
||||
#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
|
||||
|
||||
/* Output stage 20 control register for base clock */
|
||||
#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
|
||||
|
||||
/* Reserved output stage */
|
||||
#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
|
||||
|
||||
/* Output stage 25 control register for base clock */
|
||||
#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
|
||||
|
||||
/* Output stage 26 control CLK register for base clock */
|
||||
#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
|
||||
|
||||
/* Output stage 27 control CLK register for base clock */
|
||||
#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
|
||||
|
||||
/* --- CGU_XTAL_OSC_CTRL values -------------------------------------------- */
|
||||
|
||||
#define CGU_XTAL_OSC_CTRL_ENABLE (1 << 0) /* enable or power down xtal osc */
|
||||
#define CGU_XTAL_OSC_CTRL_BYPASS (1 << 1) /* external clock input (not xtal) */
|
||||
#define CGU_XTAL_OSC_CTRL_HF (1 << 2) /* high frequency mode (>15 MHz) */
|
||||
|
||||
/* --- CGU_PLL1_STAT values ------------------------------------------------ */
|
||||
|
||||
#define CGU_PLL1_STAT_LOCK (1 << 0)
|
||||
|
||||
/* --- CGU_PLL1_CTRL values ------------------------------------------------ */
|
||||
|
||||
#define CGU_PLL1_CTRL_PD (1 << 0) /* power down */
|
||||
#define CGU_PLL1_CTRL_BYPASS (1 << 1) /* PLL input to post-dividers */
|
||||
#define CGU_PLL1_CTRL_FBSEL (1 << 6) /* use clkout as feedback input */
|
||||
#define CGU_PLL1_CTRL_DIRECT (1 << 7) /* enable direct CCO output */
|
||||
#define CGU_PLL1_CTRL_PSEL_SHIFT 8 /* division ratio P (2 bits) */
|
||||
#define CGU_PLL1_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */
|
||||
#define CGU_PLL1_CTRL_NSEL_SHIFT 12 /* division ratio N (2 bits) */
|
||||
#define CGU_PLL1_CTRL_MSEL_SHIFT 16 /* division ratio M (8 bits) */
|
||||
#define CGU_PLL1_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */
|
||||
|
||||
/* --- CGU_PLL0USB_STAT values --------------------------------------------- */
|
||||
|
||||
#define CGU_PLL0USB_STAT_LOCK (1 << 0) /* PLL0 lock indicator */
|
||||
#define CGU_PLL0USB_STAT_FR (1 << 1) /* PLL0 free running indicator */
|
||||
|
||||
/* --- CGU_PLL0USB_CTRL values --------------------------------------------- */
|
||||
|
||||
#define CGU_PLL0USB_CTRL_PD (1 << 0) /* power down */
|
||||
#define CGU_PLL0USB_CTRL_BYPASS (1 << 1) /* input to post-dividers */
|
||||
#define CGU_PLL0USB_CTRL_DIRECTI (1 << 2) /* direct input */
|
||||
#define CGU_PLL0USB_CTRL_DIRECTO (1 << 3) /* direct output */
|
||||
#define CGU_PLL0USB_CTRL_CLKEN (1 << 4) /* clock enable */
|
||||
#define CGU_PLL0USB_CTRL_FRM (1 << 6) /* free running mode */
|
||||
#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */
|
||||
#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */
|
||||
|
||||
/* --- CGU_PLL0USB_MDIV values --------------------------------------------- */
|
||||
|
||||
#define CGU_PLL0USB_MDIV_MDEC_SHIFT 0 /* Decoded M-divider value (17 bits) */
|
||||
#define CGU_PLL0USB_SELP_MDEC_SHIFT 17 /* Bandwidth select P value (5 bits) */
|
||||
#define CGU_PLL0USB_SELI_MDEC_SHIFT 22 /* Bandwidth select I value (6 bits) */
|
||||
#define CGU_PLL0USB_SELR_MDEC_SHIFT 28 /* Bandwidth select R value (4 bits) */
|
||||
|
||||
/* --- CGU_PLL0USB_NP_DIV values ------------------------------------------- */
|
||||
|
||||
#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT 0 /* Decoded P-divider value (7 bits) */
|
||||
#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT 12 /* Decoded N-divider value (8 bits) */
|
||||
|
||||
/* --- CGU_BASE_x_CLK values ----------------------------------------------- */
|
||||
|
||||
#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */
|
||||
#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */
|
||||
#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
|
||||
|
||||
/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */
|
||||
|
||||
#define CGU_SRC_32K 0x00
|
||||
#define CGU_SRC_IRC 0x01
|
||||
#define CGU_SRC_ENET_RX 0x02
|
||||
#define CGU_SRC_ENET_TX 0x03
|
||||
#define CGU_SRC_GP_CLKIN 0x04
|
||||
#define CGU_SRC_XTAL 0x06
|
||||
#define CGU_SRC_PLL0USB 0x07
|
||||
#define CGU_SRC_PLL0AUDIO 0x08
|
||||
#define CGU_SRC_PLL1 0x09
|
||||
#define CGU_SRC_IDIVA 0x0C
|
||||
#define CGU_SRC_IDIVB 0x0D
|
||||
#define CGU_SRC_IDIVC 0x0E
|
||||
#define CGU_SRC_IDIVD 0x0F
|
||||
#define CGU_SRC_IDIVE 0x10
|
||||
|
||||
#endif
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_CREG_H
|
||||
#define LPC43XX_CREG_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- CREG registers ----------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Chip configuration register 32 kHz oscillator output and BOD control
|
||||
* register
|
||||
*/
|
||||
#define CREG_CREG0 MMIO32(CREG_BASE + 0x004)
|
||||
|
||||
/* ARM Cortex-M4 memory mapping */
|
||||
#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)
|
||||
|
||||
/* Chip configuration register 1 */
|
||||
#define CREG_CREG1 MMIO32(CREG_BASE + 0x108)
|
||||
|
||||
/* Chip configuration register 2 */
|
||||
#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C)
|
||||
|
||||
/* Chip configuration register 3 */
|
||||
#define CREG_CREG3 MMIO32(CREG_BASE + 0x110)
|
||||
|
||||
/* Chip configuration register 4 */
|
||||
#define CREG_CREG4 MMIO32(CREG_BASE + 0x114)
|
||||
|
||||
/* Chip configuration register 5 */
|
||||
#define CREG_CREG5 MMIO32(CREG_BASE + 0x118)
|
||||
|
||||
/* DMA muxing control */
|
||||
#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C)
|
||||
|
||||
/* ETB RAM configuration */
|
||||
#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128)
|
||||
|
||||
/*
|
||||
* Chip configuration register 6. Controls multiple functions: Ethernet
|
||||
* interface, SCT output, I2S0/1 inputs, EMC clock.
|
||||
*/
|
||||
#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C)
|
||||
|
||||
/* Cortex-M4 TXEV event clear */
|
||||
#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130)
|
||||
|
||||
/* Part ID */
|
||||
#define CREG_CHIPID MMIO32(CREG_BASE + 0x200)
|
||||
|
||||
/* Cortex-M0 TXEV event clear */
|
||||
#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400)
|
||||
|
||||
/* ARM Cortex-M0 memory mapping */
|
||||
#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_EVENTROUTER_H
|
||||
#define LPC43XX_EVENTROUTER_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Event Router registers ---------------------------------------------- */
|
||||
|
||||
/* Level configuration register */
|
||||
#define EVENTROUTER_HILO MMIO32(EVENTROUTER_BASE + 0x000)
|
||||
|
||||
/* Edge configuration */
|
||||
#define EVENTROUTER_EDGE MMIO32(EVENTROUTER_BASE + 0x004)
|
||||
|
||||
/* Clear event enable register */
|
||||
#define EVENTROUTER_CLR_EN MMIO32(EVENTROUTER_BASE + 0xFD8)
|
||||
|
||||
/* Set event enable register */
|
||||
#define EVENTROUTER_ET_EN MMIO32(EVENTROUTER_BASE + 0xFDC)
|
||||
|
||||
/* Event Status register */
|
||||
#define EVENTROUTER_STATUS MMIO32(EVENTROUTER_BASE + 0xFE0)
|
||||
|
||||
/* Event Enable register */
|
||||
#define EVENTROUTER_ENABLE MMIO32(EVENTROUTER_BASE + 0xFE4)
|
||||
|
||||
/* Clear event status register */
|
||||
#define EVENTROUTER_CLR_STAT MMIO32(EVENTROUTER_BASE + 0xFE8)
|
||||
|
||||
/* Set event status register */
|
||||
#define EVENTROUTER_SET_STAT MMIO32(EVENTROUTER_BASE + 0xFEC)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_GIMA_H
|
||||
#define LPC43XX_GIMA_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- GIMA registers ----------------------------------------------------- */
|
||||
|
||||
/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
|
||||
#define GIMA_CAP0_0_IN MMIO32(GIMA_BASE + 0x000)
|
||||
|
||||
/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
|
||||
#define GIMA_CAP0_1_IN MMIO32(GIMA_BASE + 0x004)
|
||||
|
||||
/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
|
||||
#define GIMA_CAP0_2_IN MMIO32(GIMA_BASE + 0x008)
|
||||
|
||||
/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
|
||||
#define GIMA_CAP0_3_IN MMIO32(GIMA_BASE + 0x00C)
|
||||
|
||||
/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
|
||||
#define GIMA_CAP1_0_IN MMIO32(GIMA_BASE + 0x010)
|
||||
|
||||
/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
|
||||
#define GIMA_CAP1_1_IN MMIO32(GIMA_BASE + 0x014)
|
||||
|
||||
/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
|
||||
#define GIMA_CAP1_2_IN MMIO32(GIMA_BASE + 0x018)
|
||||
|
||||
/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
|
||||
#define GIMA_CAP1_3_IN MMIO32(GIMA_BASE + 0x01C)
|
||||
|
||||
/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
|
||||
#define GIMA_CAP2_0_IN MMIO32(GIMA_BASE + 0x020)
|
||||
|
||||
/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
|
||||
#define GIMA_CAP2_1_IN MMIO32(GIMA_BASE + 0x024)
|
||||
|
||||
/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
|
||||
#define GIMA_CAP2_2_IN MMIO32(GIMA_BASE + 0x028)
|
||||
|
||||
/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
|
||||
#define GIMA_CAP2_3_IN MMIO32(GIMA_BASE + 0x02C)
|
||||
|
||||
/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
|
||||
#define GIMA_CAP3_0_IN MMIO32(GIMA_BASE + 0x030)
|
||||
|
||||
/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
|
||||
#define GIMA_CAP3_1_IN MMIO32(GIMA_BASE + 0x034)
|
||||
|
||||
/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
|
||||
#define GIMA_CAP3_2_IN MMIO32(GIMA_BASE + 0x038)
|
||||
|
||||
/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
|
||||
#define GIMA_CAP3_3_IN MMIO32(GIMA_BASE + 0x03C)
|
||||
|
||||
/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
|
||||
#define GIMA_CTIN_0_IN MMIO32(GIMA_BASE + 0x040)
|
||||
|
||||
/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
|
||||
#define GIMA_CTIN_1_IN MMIO32(GIMA_BASE + 0x044)
|
||||
|
||||
/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
|
||||
#define GIMA_CTIN_2_IN MMIO32(GIMA_BASE + 0x048)
|
||||
|
||||
/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */
|
||||
#define GIMA_CTIN_3_IN MMIO32(GIMA_BASE + 0x04C)
|
||||
|
||||
/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */
|
||||
#define GIMA_CTIN_4_IN MMIO32(GIMA_BASE + 0x050)
|
||||
|
||||
/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */
|
||||
#define GIMA_CTIN_5_IN MMIO32(GIMA_BASE + 0x054)
|
||||
|
||||
/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */
|
||||
#define GIMA_CTIN_6_IN MMIO32(GIMA_BASE + 0x058)
|
||||
|
||||
/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */
|
||||
#define GIMA_CTIN_7_IN MMIO32(GIMA_BASE + 0x05C)
|
||||
|
||||
/* VADC trigger input multiplexer (GIMA output 24) */
|
||||
#define GIMA_VADC_TRIGGER_IN MMIO32(GIMA_BASE + 0x060)
|
||||
|
||||
/* Event router input 13 multiplexer (GIMA output 25) */
|
||||
#define GIMA_EVENTROUTER_13_IN MMIO32(GIMA_BASE + 0x064)
|
||||
|
||||
/* Event router input 14 multiplexer (GIMA output 26) */
|
||||
#define GIMA_EVENTROUTER_14_IN MMIO32(GIMA_BASE + 0x068)
|
||||
|
||||
/* Event router input 16 multiplexer (GIMA output 27) */
|
||||
#define GIMA_EVENTROUTER_16_IN MMIO32(GIMA_BASE + 0x06C)
|
||||
|
||||
/* ADC start0 input multiplexer (GIMA output 28) */
|
||||
#define GIMA_ADCSTART0_IN MMIO32(GIMA_BASE + 0x070)
|
||||
|
||||
/* ADC start1 input multiplexer (GIMA output 29) */
|
||||
#define GIMA_ADCSTART1_IN MMIO32(GIMA_BASE + 0x074)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,143 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_GPDMA_H
|
||||
#define LPC43XX_GPDMA_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* GPDMA channel base addresses */
|
||||
#define GPDMA_CHANNEL0 (GPDMA_PORT_BASE + 0x100)
|
||||
#define GPDMA_CHANNEL1 (GPDMA_PORT_BASE + 0x120)
|
||||
#define GPDMA_CHANNEL2 (GPDMA_PORT_BASE + 0x140)
|
||||
#define GPDMA_CHANNEL3 (GPDMA_PORT_BASE + 0x160)
|
||||
#define GPDMA_CHANNEL4 (GPDMA_PORT_BASE + 0x180)
|
||||
#define GPDMA_CHANNEL5 (GPDMA_PORT_BASE + 0x1A0)
|
||||
#define GPDMA_CHANNEL6 (GPDMA_PORT_BASE + 0x1C0)
|
||||
#define GPDMA_CHANNEL7 (GPDMA_PORT_BASE + 0x1E0)
|
||||
|
||||
|
||||
/* --- GPDMA registers ----------------------------------------------------- */
|
||||
|
||||
/* General registers */
|
||||
|
||||
/* DMA Interrupt Status Register */
|
||||
#define GPDMA_NTSTAT MMIO32(GPDMA_BASE + 0x000)
|
||||
|
||||
/* DMA Interrupt Terminal Count Request Status Register */
|
||||
#define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004)
|
||||
|
||||
/* DMA Interrupt Terminal Count Request Clear Register */
|
||||
#define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008)
|
||||
|
||||
/* DMA Interrupt Error Status Register */
|
||||
#define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C)
|
||||
|
||||
/* DMA Interrupt Error Clear Register */
|
||||
#define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010)
|
||||
|
||||
/* DMA Raw Interrupt Terminal Count Status Register */
|
||||
#define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014)
|
||||
|
||||
/* DMA Raw Error Interrupt Status Register */
|
||||
#define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018)
|
||||
|
||||
/* DMA Enabled Channel Register */
|
||||
#define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C)
|
||||
|
||||
/* DMA Software Burst Request Register */
|
||||
#define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020)
|
||||
|
||||
/* DMA Software Single Request Register */
|
||||
#define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024)
|
||||
|
||||
/* DMA Software Last Burst Request Register */
|
||||
#define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028)
|
||||
|
||||
/* DMA Software Last Single Request Register */
|
||||
#define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C)
|
||||
|
||||
/* DMA Configuration Register */
|
||||
#define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030)
|
||||
|
||||
/* DMA Synchronization Register */
|
||||
#define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034)
|
||||
|
||||
|
||||
/* Channel registers */
|
||||
|
||||
/* Source Address Register */
|
||||
#define GPDMA_SRCADDR(channel) MMIO32(channel + 0x000)
|
||||
#define GPDMA_C0SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL0)
|
||||
#define GPDMA_C1SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL1)
|
||||
#define GPDMA_C2SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL2)
|
||||
#define GPDMA_C3SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL3)
|
||||
#define GPDMA_C4SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL4)
|
||||
#define GPDMA_C5SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL5)
|
||||
#define GPDMA_C6SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL6)
|
||||
#define GPDMA_C7SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL7)
|
||||
|
||||
/* Destination Address Register */
|
||||
#define GPDMA_DESTADDR(channel) MMIO32(channel + 0x004)
|
||||
#define GPDMA_C0DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL0)
|
||||
#define GPDMA_C1DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL1)
|
||||
#define GPDMA_C2DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL2)
|
||||
#define GPDMA_C3DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL3)
|
||||
#define GPDMA_C4DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL4)
|
||||
#define GPDMA_C5DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL5)
|
||||
#define GPDMA_C6DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL6)
|
||||
#define GPDMA_C7DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL7)
|
||||
|
||||
/* Linked List Item Register */
|
||||
#define GPDMA_LLI(channel) MMIO32(channel + 0x008)
|
||||
#define GPDMA_C0LLI GPDMA_LLI(GPDMA_CHANNEL0)
|
||||
#define GPDMA_C1LLI GPDMA_LLI(GPDMA_CHANNEL1)
|
||||
#define GPDMA_C2LLI GPDMA_LLI(GPDMA_CHANNEL2)
|
||||
#define GPDMA_C3LLI GPDMA_LLI(GPDMA_CHANNEL3)
|
||||
#define GPDMA_C4LLI GPDMA_LLI(GPDMA_CHANNEL4)
|
||||
#define GPDMA_C5LLI GPDMA_LLI(GPDMA_CHANNEL5)
|
||||
#define GPDMA_C6LLI GPDMA_LLI(GPDMA_CHANNEL6)
|
||||
#define GPDMA_C7LLI GPDMA_LLI(GPDMA_CHANNEL7)
|
||||
|
||||
/* Control Register */
|
||||
#define GPDMA_CONTROL(channel) MMIO32(channel + 0x00C)
|
||||
#define GPDMA_C0CONTROL GPDMA_CONTROL(GPDMA_CHANNEL0)
|
||||
#define GPDMA_C1CONTROL GPDMA_CONTROL(GPDMA_CHANNEL1)
|
||||
#define GPDMA_C2CONTROL GPDMA_CONTROL(GPDMA_CHANNEL2)
|
||||
#define GPDMA_C3CONTROL GPDMA_CONTROL(GPDMA_CHANNEL3)
|
||||
#define GPDMA_C4CONTROL GPDMA_CONTROL(GPDMA_CHANNEL4)
|
||||
#define GPDMA_C5CONTROL GPDMA_CONTROL(GPDMA_CHANNEL5)
|
||||
#define GPDMA_C6CONTROL GPDMA_CONTROL(GPDMA_CHANNEL6)
|
||||
#define GPDMA_C7CONTROL GPDMA_CONTROL(GPDMA_CHANNEL7)
|
||||
|
||||
/* Configuration Register */
|
||||
#define GPDMA_CONFIG(channel) MMIO32(channel + 0x010)
|
||||
#define GPDMA_C0CONFIG GPDMA_CONFIG(GPDMA_CHANNEL0)
|
||||
#define GPDMA_C1CONFIG GPDMA_CONFIG(GPDMA_CHANNEL1)
|
||||
#define GPDMA_C2CONFIG GPDMA_CONFIG(GPDMA_CHANNEL2)
|
||||
#define GPDMA_C3CONFIG GPDMA_CONFIG(GPDMA_CHANNEL3)
|
||||
#define GPDMA_C4CONFIG GPDMA_CONFIG(GPDMA_CHANNEL4)
|
||||
#define GPDMA_C5CONFIG GPDMA_CONFIG(GPDMA_CHANNEL5)
|
||||
#define GPDMA_C6CONFIG GPDMA_CONFIG(GPDMA_CHANNEL6)
|
||||
#define GPDMA_C7CONFIG GPDMA_CONFIG(GPDMA_CHANNEL7)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_GPIO_H
|
||||
#define LPC43XX_GPIO_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* GPIO port base addresses (for convenience) */
|
||||
#define GPIO0 (GPIO_PORT_BASE + 0x2000)
|
||||
#define GPIO1 (GPIO_PORT_BASE + 0x2004)
|
||||
#define GPIO2 (GPIO_PORT_BASE + 0x2008)
|
||||
#define GPIO3 (GPIO_PORT_BASE + 0x200C)
|
||||
#define GPIO4 (GPIO_PORT_BASE + 0x2010)
|
||||
#define GPIO5 (GPIO_PORT_BASE + 0x2014)
|
||||
#define GPIO6 (GPIO_PORT_BASE + 0x2018)
|
||||
#define GPIO7 (GPIO_PORT_BASE + 0x201C)
|
||||
|
||||
/* GPIO number definitions (for convenience) */
|
||||
#define GPIOPIN0 (1 << 0)
|
||||
#define GPIOPIN1 (1 << 1)
|
||||
#define GPIOPIN2 (1 << 2)
|
||||
#define GPIOPIN3 (1 << 3)
|
||||
#define GPIOPIN4 (1 << 4)
|
||||
#define GPIOPIN5 (1 << 5)
|
||||
#define GPIOPIN6 (1 << 6)
|
||||
#define GPIOPIN7 (1 << 7)
|
||||
#define GPIOPIN8 (1 << 8)
|
||||
#define GPIOPIN9 (1 << 9)
|
||||
#define GPIOPIN10 (1 << 10)
|
||||
#define GPIOPIN11 (1 << 11)
|
||||
#define GPIOPIN12 (1 << 12)
|
||||
#define GPIOPIN13 (1 << 13)
|
||||
#define GPIOPIN14 (1 << 14)
|
||||
#define GPIOPIN15 (1 << 15)
|
||||
#define GPIOPIN16 (1 << 16)
|
||||
#define GPIOPIN17 (1 << 17)
|
||||
#define GPIOPIN18 (1 << 18)
|
||||
#define GPIOPIN19 (1 << 19)
|
||||
#define GPIOPIN20 (1 << 20)
|
||||
#define GPIOPIN21 (1 << 21)
|
||||
#define GPIOPIN22 (1 << 22)
|
||||
#define GPIOPIN23 (1 << 23)
|
||||
#define GPIOPIN24 (1 << 24)
|
||||
#define GPIOPIN25 (1 << 25)
|
||||
#define GPIOPIN26 (1 << 26)
|
||||
#define GPIOPIN27 (1 << 27)
|
||||
#define GPIOPIN28 (1 << 28)
|
||||
#define GPIOPIN29 (1 << 29)
|
||||
#define GPIOPIN30 (1 << 30)
|
||||
#define GPIOPIN31 (1 << 31)
|
||||
|
||||
/* --- GPIO registers ------------------------------------------------------ */
|
||||
|
||||
//TODO byte/word access registers
|
||||
|
||||
/* GPIO data direction register (GPIOn_DIR) */
|
||||
#define GPIO_DIR(port) MMIO32(port + 0x00)
|
||||
#define GPIO0_DIR GPIO_DIR(GPIO0)
|
||||
#define GPIO1_DIR GPIO_DIR(GPIO1)
|
||||
#define GPIO2_DIR GPIO_DIR(GPIO2)
|
||||
#define GPIO3_DIR GPIO_DIR(GPIO3)
|
||||
#define GPIO4_DIR GPIO_DIR(GPIO4)
|
||||
#define GPIO5_DIR GPIO_DIR(GPIO5)
|
||||
#define GPIO6_DIR GPIO_DIR(GPIO6)
|
||||
#define GPIO7_DIR GPIO_DIR(GPIO7)
|
||||
|
||||
/* GPIO fast mask register (GPIOn_MASK) */
|
||||
#define GPIO_MASK(port) MMIO32(port + 0x80)
|
||||
#define GPIO0_MASK GPIO_MASK(GPIO0)
|
||||
#define GPIO1_MASK GPIO_MASK(GPIO1)
|
||||
#define GPIO2_MASK GPIO_MASK(GPIO2)
|
||||
#define GPIO3_MASK GPIO_MASK(GPIO3)
|
||||
#define GPIO4_MASK GPIO_MASK(GPIO4)
|
||||
#define GPIO5_MASK GPIO_MASK(GPIO5)
|
||||
#define GPIO6_MASK GPIO_MASK(GPIO6)
|
||||
#define GPIO7_MASK GPIO_MASK(GPIO7)
|
||||
|
||||
/* GPIO port pin value register (GPIOn_PIN) */
|
||||
#define GPIO_PIN(port) MMIO32(port + 0x100)
|
||||
#define GPIO0_PIN GPIO_PIN(GPIO0)
|
||||
#define GPIO1_PIN GPIO_PIN(GPIO1)
|
||||
#define GPIO2_PIN GPIO_PIN(GPIO2)
|
||||
#define GPIO3_PIN GPIO_PIN(GPIO3)
|
||||
#define GPIO4_PIN GPIO_PIN(GPIO4)
|
||||
#define GPIO5_PIN GPIO_PIN(GPIO5)
|
||||
#define GPIO6_PIN GPIO_PIN(GPIO6)
|
||||
#define GPIO7_PIN GPIO_PIN(GPIO7)
|
||||
|
||||
/* GPIO port masked pin value register (GPIOn_MPIN) */
|
||||
#define GPIO_MPIN(port) MMIO32(port + 0x180)
|
||||
#define GPIO0_MPIN GPIO_MPIN(GPIO0)
|
||||
#define GPIO1_MPIN GPIO_MPIN(GPIO1)
|
||||
#define GPIO2_MPIN GPIO_MPIN(GPIO2)
|
||||
#define GPIO3_MPIN GPIO_MPIN(GPIO3)
|
||||
#define GPIO4_MPIN GPIO_MPIN(GPIO4)
|
||||
#define GPIO5_MPIN GPIO_MPIN(GPIO5)
|
||||
#define GPIO6_MPIN GPIO_MPIN(GPIO6)
|
||||
#define GPIO7_MPIN GPIO_MPIN(GPIO7)
|
||||
|
||||
/* GPIO port output set register (GPIOn_SET) */
|
||||
#define GPIO_SET(port) MMIO32(port + 0x200)
|
||||
#define GPIO0_SET GPIO_SET(GPIO0)
|
||||
#define GPIO1_SET GPIO_SET(GPIO1)
|
||||
#define GPIO2_SET GPIO_SET(GPIO2)
|
||||
#define GPIO3_SET GPIO_SET(GPIO3)
|
||||
#define GPIO4_SET GPIO_SET(GPIO4)
|
||||
#define GPIO5_SET GPIO_SET(GPIO5)
|
||||
#define GPIO6_SET GPIO_SET(GPIO6)
|
||||
#define GPIO7_SET GPIO_SET(GPIO7)
|
||||
|
||||
/* GPIO port output clear register (GPIOn_CLR) */
|
||||
#define GPIO_CLR(port) MMIO32(port + 0x280)
|
||||
#define GPIO0_CLR GPIO_CLR(GPIO0)
|
||||
#define GPIO1_CLR GPIO_CLR(GPIO1)
|
||||
#define GPIO2_CLR GPIO_CLR(GPIO2)
|
||||
#define GPIO3_CLR GPIO_CLR(GPIO3)
|
||||
#define GPIO4_CLR GPIO_CLR(GPIO4)
|
||||
#define GPIO5_CLR GPIO_CLR(GPIO5)
|
||||
#define GPIO6_CLR GPIO_CLR(GPIO6)
|
||||
#define GPIO7_CLR GPIO_CLR(GPIO7)
|
||||
|
||||
/* GPIO port toggle register (GPIOn_NOT) */
|
||||
#define GPIO_NOT(port) MMIO32(port + 0x300)
|
||||
#define GPIO0_NOT GPIO_NOT(GPIO0)
|
||||
#define GPIO1_NOT GPIO_NOT(GPIO1)
|
||||
#define GPIO2_NOT GPIO_NOT(GPIO2)
|
||||
#define GPIO3_NOT GPIO_NOT(GPIO3)
|
||||
#define GPIO4_NOT GPIO_NOT(GPIO4)
|
||||
#define GPIO5_NOT GPIO_NOT(GPIO5)
|
||||
#define GPIO6_NOT GPIO_NOT(GPIO6)
|
||||
#define GPIO7_NOT GPIO_NOT(GPIO7)
|
||||
|
||||
//TODO interrupts
|
||||
|
||||
void gpio_set(u32 gpioport, u32 gpios);
|
||||
void gpio_clear(u32 gpioport, u32 gpios);
|
||||
void gpio_toggle(u32 gpioport, u32 gpios);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_I2C_H
|
||||
#define LPC43XX_I2C_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* I2C port base addresses (for convenience) */
|
||||
#define I2C0 I2C0_BASE
|
||||
#define I2C1 I2C1_BASE
|
||||
|
||||
/* --- I2C registers ------------------------------------------------------- */
|
||||
|
||||
/* I2C Control Set Register */
|
||||
#define I2C_CONSET(port) MMIO32(port + 0x000)
|
||||
#define I2C0_CONSET I2C_CONSET(I2C0)
|
||||
#define I2C1_CONSET I2C_CONSET(I2C1)
|
||||
|
||||
/* I2C Status Register */
|
||||
#define I2C_STAT(port) MMIO32(port + 0x004)
|
||||
#define I2C0_STAT I2C_STAT(I2C0)
|
||||
#define I2C1_STAT I2C_STAT(I2C1)
|
||||
|
||||
/* I2C Data Register */
|
||||
#define I2C_DAT(port) MMIO32(port + 0x008)
|
||||
#define I2C0_DAT I2C_DAT(I2C0)
|
||||
#define I2C1_DAT I2C_DAT(I2C1)
|
||||
|
||||
/* I2C Slave Address Register 0 */
|
||||
#define I2C_ADR0(port) MMIO32(port + 0x00C)
|
||||
#define I2C0_ADR0 I2C_ADR0(I2C0)
|
||||
#define I2C1_ADR0 I2C_ADR0(I2C1)
|
||||
|
||||
/* SCH Duty Cycle Register High Half Word */
|
||||
#define I2C_SCLH(port) MMIO32(port + 0x010)
|
||||
#define I2C0_SCLH I2C_SCLH(I2C0)
|
||||
#define I2C1_SCLH I2C_SCLH(I2C1)
|
||||
|
||||
/* SCL Duty Cycle Register Low Half Word */
|
||||
#define I2C_SCLL(port) MMIO32(port + 0x014)
|
||||
#define I2C0_SCLL I2C_SCLL(I2C0)
|
||||
#define I2C1_SCLL I2C_SCLL(I2C1)
|
||||
|
||||
/* I2C Control Clear Register */
|
||||
#define I2C_CONCLR(port) MMIO32(port + 0x018)
|
||||
#define I2C0_CONCLR I2C_CONCLR(I2C0)
|
||||
#define I2C1_CONCLR I2C_CONCLR(I2C1)
|
||||
|
||||
/* Monitor mode control register */
|
||||
#define I2C_MMCTRL(port) MMIO32(port + 0x01C)
|
||||
#define I2C0_MMCTRL I2C_MMCTRL(I2C0)
|
||||
#define I2C1_MMCTRL I2C_MMCTRL(I2C1)
|
||||
|
||||
/* I2C Slave Address Register 1 */
|
||||
#define I2C_ADR1(port) MMIO32(port + 0x020)
|
||||
#define I2C0_ADR1 I2C_ADR1(I2C0)
|
||||
#define I2C1_ADR1 I2C_ADR1(I2C1)
|
||||
|
||||
/* I2C Slave Address Register 2 */
|
||||
#define I2C_ADR2(port) MMIO32(port + 0x024)
|
||||
#define I2C0_ADR2 I2C_ADR2(I2C0)
|
||||
#define I2C1_ADR2 I2C_ADR2(I2C1)
|
||||
|
||||
/* I2C Slave Address Register 3 */
|
||||
#define I2C_ADR3(port) MMIO32(port + 0x028)
|
||||
#define I2C0_ADR3 I2C_ADR3(I2C0)
|
||||
#define I2C1_ADR3 I2C_ADR3(I2C1)
|
||||
|
||||
/* Data buffer register */
|
||||
#define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C)
|
||||
#define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0)
|
||||
#define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1)
|
||||
|
||||
/* I2C Slave address mask register 0 */
|
||||
#define I2C_MASK0(port) MMIO32(port + 0x030)
|
||||
#define I2C0_MASK0 I2C_MASK0(I2C0)
|
||||
#define I2C1_MASK0 I2C_MASK0(I2C1)
|
||||
|
||||
/* I2C Slave address mask register 1 */
|
||||
#define I2C_MASK1(port) MMIO32(port + 0x034)
|
||||
#define I2C0_MASK1 I2C_MASK1(I2C0)
|
||||
#define I2C1_MASK1 I2C_MASK1(I2C1)
|
||||
|
||||
/* I2C Slave address mask register 2 */
|
||||
#define I2C_MASK2(port) MMIO32(port + 0x038)
|
||||
#define I2C0_MASK2 I2C_MASK2(I2C0)
|
||||
#define I2C1_MASK2 I2C_MASK2(I2C1)
|
||||
|
||||
/* I2C Slave address mask register 3 */
|
||||
#define I2C_MASK3(port) MMIO32(port + 0x03C)
|
||||
#define I2C0_MASK3 I2C_MASK3(I2C0)
|
||||
#define I2C1_MASK3 I2C_MASK3(I2C1)
|
||||
|
||||
/* --- I2Cx_CONCLR values -------------------------------------------------- */
|
||||
|
||||
#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */
|
||||
#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */
|
||||
#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */
|
||||
#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */
|
||||
|
||||
/* --- I2Cx_CONSET values -------------------------------------------------- */
|
||||
|
||||
#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */
|
||||
#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */
|
||||
#define I2C_CONSET_STO (1 << 4) /* STOP flag */
|
||||
#define I2C_CONSET_STA (1 << 5) /* START flag */
|
||||
#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */
|
||||
|
||||
/* --- I2C const definitions ----------------------------------------------- */
|
||||
|
||||
#define I2C_WRITE 0
|
||||
#define I2C_READ 1
|
||||
|
||||
/* --- I2C funtion prototypes----------------------------------------------- */
|
||||
|
||||
void i2c0_init(void);
|
||||
void i2c0_tx_start(void);
|
||||
void i2c0_tx_byte(u8 byte);
|
||||
u8 i2c0_rx_byte(void);
|
||||
void i2c0_stop(void);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_I2S_H
|
||||
#define LPC43XX_I2S_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* I2S port base addresses (for convenience) */
|
||||
#define I2S0 I2S0_BASE
|
||||
#define I2S1 I2S1_BASE
|
||||
|
||||
|
||||
/* --- I2S registers ------------------------------------------------------- */
|
||||
|
||||
/* I2S Digital Audio Output Register */
|
||||
#define I2S_DAO(port) MMIO32(port + 0x000)
|
||||
#define I2S0_DAO I2S_DAO(I2S0)
|
||||
#define I2S1_DAO I2S_DAO(I2S1)
|
||||
|
||||
/* I2S Digital Audio Input Register */
|
||||
#define I2S_DAI(port) MMIO32(port + 0x004)
|
||||
#define I2S0_DAI I2S_DAI(I2S0)
|
||||
#define I2S1_DAI I2S_DAI(I2S1)
|
||||
|
||||
/* I2S Transmit FIFO */
|
||||
#define I2S_TXFIFO(port) MMIO32(port + 0x008)
|
||||
#define I2S0_TXFIFO I2S_TXFIFO(I2S0)
|
||||
#define I2S1_TXFIFO I2S_TXFIFO(I2S1)
|
||||
|
||||
/* I2S Receive FIFO */
|
||||
#define I2S_RXFIFO(port) MMIO32(port + 0x00C)
|
||||
#define I2S0_RXFIFO I2S_RXFIFO(I2S0)
|
||||
#define I2S1_RXFIFO I2S_RXFIFO(I2S1)
|
||||
|
||||
/* I2S Status Feedback Register */
|
||||
#define I2S_STATE(port) MMIO32(port + 0x010)
|
||||
#define I2S0_STATE I2S_STATE(I2S0)
|
||||
#define I2S1_STATE I2S_STATE(I2S1)
|
||||
|
||||
/* I2S DMA Configuration Register 1 */
|
||||
#define I2S_DMA1(port) MMIO32(port + 0x014)
|
||||
#define I2S0_DMA1 I2S_DMA1(I2S0)
|
||||
#define I2S1_DMA1 I2S_DMA1(I2S1)
|
||||
|
||||
/* I2S DMA Configuration Register 2 */
|
||||
#define I2S_DMA2(port) MMIO32(port + 0x018)
|
||||
#define I2S0_DMA2 I2S_DMA2(I2S0)
|
||||
#define I2S1_DMA2 I2S_DMA2(I2S1)
|
||||
|
||||
/* I2S Interrupt Request Control Register */
|
||||
#define I2S_IRQ(port) MMIO32(port + 0x01C)
|
||||
#define I2S0_IRQ I2S_IRQ(I2S0)
|
||||
#define I2S1_IRQ I2S_IRQ(I2S1)
|
||||
|
||||
/* I2S Transmit MCLK divider */
|
||||
#define I2S_TXRATE(port) MMIO32(port + 0x020)
|
||||
#define I2S0_TXRATE I2S_TXRATE(I2S0)
|
||||
#define I2S1_TXRATE I2S_TXRATE(I2S1)
|
||||
|
||||
/* I2S Receive MCLK divider */
|
||||
#define I2S_RXRATE(port) MMIO32(port + 0x024)
|
||||
#define I2S0_RXRATE I2S_RXRATE(I2S0)
|
||||
#define I2S1_RXRATE I2S_RXRATE(I2S1)
|
||||
|
||||
/* I2S Transmit bit rate divider */
|
||||
#define I2S_TXBITRATE(port) MMIO32(port + 0x028)
|
||||
#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0)
|
||||
#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1)
|
||||
|
||||
/* I2S Receive bit rate divider */
|
||||
#define I2S_RXBITRATE(port) MMIO32(port + 0x02C)
|
||||
#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0)
|
||||
#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1)
|
||||
|
||||
/* I2S Transmit mode control */
|
||||
#define I2S_TXMODE(port) MMIO32(port + 0x030)
|
||||
#define I2S0_TXMODE I2S_TXMODE(I2S0)
|
||||
#define I2S1_TXMODE I2S_TXMODE(I2S1)
|
||||
|
||||
/* I2S Receive mode control */
|
||||
#define I2S_RXMODE(port) MMIO32(port + 0x034)
|
||||
#define I2S0_RXMODE I2S_RXMODE(I2S0)
|
||||
#define I2S1_RXMODE I2S_RXMODE(I2S1)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_MEMORYMAP_H
|
||||
#define LPC43XX_MEMORYMAP_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- LPC43XX specific peripheral definitions ----------------------------- */
|
||||
|
||||
/* Memory map for all busses */
|
||||
#define PERIPH_BASE_AHB 0x40000000
|
||||
#define PERIPH_BASE_APB0 0x40080000
|
||||
#define PERIPH_BASE_APB1 0x400A0000
|
||||
#define PERIPH_BASE_APB2 0x400C0000
|
||||
#define PERIPH_BASE_APB3 0x400E0000
|
||||
|
||||
/* Register boundary addresses */
|
||||
|
||||
/* AHB (0x4000 0000 - 0x4001 2000) */
|
||||
#define SCT_BASE (PERIPH_BASE_AHB + 0x00000)
|
||||
/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
|
||||
#define DMA_BASE (PERIPH_BASE_AHB + 0x02000)
|
||||
#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)
|
||||
#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000)
|
||||
#define EMC_BASE (PERIPH_BASE_AHB + 0x05000)
|
||||
#define USB0_BASE (PERIPH_BASE_AHB + 0x06000)
|
||||
#define USB1_BASE (PERIPH_BASE_AHB + 0x07000)
|
||||
#define LCD_BASE (PERIPH_BASE_AHB + 0x08000)
|
||||
/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
|
||||
#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
|
||||
|
||||
/* 0x4001 2000 - 0x4003 FFFF Reserved */
|
||||
|
||||
/* RTC domain peripherals */
|
||||
#define ATIMER_BASE 0x40040000
|
||||
#define BACKUP_REG_BASE 0x40041000
|
||||
#define PMC_BASE 0x40042000
|
||||
#define CREG_BASE 0x40043000
|
||||
#define EVENTROUTER_BASE 0x40044000
|
||||
#define OTP_BASE 0x40045000
|
||||
#define RTC_BASE 0x40046000
|
||||
/* 0x4004 7000 - 0x4004 FFFF Reserved */
|
||||
|
||||
/* clocking/reset control peripherals */
|
||||
#define CGU_BASE 0x40050000
|
||||
#define CCU1_BASE 0x40051000
|
||||
#define CCU2_BASE 0x40052000
|
||||
#define RGU_BASE 0x40053000
|
||||
/* 0x4005 4000 - 0x4005 FFFF Reserved */
|
||||
|
||||
/* 0x4006 0000 - 0x4007 FFFF Reserved */
|
||||
|
||||
/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
|
||||
#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)
|
||||
#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000)
|
||||
#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000)
|
||||
#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)
|
||||
#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
|
||||
#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)
|
||||
#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000)
|
||||
#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)
|
||||
#define GPIO_GROUP0_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)
|
||||
#define GPIO_GROUP1_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)
|
||||
/* 0x4008 A000 - 0x4008 FFFF Reserved */
|
||||
|
||||
/* 0x4009 0000 - 0x4009 FFFF Reserved */
|
||||
|
||||
/* APB1 (0x400A 0000 - 0x400A FFFF) */
|
||||
#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)
|
||||
#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)
|
||||
#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)
|
||||
#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)
|
||||
#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)
|
||||
/* 0x400A 5000 - 0x400A FFFF Reserved */
|
||||
|
||||
/* 0x400B 0000 - 0x400B FFFF Reserved */
|
||||
|
||||
/* APB2 (0x400C 0000 - 0x400C FFFF) */
|
||||
#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)
|
||||
#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000)
|
||||
#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000)
|
||||
#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)
|
||||
#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)
|
||||
#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)
|
||||
#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000)
|
||||
#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000)
|
||||
/* 0x400C 8000 - 0x400C FFFF Reserved */
|
||||
|
||||
/* 0x400D 0000 - 0x400D FFFF Reserved */
|
||||
|
||||
/* APB3 (0x400E 0000 - 0x400E FFFF) */
|
||||
#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)
|
||||
#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000)
|
||||
#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)
|
||||
#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000)
|
||||
#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)
|
||||
/* 0x400E 5000 - 0x400E FFFF Reserved */
|
||||
|
||||
/* 0x400F 0000 - 0x400F 0FFF Reserved */
|
||||
|
||||
#define AES_BASE 0x400F1000
|
||||
|
||||
/* 0x400F 2000 - 0x400F 3FFF Reserved */
|
||||
|
||||
#define GPIO_PORT_BASE 0x400F4000
|
||||
|
||||
/* 0x400F 8000 - 0x400F FFFF Reserved */
|
||||
|
||||
#define SPI_PORT_BASE 0x40100000
|
||||
#define SGPIO_PORT_BASE 0x40101000
|
||||
|
||||
/* 0x4010 2000 - 0x41FF FFFF Reserved */
|
||||
|
||||
/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
|
||||
|
||||
/* 0x4400 0000 - 0x5FFF FFFF Reserved */
|
||||
|
||||
/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
|
||||
|
||||
#endif
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_NVIC_H
|
||||
#define LPC43XX_NVIC_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/cm3/memorymap.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- NVIC Registers ------------------------------------------------------ */
|
||||
|
||||
/* ISER: Interrupt Set Enable Registers */
|
||||
/* Note: 8 32bit Registers */
|
||||
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
|
||||
|
||||
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
|
||||
|
||||
/* ICER: Interrupt Clear Enable Registers */
|
||||
/* Note: 8 32bit Registers */
|
||||
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
|
||||
|
||||
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
|
||||
|
||||
/* ISPR: Interrupt Set Pending Registers */
|
||||
/* Note: 8 32bit Registers */
|
||||
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
|
||||
|
||||
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
|
||||
|
||||
/* ICPR: Interrupt Clear Pending Registers */
|
||||
/* Note: 8 32bit Registers */
|
||||
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
|
||||
|
||||
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
|
||||
|
||||
/* IABR: Interrupt Active Bit Register */
|
||||
/* Note: 8 32bit Registers */
|
||||
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
|
||||
|
||||
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
|
||||
|
||||
/* IPR: Interrupt Priority Registers */
|
||||
/* Note: 240 8bit Registers */
|
||||
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
|
||||
|
||||
/* STIR: Software Trigger Interrupt Register */
|
||||
#define NVIC_STIR MMIO32(STIR_BASE)
|
||||
|
||||
/* --- IRQ channel numbers-------------------------------------------------- */
|
||||
|
||||
/* Cortex M4 System Interrupts */
|
||||
#define NVIC_NMI_IRQ -14
|
||||
#define NVIC_HARD_FAULT_IRQ -13
|
||||
#define NVIC_MEM_MANAGE_IRQ -12
|
||||
#define NVIC_BUS_FAULT_IRQ -11
|
||||
#define NVIC_USAGE_FAULT_IRQ -10
|
||||
/* irq numbers -6 to -9 are reserved */
|
||||
#define NVIC_SV_CALL_IRQ -5
|
||||
#define DEBUG_MONITOR_IRQ -4
|
||||
/* irq number -3 reserved */
|
||||
#define NVIC_PENDSV_IRQ -2
|
||||
#define NVIC_SYSTICK_IRQ -1
|
||||
|
||||
/* LPC43xx M4 specific user interrupts */
|
||||
#define NVIC_M4_DAC_IRQ 0
|
||||
#define NVIC_M4_M0CORE_IRQ 1
|
||||
#define NVIC_M4_DMA_IRQ 2
|
||||
#define NVIC_M4_ETHERNET_IRQ 5
|
||||
#define NVIC_M4_SDIO_IRQ 6
|
||||
#define NVIC_M4_LCD_IRQ 7
|
||||
#define NVIC_M4_USB0_IRQ 8
|
||||
#define NVIC_M4_USB1_IRQ 9
|
||||
#define NVIC_M4_SCT_IRQ 10
|
||||
#define NVIC_M4_RITIMER_IRQ 11
|
||||
#define NVIC_M4_TIMER0_IRQ 12
|
||||
#define NVIC_M4_TIMER1_IRQ 13
|
||||
#define NVIC_M4_TIMER2_IRQ 14
|
||||
#define NVIC_M4_TIMER3_IRQ 15
|
||||
#define NVIC_M4_MCPWM_IRQ 16
|
||||
#define NVIC_M4_ADC0_IRQ 17
|
||||
#define NVIC_M4_I2C0_IRQ 18
|
||||
#define NVIC_M4_I2C1_IRQ 19
|
||||
#define NVIC_M4_SPI_IRQ 20
|
||||
#define NVIC_M4_ADC1_IRQ 21
|
||||
#define NVIC_M4_SSP0_IRQ 22
|
||||
#define NVIC_M4_SSP1_IRQ 23
|
||||
#define NVIC_M4_USART0_IRQ 24
|
||||
#define NVIC_M4_UART1_IRQ 25
|
||||
#define NVIC_M4_USART2_IRQ 26
|
||||
#define NVIC_M4_USART3_IRQ 27
|
||||
#define NVIC_M4_I2S0_IRQ 28
|
||||
#define NVIC_M4_I2S1_IRQ 29
|
||||
#define NVIC_M4_SPIFI_IRQ 30
|
||||
#define NVIC_M4_SGPIO_IRQ 31
|
||||
#define NVIC_M4_PIN_INT0_IRQ 32
|
||||
#define NVIC_M4_PIN_INT1_IRQ 33
|
||||
#define NVIC_M4_PIN_INT2_IRQ 34
|
||||
#define NVIC_M4_PIN_INT3_IRQ 35
|
||||
#define NVIC_M4_PIN_INT4_IRQ 36
|
||||
#define NVIC_M4_PIN_INT5_IRQ 37
|
||||
#define NVIC_M4_PIN_INT6_IRQ 38
|
||||
#define NVIC_M4_PIN_INT7_IRQ 39
|
||||
#define NVIC_M4_GINT0_IRQ 40
|
||||
#define NVIC_M4_GINT1_IRQ 41
|
||||
#define NVIC_M4_EVENTROUTER_IRQ 42
|
||||
#define NVIC_M4_C_CAN1_IRQ 43
|
||||
#define NVIC_M4_ATIMER_IRQ 46
|
||||
#define NVIC_M4_RTC_IRQ 47
|
||||
#define NVIC_M4_WWDT_IRQ 49
|
||||
#define NVIC_M4_C_CAN0_IRQ 51
|
||||
#define NVIC_M4_QEI_IRQ 52
|
||||
|
||||
/* LPC43xx M0 specific user interrupts */
|
||||
//TODO
|
||||
|
||||
/* --- NVIC functions ------------------------------------------------------ */
|
||||
|
||||
void nvic_enable_irq(u8 irqn);
|
||||
void nvic_disable_irq(u8 irqn);
|
||||
u8 nvic_get_pending_irq(u8 irqn);
|
||||
void nvic_set_pending_irq(u8 irqn);
|
||||
void nvic_clear_pending_irq(u8 irqn);
|
||||
u8 nvic_get_active_irq(u8 irqn);
|
||||
u8 nvic_get_irq_enabled(u8 irqn);
|
||||
void nvic_set_priority(u8 irqn, u8 priority);
|
||||
void nvic_generate_software_interrupt(u8 irqn);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_RGU_H
|
||||
#define LPC43XX_RGU_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- RGU registers ------------------------------------------------------- */
|
||||
|
||||
/* Reset control register 0 */
|
||||
#define RESET_CTRL0 MMIO32(RGU_BASE + 0x100)
|
||||
|
||||
/* Reset control register 1 */
|
||||
#define RESET_CTRL1 MMIO32(RGU_BASE + 0x104)
|
||||
|
||||
/* Reset status register 0 */
|
||||
#define RESET_STATUS0 MMIO32(RGU_BASE + 0x110)
|
||||
|
||||
/* Reset status register 1 */
|
||||
#define RESET_STATUS1 MMIO32(RGU_BASE + 0x114)
|
||||
|
||||
/* Reset status register 2 */
|
||||
#define RESET_STATUS2 MMIO32(RGU_BASE + 0x118)
|
||||
|
||||
/* Reset status register 3 */
|
||||
#define RESET_STATUS3 MMIO32(RGU_BASE + 0x11C)
|
||||
|
||||
/* Reset active status register 0 */
|
||||
#define RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150)
|
||||
|
||||
/* Reset active status register 1 */
|
||||
#define RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154)
|
||||
|
||||
/* Reset external status register 0 for CORE_RST */
|
||||
#define RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400)
|
||||
|
||||
/* Reset external status register 1 for PERIPH_RST */
|
||||
#define RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404)
|
||||
|
||||
/* Reset external status register 2 for MASTER_RST */
|
||||
#define RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C)
|
||||
|
||||
/* Reset external status register 4 for WWDT_RST */
|
||||
#define RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410)
|
||||
|
||||
/* Reset external status register 5 for CREG_RST */
|
||||
#define RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C)
|
||||
|
||||
/* Reset external status register 8 for BUS_RST */
|
||||
#define RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420)
|
||||
|
||||
/* Reset external status register 9 for SCU_RST */
|
||||
#define RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430)
|
||||
|
||||
/* Reset external status register 13 for M4_RST */
|
||||
#define RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C)
|
||||
|
||||
/* Reset external status register 16 for LCD_RST */
|
||||
#define RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440)
|
||||
|
||||
/* Reset external status register 17 for USB0_RST */
|
||||
#define RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444)
|
||||
|
||||
/* Reset external status register 18 for USB1_RST */
|
||||
#define RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448)
|
||||
|
||||
/* Reset external status register 19 for DMA_RST */
|
||||
#define RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C)
|
||||
|
||||
/* Reset external status register 20 for SDIO_RST */
|
||||
#define RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450)
|
||||
|
||||
/* Reset external status register 21 for EMC_RST */
|
||||
#define RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454)
|
||||
|
||||
/* Reset external status register 22 for ETHERNET_RST */
|
||||
#define RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C)
|
||||
|
||||
/* Reset external status register 28 for GPIO_RST */
|
||||
#define RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C)
|
||||
|
||||
/* Reset external status register 32 for TIMER0_RST */
|
||||
#define RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480)
|
||||
|
||||
/* Reset external status register 33 for TIMER1_RST */
|
||||
#define RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484)
|
||||
|
||||
/* Reset external status register 34 for TIMER2_RST */
|
||||
#define RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488)
|
||||
|
||||
/* Reset external status register 35 for TIMER3_RST */
|
||||
#define RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C)
|
||||
|
||||
/* Reset external status register 36 for RITIMER_RST */
|
||||
#define RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490)
|
||||
|
||||
/* Reset external status register 37 for SCT_RST */
|
||||
#define RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494)
|
||||
|
||||
/* Reset external status register 38 for MOTOCONPWM_RST */
|
||||
#define RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498)
|
||||
|
||||
/* Reset external status register 39 for QEI_RST */
|
||||
#define RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C)
|
||||
|
||||
/* Reset external status register 40 for ADC0_RST */
|
||||
#define RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0)
|
||||
|
||||
/* Reset external status register 41 for ADC1_RST */
|
||||
#define RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4)
|
||||
|
||||
/* Reset external status register 42 for DAC_RST */
|
||||
#define RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC)
|
||||
|
||||
/* Reset external status register 44 for UART0_RST */
|
||||
#define RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0)
|
||||
|
||||
/* Reset external status register 45 for UART1_RST */
|
||||
#define RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4)
|
||||
|
||||
/* Reset external status register 46 for UART2_RST */
|
||||
#define RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8)
|
||||
|
||||
/* Reset external status register 47 for UART3_RST */
|
||||
#define RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC)
|
||||
|
||||
/* Reset external status register 48 for I2C0_RST */
|
||||
#define RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0)
|
||||
|
||||
/* Reset external status register 49 for I2C1_RST */
|
||||
#define RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4)
|
||||
|
||||
/* Reset external status register 50 for SSP0_RST */
|
||||
#define RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8)
|
||||
|
||||
/* Reset external status register 51 for SSP1_RST */
|
||||
#define RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC)
|
||||
|
||||
/* Reset external status register 52 for I2S_RST */
|
||||
#define RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0)
|
||||
|
||||
/* Reset external status register 53 for SPIFI_RST */
|
||||
#define RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4)
|
||||
|
||||
/* Reset external status register 54 for CAN1_RST */
|
||||
#define RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8)
|
||||
|
||||
/* Reset external status register 55 for CAN0_RST */
|
||||
#define RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC)
|
||||
|
||||
/* Reset external status register 56 for M0APP_RST */
|
||||
#define RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0)
|
||||
|
||||
/* Reset external status register 57 for SGPIO_RST */
|
||||
#define RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4)
|
||||
|
||||
/* Reset external status register 58 for SPI_RST */
|
||||
#define RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8)
|
||||
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_RITIMER_H
|
||||
#define LPC43XX_RITIMER_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Repetitive Interrupt Timer registers -------------------------------- */
|
||||
|
||||
/* Compare register */
|
||||
#define RITIMER_COMPVAL MMIO32(RITIMER_BASE + 0x000)
|
||||
|
||||
/* Mask register */
|
||||
#define RITIMER_MASK MMIO32(RITIMER_BASE + 0x004)
|
||||
|
||||
/* Control register */
|
||||
#define RITIMER_CTRL MMIO32(RITIMER_BASE + 0x008)
|
||||
|
||||
/* 32-bit counter */
|
||||
#define RITIMER_COUNTER MMIO32(RITIMER_BASE + 0x00C)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,730 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_SCU_H
|
||||
#define LPC43XX_SCU_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* Pin group base addresses */
|
||||
#define PIN_GROUP0 (SCU_BASE + 0x000)
|
||||
#define PIN_GROUP1 (SCU_BASE + 0x080)
|
||||
#define PIN_GROUP2 (SCU_BASE + 0x100)
|
||||
#define PIN_GROUP3 (SCU_BASE + 0x180)
|
||||
#define PIN_GROUP4 (SCU_BASE + 0x200)
|
||||
#define PIN_GROUP5 (SCU_BASE + 0x280)
|
||||
#define PIN_GROUP6 (SCU_BASE + 0x300)
|
||||
#define PIN_GROUP7 (SCU_BASE + 0x380)
|
||||
#define PIN_GROUP8 (SCU_BASE + 0x400)
|
||||
#define PIN_GROUP9 (SCU_BASE + 0x480)
|
||||
#define PIN_GROUPA (SCU_BASE + 0x500)
|
||||
#define PIN_GROUPB (SCU_BASE + 0x580)
|
||||
#define PIN_GROUPC (SCU_BASE + 0x600)
|
||||
#define PIN_GROUPD (SCU_BASE + 0x680)
|
||||
#define PIN_GROUPE (SCU_BASE + 0x700)
|
||||
#define PIN_GROUPF (SCU_BASE + 0x780)
|
||||
|
||||
#define PIN0 0x000
|
||||
#define PIN1 0x004
|
||||
#define PIN2 0x008
|
||||
#define PIN3 0x00C
|
||||
#define PIN4 0x010
|
||||
#define PIN5 0x014
|
||||
#define PIN6 0x018
|
||||
#define PIN7 0x01C
|
||||
#define PIN8 0x020
|
||||
#define PIN9 0x024
|
||||
#define PIN10 0x028
|
||||
#define PIN11 0x02C
|
||||
#define PIN12 0x030
|
||||
#define PIN13 0x034
|
||||
#define PIN14 0x038
|
||||
#define PIN15 0x03C
|
||||
#define PIN16 0x040
|
||||
#define PIN17 0x044
|
||||
#define PIN18 0x048
|
||||
#define PIN19 0x04C
|
||||
#define PIN20 0x050
|
||||
|
||||
|
||||
/* --- SCU registers ------------------------------------------------------- */
|
||||
|
||||
/* Pin configuration registers */
|
||||
|
||||
#define SCU_SFS(group, pin) MMIO32(group + pin)
|
||||
|
||||
/* Pins P0_n */
|
||||
#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0)
|
||||
#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1)
|
||||
|
||||
/* Pins P1_n */
|
||||
#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0)
|
||||
#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1)
|
||||
#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2)
|
||||
#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3)
|
||||
#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4)
|
||||
#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5)
|
||||
#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6)
|
||||
#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7)
|
||||
#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8)
|
||||
#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9)
|
||||
#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10)
|
||||
#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11)
|
||||
#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12)
|
||||
#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13)
|
||||
#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14)
|
||||
#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15)
|
||||
#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16)
|
||||
#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17)
|
||||
#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18)
|
||||
#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19)
|
||||
#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20)
|
||||
|
||||
/* Pins P2_n */
|
||||
#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0)
|
||||
#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1)
|
||||
#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2)
|
||||
#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3)
|
||||
#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4)
|
||||
#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5)
|
||||
#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6)
|
||||
#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7)
|
||||
#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8)
|
||||
#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9)
|
||||
#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10)
|
||||
#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11)
|
||||
#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12)
|
||||
#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13)
|
||||
|
||||
/* Pins P3_n */
|
||||
#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0)
|
||||
#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1)
|
||||
#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2)
|
||||
#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3)
|
||||
#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4)
|
||||
#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5)
|
||||
#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6)
|
||||
#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7)
|
||||
#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8)
|
||||
|
||||
/* Pins P4_n */
|
||||
#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0)
|
||||
#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1)
|
||||
#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2)
|
||||
#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3)
|
||||
#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4)
|
||||
#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5)
|
||||
#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6)
|
||||
#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7)
|
||||
#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8)
|
||||
#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9)
|
||||
#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10)
|
||||
|
||||
/* Pins P5_n */
|
||||
#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0)
|
||||
#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1)
|
||||
#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2)
|
||||
#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3)
|
||||
#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4)
|
||||
#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5)
|
||||
#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6)
|
||||
#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7)
|
||||
|
||||
/* Pins P6_n */
|
||||
#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0)
|
||||
#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1)
|
||||
#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2)
|
||||
#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3)
|
||||
#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4)
|
||||
#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5)
|
||||
#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6)
|
||||
#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7)
|
||||
#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8)
|
||||
#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9)
|
||||
#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10)
|
||||
#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11)
|
||||
#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12)
|
||||
|
||||
/* Pins P7_n */
|
||||
#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0)
|
||||
#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1)
|
||||
#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2)
|
||||
#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3)
|
||||
#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4)
|
||||
#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5)
|
||||
#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6)
|
||||
#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7)
|
||||
|
||||
/* Pins P8_n */
|
||||
#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0)
|
||||
#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1)
|
||||
#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2)
|
||||
#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3)
|
||||
#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4)
|
||||
#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5)
|
||||
#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6)
|
||||
#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7)
|
||||
#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8)
|
||||
|
||||
/* Pins P9_n */
|
||||
#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0)
|
||||
#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1)
|
||||
#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2)
|
||||
#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3)
|
||||
#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4)
|
||||
#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5)
|
||||
#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6)
|
||||
|
||||
/* Pins PA_n */
|
||||
#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0)
|
||||
#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1)
|
||||
#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2)
|
||||
#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3)
|
||||
#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4)
|
||||
|
||||
/* Pins PB_n */
|
||||
#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0)
|
||||
#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1)
|
||||
#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2)
|
||||
#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3)
|
||||
#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4)
|
||||
#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5)
|
||||
#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6)
|
||||
|
||||
/* Pins PC_n */
|
||||
#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0)
|
||||
#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1)
|
||||
#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2)
|
||||
#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3)
|
||||
#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4)
|
||||
#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5)
|
||||
#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6)
|
||||
#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7)
|
||||
#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8)
|
||||
#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9)
|
||||
#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10)
|
||||
#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11)
|
||||
#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12)
|
||||
#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13)
|
||||
#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14)
|
||||
|
||||
/* Pins PD_n */
|
||||
#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0)
|
||||
#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1)
|
||||
#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2)
|
||||
#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3)
|
||||
#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4)
|
||||
#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5)
|
||||
#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6)
|
||||
#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7)
|
||||
#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8)
|
||||
#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9)
|
||||
#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10)
|
||||
#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11)
|
||||
#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12)
|
||||
#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13)
|
||||
#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14)
|
||||
#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15)
|
||||
#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16)
|
||||
|
||||
/* Pins PE_n */
|
||||
#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0)
|
||||
#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1)
|
||||
#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2)
|
||||
#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3)
|
||||
#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4)
|
||||
#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5)
|
||||
#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6)
|
||||
#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7)
|
||||
#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8)
|
||||
#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9)
|
||||
#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10)
|
||||
#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11)
|
||||
#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12)
|
||||
#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13)
|
||||
#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14)
|
||||
#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15)
|
||||
|
||||
/* Pins PF_n */
|
||||
#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0)
|
||||
#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1)
|
||||
#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2)
|
||||
#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3)
|
||||
#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4)
|
||||
#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5)
|
||||
#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6)
|
||||
#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7)
|
||||
#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8)
|
||||
#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9)
|
||||
#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10)
|
||||
#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11)
|
||||
|
||||
/* CLKn pins */
|
||||
#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00)
|
||||
#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04)
|
||||
#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08)
|
||||
#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C)
|
||||
|
||||
/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */
|
||||
#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80)
|
||||
#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84)
|
||||
|
||||
/* ADC pin select registers */
|
||||
|
||||
/* ADC0 function select register */
|
||||
#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88)
|
||||
|
||||
/* ADC1 function select register */
|
||||
#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C)
|
||||
|
||||
/* Analog function select register */
|
||||
#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90)
|
||||
|
||||
/* EMC clock delay register */
|
||||
#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00)
|
||||
|
||||
/* Pin interrupt select registers */
|
||||
|
||||
/* Pin interrupt select register for pin interrupts 0 to 3 */
|
||||
#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00)
|
||||
|
||||
/* Pin interrupt select register for pin interrupts 4 to 7 */
|
||||
#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04)
|
||||
|
||||
/**************************/
|
||||
/* SCU I2C0 Configuration */
|
||||
/**************************/
|
||||
/*
|
||||
* Select input glitch filter time constant for the SCL pin.
|
||||
* 0 = 50 ns glitch filter.
|
||||
* 1 = 3ns glitch filter.
|
||||
*/
|
||||
#define SCU_SCL_EFP (BIT0)
|
||||
|
||||
/* BIT1 Reserved. Always write a 0 to this bit. */
|
||||
|
||||
/*
|
||||
* Select I2C mode for the SCL pin.
|
||||
* 0 = Standard/Fast mode transmit.
|
||||
* 1 = Fast-mode Plus transmit.
|
||||
*/
|
||||
#define SCU_SCL_EHD (BIT2)
|
||||
|
||||
/*
|
||||
* Enable the input receiver for the SCL pin.
|
||||
* Always write a 1 to this bit when using the
|
||||
* I2C0.
|
||||
* 0 = Disabled.
|
||||
* 1 = Enabled.
|
||||
*/
|
||||
#define SCU_SCL_EZI_EN (BIT3)
|
||||
|
||||
/* BIT4-6 Reserved. */
|
||||
|
||||
/*
|
||||
* Enable or disable input glitch filter for the
|
||||
* SCL pin. The filter time constant is
|
||||
* determined by bit EFP.
|
||||
* 0 = Enable input filter.
|
||||
* 1 = Disable input filter.
|
||||
*/
|
||||
#define SCU_SCL_ZIF_DIS (BIT7)
|
||||
|
||||
/*
|
||||
* Select input glitch filter time constant for the SDA pin.
|
||||
* 0 = 50 ns glitch filter.
|
||||
* 1 = 3ns glitch filter.
|
||||
*/
|
||||
#define SCU_SDA_EFP (BIT8)
|
||||
|
||||
/* BIT9 Reserved. Always write a 0 to this bit. */
|
||||
|
||||
/*
|
||||
* Select I2C mode for the SDA pin.
|
||||
* 0 = Standard/Fast mode transmit.
|
||||
* 1 = Fast-mode Plus transmit.
|
||||
*/
|
||||
#define SCU_SDA_EHD (BIT10)
|
||||
|
||||
/*
|
||||
* Enable the input receiver for the SDA pin.
|
||||
* Always write a 1 to this bit when using the
|
||||
* I2C0.
|
||||
* 0 = Disabled.
|
||||
* 1 = Enabled.
|
||||
*/
|
||||
#define SCU_SDA_EZI_EN (BIT11)
|
||||
|
||||
/* BIT 12-14 - Reserved */
|
||||
|
||||
/*
|
||||
* Enable or disable input glitch filter for the
|
||||
* SDA pin. The filter time constant is
|
||||
* determined by bit SDA_EFP.
|
||||
* 0 = Enable input filter.
|
||||
* 1 = Disable input filter.
|
||||
*/
|
||||
#define SCU_SDA_ZIF_DIS (BIT15)
|
||||
|
||||
/* Standard mode for I2C SCL/SDA Standard/Fast mode */
|
||||
#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)
|
||||
|
||||
/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */
|
||||
#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \
|
||||
SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)
|
||||
|
||||
/*
|
||||
* SCU PIN Normal Drive:
|
||||
* The pin configuration registers for normal-drive pins control the following pins:
|
||||
* - P0_0 and P0_1
|
||||
* - P1_0 to P1_16 and P1_18 to P1_20
|
||||
* - P2_0 to P2_2 and P2_6 to P2_13
|
||||
* - P3_0 to P3_2 and P3_4 to P3_8
|
||||
* - P4_0 to P4_10
|
||||
* - P5_0 to P5_7
|
||||
* - P6_0 to P6_12
|
||||
* - P7_0 to P7_7
|
||||
* - P8_3 to P8_8
|
||||
* - P9_0 to P9_6
|
||||
* - PA_0 and PA_4
|
||||
* - PB_0 to PB_6
|
||||
* - PC_0 to PC_14
|
||||
* - PE_0 to PE_15
|
||||
* - PF_0 to PF_11
|
||||
*
|
||||
* Pin configuration registers for High-Drive pins.
|
||||
* The pin configuration registers for high-drive pins control the following pins:
|
||||
* - P1_17
|
||||
* - P2_3 to P2_5
|
||||
* - P8_0 to P8_2
|
||||
* - PA_1 to PA_3
|
||||
*
|
||||
* Pin configuration registers for High-Speed pins.
|
||||
* This register controls the following pins:
|
||||
* - P3_3 and pins CLK0 to CLK3.
|
||||
*/
|
||||
typedef enum {
|
||||
/* Group Port 0 */
|
||||
P0_0 = (PIN_GROUP0+PIN0),
|
||||
P0_1 = (PIN_GROUP0+PIN1),
|
||||
|
||||
/* Group Port 1 */
|
||||
P1_0 = (PIN_GROUP1+PIN0),
|
||||
P1_1 = (PIN_GROUP1+PIN1),
|
||||
P1_2 = (PIN_GROUP1+PIN2),
|
||||
P1_3 = (PIN_GROUP1+PIN3),
|
||||
P1_4 = (PIN_GROUP1+PIN4),
|
||||
P1_5 = (PIN_GROUP1+PIN5),
|
||||
P1_6 = (PIN_GROUP1+PIN6),
|
||||
P1_7 = (PIN_GROUP1+PIN7),
|
||||
P1_8 = (PIN_GROUP1+PIN8),
|
||||
P1_9 = (PIN_GROUP1+PIN9),
|
||||
P1_10 = (PIN_GROUP1+PIN10),
|
||||
P1_11 = (PIN_GROUP1+PIN11),
|
||||
P1_12 = (PIN_GROUP1+PIN12),
|
||||
P1_13 = (PIN_GROUP1+PIN13),
|
||||
P1_14 = (PIN_GROUP1+PIN14),
|
||||
P1_15 = (PIN_GROUP1+PIN15),
|
||||
P1_16 = (PIN_GROUP1+PIN16),
|
||||
|
||||
/* P1_17 is High-Drive pin */
|
||||
P1_17 = (PIN_GROUP1+PIN17),
|
||||
|
||||
P1_18 = (PIN_GROUP1+PIN18),
|
||||
P1_19 = (PIN_GROUP1+PIN19),
|
||||
P1_20 = (PIN_GROUP1+PIN20),
|
||||
|
||||
/* Group Port 2 */
|
||||
P2_0 = (PIN_GROUP2+PIN0),
|
||||
P2_1 = (PIN_GROUP2+PIN1),
|
||||
P2_2 = (PIN_GROUP2+PIN2),
|
||||
|
||||
/* P2_3 to P2_5 are High-Drive pins */
|
||||
P2_3 = (PIN_GROUP2+PIN3),
|
||||
P2_4 = (PIN_GROUP2+PIN4),
|
||||
P2_5 = (PIN_GROUP2+PIN5),
|
||||
|
||||
P2_6 = (PIN_GROUP2+PIN6),
|
||||
P2_7 = (PIN_GROUP2+PIN7),
|
||||
P2_8 = (PIN_GROUP2+PIN8),
|
||||
P2_9 = (PIN_GROUP2+PIN9),
|
||||
P2_10 = (PIN_GROUP2+PIN10),
|
||||
P2_11 = (PIN_GROUP2+PIN11),
|
||||
P2_12 = (PIN_GROUP2+PIN12),
|
||||
P2_13 = (PIN_GROUP2+PIN13),
|
||||
|
||||
/* Group Port 3 */
|
||||
P3_0 = (PIN_GROUP3+PIN0),
|
||||
P3_1 = (PIN_GROUP3+PIN1),
|
||||
P3_2 = (PIN_GROUP3+PIN2),
|
||||
|
||||
/* P3_3 is High-Speed pin */
|
||||
P3_3 = (PIN_GROUP3+PIN3),
|
||||
|
||||
P3_4 = (PIN_GROUP3+PIN4),
|
||||
P3_5 = (PIN_GROUP3+PIN5),
|
||||
P3_6 = (PIN_GROUP3+PIN6),
|
||||
P3_7 = (PIN_GROUP3+PIN7),
|
||||
P3_8 = (PIN_GROUP3+PIN8),
|
||||
|
||||
/* Group Port 4 */
|
||||
P4_0 = (PIN_GROUP4+PIN0),
|
||||
P4_1 = (PIN_GROUP4+PIN1),
|
||||
P4_2 = (PIN_GROUP4+PIN2),
|
||||
P4_3 = (PIN_GROUP4+PIN3),
|
||||
P4_4 = (PIN_GROUP4+PIN4),
|
||||
P4_5 = (PIN_GROUP4+PIN5),
|
||||
P4_6 = (PIN_GROUP4+PIN6),
|
||||
P4_7 = (PIN_GROUP4+PIN7),
|
||||
P4_8 = (PIN_GROUP4+PIN8),
|
||||
P4_9 = (PIN_GROUP4+PIN9),
|
||||
P4_10 = (PIN_GROUP4+PIN10),
|
||||
|
||||
/* Group Port 5 */
|
||||
P5_0 = (PIN_GROUP5+PIN0),
|
||||
P5_1 = (PIN_GROUP5+PIN1),
|
||||
P5_2 = (PIN_GROUP5+PIN2),
|
||||
P5_3 = (PIN_GROUP5+PIN3),
|
||||
P5_4 = (PIN_GROUP5+PIN4),
|
||||
P5_5 = (PIN_GROUP5+PIN5),
|
||||
P5_6 = (PIN_GROUP5+PIN6),
|
||||
P5_7 = (PIN_GROUP5+PIN7),
|
||||
|
||||
/* Group Port 6 */
|
||||
P6_0 = (PIN_GROUP6+PIN0),
|
||||
P6_1 = (PIN_GROUP6+PIN1),
|
||||
P6_2 = (PIN_GROUP6+PIN2),
|
||||
P6_3 = (PIN_GROUP6+PIN3),
|
||||
P6_4 = (PIN_GROUP6+PIN4),
|
||||
P6_5 = (PIN_GROUP6+PIN5),
|
||||
P6_6 = (PIN_GROUP6+PIN6),
|
||||
P6_7 = (PIN_GROUP6+PIN7),
|
||||
P6_8 = (PIN_GROUP6+PIN8),
|
||||
P6_9 = (PIN_GROUP6+PIN9),
|
||||
P6_10 = (PIN_GROUP6+PIN10),
|
||||
P6_11 = (PIN_GROUP6+PIN11),
|
||||
P6_12 = (PIN_GROUP6+PIN12),
|
||||
|
||||
/* Group Port 7 */
|
||||
P7_0 = (PIN_GROUP7+PIN0),
|
||||
P7_1 = (PIN_GROUP7+PIN1),
|
||||
P7_2 = (PIN_GROUP7+PIN2),
|
||||
P7_3 = (PIN_GROUP7+PIN3),
|
||||
P7_4 = (PIN_GROUP7+PIN4),
|
||||
P7_5 = (PIN_GROUP7+PIN5),
|
||||
P7_6 = (PIN_GROUP7+PIN6),
|
||||
P7_7 = (PIN_GROUP7+PIN7),
|
||||
|
||||
/* Group Port 8 */
|
||||
/* P8_0 to P8_2 are High-Drive pins */
|
||||
P8_0 = (PIN_GROUP8+PIN0),
|
||||
P8_1 = (PIN_GROUP8+PIN1),
|
||||
P8_2 = (PIN_GROUP8+PIN2),
|
||||
|
||||
P8_3 = (PIN_GROUP8+PIN3),
|
||||
P8_4 = (PIN_GROUP8+PIN4),
|
||||
P8_5 = (PIN_GROUP8+PIN5),
|
||||
P8_6 = (PIN_GROUP8+PIN6),
|
||||
P8_7 = (PIN_GROUP8+PIN7),
|
||||
P8_8 = (PIN_GROUP8+PIN8),
|
||||
|
||||
/* Group Port 9 */
|
||||
P9_0 = (PIN_GROUP9+PIN0),
|
||||
P9_1 = (PIN_GROUP9+PIN1),
|
||||
P9_2 = (PIN_GROUP9+PIN2),
|
||||
P9_3 = (PIN_GROUP9+PIN3),
|
||||
P9_4 = (PIN_GROUP9+PIN4),
|
||||
P9_5 = (PIN_GROUP9+PIN5),
|
||||
P9_6 = (PIN_GROUP9+PIN6),
|
||||
|
||||
/* Group Port A */
|
||||
PA_0 = (PIN_GROUPA+PIN0),
|
||||
/* PA_1 to PA_3 are Normal & High-Drive Pins */
|
||||
PA_1 = (PIN_GROUPA+PIN1),
|
||||
PA_2 = (PIN_GROUPA+PIN2),
|
||||
PA_3 = (PIN_GROUPA+PIN3),
|
||||
PA_4 = (PIN_GROUPA+PIN4),
|
||||
|
||||
/* Group Port B */
|
||||
PB_0 = (PIN_GROUPB+PIN0),
|
||||
PB_1 = (PIN_GROUPB+PIN1),
|
||||
PB_2 = (PIN_GROUPB+PIN2),
|
||||
PB_3 = (PIN_GROUPB+PIN3),
|
||||
PB_4 = (PIN_GROUPB+PIN4),
|
||||
PB_5 = (PIN_GROUPB+PIN5),
|
||||
PB_6 = (PIN_GROUPB+PIN6),
|
||||
|
||||
/* Group Port C */
|
||||
PC_0 = (PIN_GROUPC+PIN0),
|
||||
PC_1 = (PIN_GROUPC+PIN1),
|
||||
PC_2 = (PIN_GROUPC+PIN2),
|
||||
PC_3 = (PIN_GROUPC+PIN3),
|
||||
PC_4 = (PIN_GROUPC+PIN4),
|
||||
PC_5 = (PIN_GROUPC+PIN5),
|
||||
PC_6 = (PIN_GROUPC+PIN6),
|
||||
PC_7 = (PIN_GROUPC+PIN7),
|
||||
PC_8 = (PIN_GROUPC+PIN8),
|
||||
PC_9 = (PIN_GROUPC+PIN9),
|
||||
PC_10 = (PIN_GROUPC+PIN10),
|
||||
PC_11 = (PIN_GROUPC+PIN11),
|
||||
PC_12 = (PIN_GROUPC+PIN12),
|
||||
PC_13 = (PIN_GROUPC+PIN13),
|
||||
PC_14 = (PIN_GROUPC+PIN14),
|
||||
|
||||
/* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */
|
||||
PD_0 = (PIN_GROUPD+PIN0),
|
||||
PD_1 = (PIN_GROUPD+PIN1),
|
||||
PD_2 = (PIN_GROUPD+PIN2),
|
||||
PD_3 = (PIN_GROUPD+PIN3),
|
||||
PD_4 = (PIN_GROUPD+PIN4),
|
||||
PD_5 = (PIN_GROUPD+PIN5),
|
||||
PD_6 = (PIN_GROUPD+PIN6),
|
||||
PD_7 = (PIN_GROUPD+PIN7),
|
||||
PD_8 = (PIN_GROUPD+PIN8),
|
||||
PD_9 = (PIN_GROUPD+PIN9),
|
||||
PD_10 = (PIN_GROUPD+PIN10),
|
||||
PD_11 = (PIN_GROUPD+PIN11),
|
||||
PD_12 = (PIN_GROUPD+PIN12),
|
||||
PD_13 = (PIN_GROUPD+PIN13),
|
||||
PD_14 = (PIN_GROUPD+PIN14),
|
||||
PD_15 = (PIN_GROUPD+PIN15),
|
||||
PD_16 = (PIN_GROUPD+PIN16),
|
||||
|
||||
/* Group Port E */
|
||||
PE_0 = (PIN_GROUPE+PIN0),
|
||||
PE_1 = (PIN_GROUPE+PIN1),
|
||||
PE_2 = (PIN_GROUPE+PIN2),
|
||||
PE_3 = (PIN_GROUPE+PIN3),
|
||||
PE_4 = (PIN_GROUPE+PIN4),
|
||||
PE_5 = (PIN_GROUPE+PIN5),
|
||||
PE_6 = (PIN_GROUPE+PIN6),
|
||||
PE_7 = (PIN_GROUPE+PIN7),
|
||||
PE_8 = (PIN_GROUPE+PIN8),
|
||||
PE_9 = (PIN_GROUPE+PIN9),
|
||||
PE_10 = (PIN_GROUPE+PIN10),
|
||||
PE_11 = (PIN_GROUPE+PIN11),
|
||||
PE_12 = (PIN_GROUPE+PIN12),
|
||||
PE_13 = (PIN_GROUPE+PIN13),
|
||||
PE_14 = (PIN_GROUPE+PIN14),
|
||||
PE_15 = (PIN_GROUPE+PIN15),
|
||||
|
||||
/* Group Port F */
|
||||
PF_0 = (PIN_GROUPF+PIN0),
|
||||
PF_1 = (PIN_GROUPF+PIN1),
|
||||
PF_2 = (PIN_GROUPF+PIN2),
|
||||
PF_3 = (PIN_GROUPF+PIN3),
|
||||
PF_4 = (PIN_GROUPF+PIN4),
|
||||
PF_5 = (PIN_GROUPF+PIN5),
|
||||
PF_6 = (PIN_GROUPF+PIN6),
|
||||
PF_7 = (PIN_GROUPF+PIN7),
|
||||
PF_8 = (PIN_GROUPF+PIN8),
|
||||
PF_9 = (PIN_GROUPF+PIN9),
|
||||
PF_10 = (PIN_GROUPF+PIN10),
|
||||
PF_11 = (PIN_GROUPF+PIN11),
|
||||
|
||||
/* Group Clock 0 to 3 High-Speed pins */
|
||||
CLK0 = (SCU_BASE + 0xC00),
|
||||
CLK1 = (SCU_BASE + 0xC04),
|
||||
CLK2 = (SCU_BASE + 0xC08),
|
||||
CLK3 = (SCU_BASE + 0xC0C)
|
||||
|
||||
} scu_grp_pin_t;
|
||||
|
||||
/*
|
||||
* Pin Configuration to be used for scu_pinmux() parameter scu_conf
|
||||
* For normal-drive pins, high-drive pins, high-speed pins
|
||||
*/
|
||||
/*
|
||||
* Function BIT0 to 2.
|
||||
* Common to normal-drive pins, high-drive pins, high-speed pins.
|
||||
*/
|
||||
#define SCU_CONF_FUNCTION0 (0x0)
|
||||
#define SCU_CONF_FUNCTION1 (0x1)
|
||||
#define SCU_CONF_FUNCTION2 (0x2)
|
||||
#define SCU_CONF_FUNCTION3 (0x3)
|
||||
#define SCU_CONF_FUNCTION4 (0x4)
|
||||
#define SCU_CONF_FUNCTION5 (0x5)
|
||||
#define SCU_CONF_FUNCTION6 (0x6)
|
||||
#define SCU_CONF_FUNCTION7 (0x7)
|
||||
|
||||
/*
|
||||
* Enable pull-down resistor at pad
|
||||
* By default=0 Disable pull-down.
|
||||
* Available to normal-drive pins, high-drive pins, high-speed pins
|
||||
*/
|
||||
#define SCU_CONF_EPD_EN_PULLDOWN (BIT3)
|
||||
|
||||
/*
|
||||
* Disable pull-up resistor at pad.
|
||||
* By default=0 the pull-up resistor is enabled at reset.
|
||||
* Available to normal-drive pins, high-drive pins, high-speed pins
|
||||
*/
|
||||
#define SCU_CONF_EPUN_DIS_PULLUP (BIT4)
|
||||
|
||||
/*
|
||||
* Select Slew Rate.
|
||||
* By Default=0 Slow.
|
||||
* Available to normal-drive pins and high-speed pins, reserved for high-drive pins.
|
||||
*/
|
||||
#define SCU_CONF_EHS_FAST (BIT5)
|
||||
|
||||
/*
|
||||
* Input buffer enable.
|
||||
* By Default=0 Disable Input Buffer.
|
||||
* The input buffer is disabled by default at reset and must be enabled.
|
||||
* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins).
|
||||
* Available to normal-drive pins, high-drive pins, high-speed pins.
|
||||
*/
|
||||
#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6)
|
||||
|
||||
/*
|
||||
* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.
|
||||
* Available to normal-drive pins, high-drive pins, high-speed pins.
|
||||
*/
|
||||
#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)
|
||||
|
||||
/*
|
||||
* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9).
|
||||
* Available to high-drive pins, reserved for others.
|
||||
*/
|
||||
#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100)
|
||||
#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200)
|
||||
#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300)
|
||||
|
||||
/* BIT10 to 31 are Reserved */
|
||||
|
||||
/* Configuration for different I/O pins types */
|
||||
#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
|
||||
#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
|
||||
#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
|
||||
#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
|
||||
#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER)
|
||||
#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)
|
||||
#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER)
|
||||
#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
|
||||
#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)
|
||||
#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
|
||||
|
||||
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_SDIO_H
|
||||
#define LPC43XX_SDIO_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- SDIO registers ----------------------------------------------------- */
|
||||
|
||||
/* Control Register */
|
||||
#define SDIO_CTRL MMIO32(SDIO_BASE + 0x000)
|
||||
|
||||
/* Power Enable Register */
|
||||
#define SDIO_PWREN MMIO32(SDIO_BASE + 0x004)
|
||||
|
||||
/* Clock Divider Register */
|
||||
#define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008)
|
||||
|
||||
/* SD Clock Source Register */
|
||||
#define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C)
|
||||
|
||||
/* Clock Enable Register */
|
||||
#define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010)
|
||||
|
||||
/* Time-out Register */
|
||||
#define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014)
|
||||
|
||||
/* Card Type Register */
|
||||
#define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018)
|
||||
|
||||
/* Block Size Register */
|
||||
#define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C)
|
||||
|
||||
/* Byte Count Register */
|
||||
#define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020)
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024)
|
||||
|
||||
/* Command Argument Register */
|
||||
#define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028)
|
||||
|
||||
/* Command Register */
|
||||
#define SDIO_CMD MMIO32(SDIO_BASE + 0x02C)
|
||||
|
||||
/* Response Register 0 */
|
||||
#define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030)
|
||||
|
||||
/* Response Register 1 */
|
||||
#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034)
|
||||
|
||||
/* Response Register 2 */
|
||||
#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038)
|
||||
|
||||
/* Response Register 3 */
|
||||
#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C)
|
||||
|
||||
/* Masked Interrupt Status Register */
|
||||
#define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040)
|
||||
|
||||
/* Raw Interrupt Status Register */
|
||||
#define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044)
|
||||
|
||||
/* Status Register */
|
||||
#define SDIO_STATUS MMIO32(SDIO_BASE + 0x048)
|
||||
|
||||
/* FIFO Threshold Watermark Register */
|
||||
#define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C)
|
||||
|
||||
/* Card Detect Register */
|
||||
#define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050)
|
||||
|
||||
/* Write Protect Register */
|
||||
#define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054)
|
||||
|
||||
/* Transferred CIU Card Byte Count Register */
|
||||
#define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C)
|
||||
|
||||
/* Transferred Host to BIU-FIFO Byte Count Register */
|
||||
#define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060)
|
||||
|
||||
/* Debounce Count Register */
|
||||
#define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064)
|
||||
|
||||
/* UHS-1 Register */
|
||||
#define SDIO_UHS_REG MMIO32(SDIO_BASE + 0x074)
|
||||
|
||||
/* Hardware Reset */
|
||||
#define SDIO_RST_N MMIO32(SDIO_BASE + 0x078)
|
||||
|
||||
/* Bus Mode Register */
|
||||
#define SDIO_BMOD MMIO32(SDIO_BASE + 0x080)
|
||||
|
||||
/* Poll Demand Register */
|
||||
#define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084)
|
||||
|
||||
/* Descriptor List Base Address Register */
|
||||
#define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088)
|
||||
|
||||
/* Internal DMAC Status Register */
|
||||
#define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C)
|
||||
|
||||
/* Internal DMAC Interrupt Enable Register */
|
||||
#define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090)
|
||||
|
||||
/* Current Host Descriptor Address Register */
|
||||
#define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094)
|
||||
|
||||
/* Current Buffer Descriptor Address Register */
|
||||
#define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098)
|
||||
|
||||
/* Data FIFO read/write */
|
||||
#define SDIO_DATA MMIO32(SDIO_BASE + 0x100)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,298 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright (C) 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_SGPIO_H
|
||||
#define LPC43XX_SGPIO_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- SGPIO registers ----------------------------------------------------- */
|
||||
|
||||
/* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */
|
||||
#define SGPIO_OUT_MUX_CFG(pin) MMIO32(SGPIO_PORT_BASE + (pin * 0x04))
|
||||
#define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00)
|
||||
#define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04)
|
||||
#define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08)
|
||||
#define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C)
|
||||
#define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10)
|
||||
#define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14)
|
||||
#define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18)
|
||||
#define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C)
|
||||
#define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20)
|
||||
#define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24)
|
||||
#define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28)
|
||||
#define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C)
|
||||
#define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30)
|
||||
#define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34)
|
||||
#define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38)
|
||||
#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C)
|
||||
|
||||
/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */
|
||||
#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + (slice * 0x04))
|
||||
#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40)
|
||||
#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44)
|
||||
#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48)
|
||||
#define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C)
|
||||
#define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50)
|
||||
#define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54)
|
||||
#define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58)
|
||||
#define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C)
|
||||
#define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60)
|
||||
#define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64)
|
||||
#define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68)
|
||||
#define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C)
|
||||
#define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70)
|
||||
#define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74)
|
||||
#define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78)
|
||||
#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C)
|
||||
|
||||
/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */
|
||||
#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + (slice * 0x04))
|
||||
#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80)
|
||||
#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84)
|
||||
#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88)
|
||||
#define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C)
|
||||
#define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90)
|
||||
#define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94)
|
||||
#define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98)
|
||||
#define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C)
|
||||
#define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0)
|
||||
#define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4)
|
||||
#define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8)
|
||||
#define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC)
|
||||
#define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0)
|
||||
#define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4)
|
||||
#define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8)
|
||||
#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC)
|
||||
|
||||
/* Slice data registers (REG0 to 15) */
|
||||
#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + (slice * 0x04))
|
||||
#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0)
|
||||
#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4)
|
||||
#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8)
|
||||
#define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC)
|
||||
#define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0)
|
||||
#define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4)
|
||||
#define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8)
|
||||
#define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC)
|
||||
#define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0)
|
||||
#define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4)
|
||||
#define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8)
|
||||
#define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC)
|
||||
#define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0)
|
||||
#define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4)
|
||||
#define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8)
|
||||
#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC)
|
||||
|
||||
/* Slice data shadow registers (REG_SS0 to 15) */
|
||||
#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + (slice * 0x04))
|
||||
#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100)
|
||||
#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104)
|
||||
#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108)
|
||||
#define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C)
|
||||
#define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110)
|
||||
#define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114)
|
||||
#define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118)
|
||||
#define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C)
|
||||
#define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120)
|
||||
#define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124)
|
||||
#define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128)
|
||||
#define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C)
|
||||
#define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130)
|
||||
#define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134)
|
||||
#define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138)
|
||||
#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C)
|
||||
|
||||
/* Reload registers (PRESET0 to 15) */
|
||||
#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + (slice * 0x04))
|
||||
#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140)
|
||||
#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144)
|
||||
#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148)
|
||||
#define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C)
|
||||
#define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150)
|
||||
#define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154)
|
||||
#define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158)
|
||||
#define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C)
|
||||
#define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160)
|
||||
#define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164)
|
||||
#define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168)
|
||||
#define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C)
|
||||
#define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170)
|
||||
#define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174)
|
||||
#define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178)
|
||||
#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C)
|
||||
|
||||
/* Down counter registers (COUNT0 to 15) */
|
||||
#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + (slice * 0x04))
|
||||
#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180)
|
||||
#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184)
|
||||
#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188)
|
||||
#define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C)
|
||||
#define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190)
|
||||
#define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194)
|
||||
#define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198)
|
||||
#define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C)
|
||||
#define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0)
|
||||
#define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4)
|
||||
#define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8)
|
||||
#define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC)
|
||||
#define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0)
|
||||
#define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4)
|
||||
#define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8)
|
||||
#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC)
|
||||
|
||||
/* Position registers (POS0 to 15) */
|
||||
#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + (slice * 0x04))
|
||||
#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0)
|
||||
#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4)
|
||||
#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8)
|
||||
#define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC)
|
||||
#define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0)
|
||||
#define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4)
|
||||
#define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8)
|
||||
#define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC)
|
||||
#define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0)
|
||||
#define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4)
|
||||
#define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8)
|
||||
#define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC)
|
||||
#define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0)
|
||||
#define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4)
|
||||
#define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8)
|
||||
#define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC)
|
||||
|
||||
/* Slice name to slice index mapping */
|
||||
#define SGPIO_SLICE_A 0
|
||||
#define SGPIO_SLICE_B 1
|
||||
#define SGPIO_SLICE_C 2
|
||||
#define SGPIO_SLICE_D 3
|
||||
#define SGPIO_SLICE_E 4
|
||||
#define SGPIO_SLICE_F 5
|
||||
#define SGPIO_SLICE_G 6
|
||||
#define SGPIO_SLICE_H 7
|
||||
#define SGPIO_SLICE_I 8
|
||||
#define SGPIO_SLICE_J 9
|
||||
#define SGPIO_SLICE_K 10
|
||||
#define SGPIO_SLICE_L 11
|
||||
#define SGPIO_SLICE_M 12
|
||||
#define SGPIO_SLICE_N 13
|
||||
#define SGPIO_SLICE_O 14
|
||||
#define SGPIO_SLICE_P 15
|
||||
|
||||
/* Mask for pattern match function of slice A */
|
||||
#define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200)
|
||||
|
||||
/* Mask for pattern match function of slice H */
|
||||
#define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204)
|
||||
|
||||
/* Mask for pattern match function of slice I */
|
||||
#define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208)
|
||||
|
||||
/* Mask for pattern match function of slice P */
|
||||
#define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C)
|
||||
|
||||
/* GPIO input status register */
|
||||
#define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210)
|
||||
|
||||
/* GPIO output control register */
|
||||
#define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214)
|
||||
|
||||
/* GPIO OE control register */
|
||||
#define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218)
|
||||
|
||||
/* Enables the slice COUNT counter */
|
||||
#define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C)
|
||||
|
||||
/* Disables the slice COUNT counter */
|
||||
#define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220)
|
||||
|
||||
/* Shift clock interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00)
|
||||
|
||||
/* Shift clock interrupt set mask */
|
||||
#define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04)
|
||||
|
||||
/* Shift clock interrupt enable */
|
||||
#define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08)
|
||||
|
||||
/* Shift clock interrupt status */
|
||||
#define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C)
|
||||
|
||||
/* Shift clock interrupt clear status */
|
||||
#define SGPIO_CLR_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF10)
|
||||
|
||||
/* Shift clock interrupt set status */
|
||||
#define SGPIO_SET_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF14)
|
||||
|
||||
/* Exchange clock interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20)
|
||||
|
||||
/* Exchange clock interrupt set mask */
|
||||
#define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24)
|
||||
|
||||
/* Exchange clock interrupt enable */
|
||||
#define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28)
|
||||
|
||||
/* Exchange clock interrupt status */
|
||||
#define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C)
|
||||
|
||||
/* Exchange clock interrupt clear status */
|
||||
#define SGPIO_CLR_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF30)
|
||||
|
||||
/* Exchange clock interrupt set status */
|
||||
#define SGPIO_SET_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF34)
|
||||
|
||||
/* Pattern match interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40)
|
||||
|
||||
/* Pattern match interrupt set mask */
|
||||
#define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44)
|
||||
|
||||
/* Pattern match interrupt enable */
|
||||
#define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48)
|
||||
|
||||
/* Pattern match interrupt status */
|
||||
#define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C)
|
||||
|
||||
/* Pattern match interrupt clear status */
|
||||
#define SGPIO_CLR_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF50)
|
||||
|
||||
/* Pattern match interrupt set status */
|
||||
#define SGPIO_SET_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF54)
|
||||
|
||||
/* Input interrupt clear mask */
|
||||
#define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60)
|
||||
|
||||
/* Input bit match interrupt set mask */
|
||||
#define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64)
|
||||
|
||||
/* Input bit match interrupt enable */
|
||||
#define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68)
|
||||
|
||||
/* Input bit match interrupt status */
|
||||
#define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C)
|
||||
|
||||
/* Input bit match interrupt clear status */
|
||||
#define SGPIO_CLR_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF70)
|
||||
|
||||
/* Input bit match interrupt set status */
|
||||
#define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_SSP_H
|
||||
#define LPC43XX_SSP_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* SSP port base addresses (for convenience) */
|
||||
#define SSP0 SSP0_BASE
|
||||
#define SSP1 SSP1_BASE
|
||||
|
||||
|
||||
/* --- SSP registers ------------------------------------------------------- */
|
||||
|
||||
/* Control Register 0 */
|
||||
#define SSP_CR0(port) MMIO32(port + 0x000)
|
||||
#define SSP0_CR0 SSP_CR0(SSP0)
|
||||
#define SSP1_CR0 SSP_CR0(SSP1)
|
||||
|
||||
/* Control Register 1 */
|
||||
#define SSP_CR1(port) MMIO32(port + 0x004)
|
||||
#define SSP0_CR1 SSP_CR1(SSP0)
|
||||
#define SSP1_CR1 SSP_CR1(SSP1)
|
||||
|
||||
/* Data Register */
|
||||
#define SSP_DR(port) MMIO32(port + 0x008)
|
||||
#define SSP0_DR SSP_DR(SSP0)
|
||||
#define SSP1_DR SSP_DR(SSP1)
|
||||
|
||||
/* Status Register */
|
||||
#define SSP_SR(port) MMIO32(port + 0x00C)
|
||||
#define SSP0_SR SSP_SR(SSP0)
|
||||
#define SSP1_SR SSP_SR(SSP1)
|
||||
|
||||
#define SSP_SR_TFE BIT0
|
||||
#define SSP_SR_TNF BIT1
|
||||
#define SSP_SR_RNE BIT2
|
||||
#define SSP_SR_RFF BIT3
|
||||
#define SSP_SR_BSY BIT4
|
||||
|
||||
/* Clock Prescale Register */
|
||||
#define SSP_CPSR(port) MMIO32(port + 0x010)
|
||||
#define SSP0_CPSR SSP_CPSR(SSP0)
|
||||
#define SSP1_CPSR SSP_CPSR(SSP1)
|
||||
|
||||
/* Interrupt Mask Set and Clear Register */
|
||||
#define SSP_IMSC(port) MMIO32(port + 0x014)
|
||||
#define SSP0_IMSC SSP_IMSC(SSP0)
|
||||
#define SSP1_IMSC SSP_IMSC(SSP1)
|
||||
|
||||
/* Raw Interrupt Status Register */
|
||||
#define SSP_RIS(port) MMIO32(port + 0x018)
|
||||
#define SSP0_RIS SSP_RIS(SSP0)
|
||||
#define SSP1_RIS SSP_RIS(SSP1)
|
||||
|
||||
/* Masked Interrupt Status Register */
|
||||
#define SSP_MIS(port) MMIO32(port + 0x01C)
|
||||
#define SSP0_MIS SSP_MIS(SSP0)
|
||||
#define SSP1_MIS SSP_MIS(SSP1)
|
||||
|
||||
/* SSPICR Interrupt Clear Register */
|
||||
#define SSP_ICR(port) MMIO32(port + 0x020)
|
||||
#define SSP0_ICR SSP_ICR(SSP0)
|
||||
#define SSP1_ICR SSP_ICR(SSP1)
|
||||
|
||||
/* SSP1 DMA control register */
|
||||
#define SSP_DMACR(port) MMIO32(port + 0x024)
|
||||
#define SSP0_DMACR SSP_DMACR(SSP0)
|
||||
#define SSP1_DMACR SSP_DMACR(SSP1)
|
||||
|
||||
typedef enum {
|
||||
SSP0_NUM = 0x0,
|
||||
SSP1_NUM = 0x1
|
||||
} ssp_num_t;
|
||||
|
||||
/*
|
||||
* SSP Control Register 0
|
||||
*/
|
||||
/* SSP Data Size Bits 0 to 3 */
|
||||
typedef enum {
|
||||
SSP_DATA_4BITS = 0x3,
|
||||
SSP_DATA_5BITS = 0x4,
|
||||
SSP_DATA_6BITS = 0x5,
|
||||
SSP_DATA_7BITS = 0x6,
|
||||
SSP_DATA_8BITS = 0x7,
|
||||
SSP_DATA_9BITS = 0x8,
|
||||
SSP_DATA_10BITS = 0x9,
|
||||
SSP_DATA_11BITS = 0xA,
|
||||
SSP_DATA_12BITS = 0xB,
|
||||
SSP_DATA_13BITS = 0xC,
|
||||
SSP_DATA_14BITS = 0xD,
|
||||
SSP_DATA_15BITS = 0xE,
|
||||
SSP_DATA_16BITS = 0xF
|
||||
} ssp_datasize_t;
|
||||
|
||||
/* SSP Frame Format/Type Bits 4 & 5 */
|
||||
typedef enum {
|
||||
SSP_FRAME_SPI = 0x00,
|
||||
SSP_FRAME_TI = BIT4,
|
||||
SSP_FRAM_MICROWIRE = BIT5
|
||||
} ssp_frame_format_t;
|
||||
|
||||
/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */
|
||||
typedef enum {
|
||||
SSP_CPOL_0_CPHA_0 = 0x0,
|
||||
SSP_CPOL_1_CPHA_0 = BIT6,
|
||||
SSP_CPOL_0_CPHA_1 = BIT7,
|
||||
SSP_CPOL_1_CPHA_1 = (BIT6|BIT7)
|
||||
} ssp_cpol_cpha_t;
|
||||
|
||||
/*
|
||||
* SSP Control Register 1
|
||||
*/
|
||||
/* SSP Mode Bit0 */
|
||||
typedef enum {
|
||||
SSP_MODE_NORMAL = 0x0,
|
||||
SSP_MODE_LOOPBACK = BIT0
|
||||
} ssp_mode_t;
|
||||
|
||||
/* SSP Enable Bit1 */
|
||||
#define SSP_ENABLE BIT1
|
||||
|
||||
/* SSP Master/Slave Mode Bit2 */
|
||||
typedef enum {
|
||||
SSP_MASTER = 0x0,
|
||||
SSP_SLAVE = BIT2
|
||||
} ssp_master_slave_t;
|
||||
|
||||
/*
|
||||
* SSP Slave Output Disable Bit3
|
||||
* Slave Output Disable. This bit is relevant only in slave mode
|
||||
* (MS = 1). If it is 1, this blocks this SSP controller from driving the
|
||||
* transmit data line (MISO).
|
||||
*/
|
||||
typedef enum {
|
||||
SSP_SLAVE_OUT_ENABLE = 0x0,
|
||||
SSP_SLAVE_OUT_DISABLE = BIT3
|
||||
} ssp_slave_option_t; /* This option is relevant only in slave mode */
|
||||
|
||||
void ssp_disable(ssp_num_t ssp_num);
|
||||
|
||||
/*
|
||||
* SSP Init
|
||||
* clk_prescale shall be in range 2 to 254 (even number only).
|
||||
* Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, SCR=serial_clock_rate
|
||||
*/
|
||||
void ssp_init(ssp_num_t ssp_num,
|
||||
ssp_datasize_t data_size,
|
||||
ssp_frame_format_t frame_format,
|
||||
ssp_cpol_cpha_t cpol_cpha_format,
|
||||
u8 serial_clock_rate,
|
||||
u8 clk_prescale,
|
||||
ssp_mode_t mode,
|
||||
ssp_master_slave_t master_slave,
|
||||
ssp_slave_option_t slave_option);
|
||||
|
||||
u16 ssp_read(ssp_num_t ssp_num);
|
||||
|
||||
void ssp_write(ssp_num_t ssp_num, u16 data);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_SYSTICK_H
|
||||
#define LIBOPENCM3_SYSTICK_H
|
||||
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
#include <libopencm3/cm3/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- SYSTICK registers --------------------------------------------------- */
|
||||
/* See also libopencm3\cm3\scs.h for details on SysTicks registers */
|
||||
|
||||
/* Control and status register (STK_CTRL) */
|
||||
#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
|
||||
|
||||
/* reload value register (STK_LOAD) */
|
||||
#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
|
||||
|
||||
/* current value register (STK_VAL) */
|
||||
#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
|
||||
|
||||
/* calibration value register (STK_CALIB) */
|
||||
#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
|
||||
|
||||
/* --- STK_CTRL values ----------------------------------------------------- */
|
||||
/* Bits [31:17] Reserved, must be kept cleared. */
|
||||
/* COUNTFLAG: */
|
||||
#define STK_CTRL_COUNTFLAG (1 << 16)
|
||||
/* Bits [15:3] Reserved, must be kept cleared. */
|
||||
/* CLKSOURCE: Clock source selection */
|
||||
#define STK_CTRL_CLKSOURCE (1 << 2)
|
||||
/* TICKINT: SysTick exception request enable */
|
||||
#define STK_CTRL_TICKINT (1 << 1)
|
||||
/* ENABLE: Counter enable */
|
||||
#define STK_CTRL_ENABLE (1 << 0)
|
||||
|
||||
/* --- STK_LOAD values ----------------------------------------------------- */
|
||||
/* Bits [31:24] Reserved, must be kept cleared. */
|
||||
/* RELOAD[23:0]: RELOAD value */
|
||||
|
||||
/* --- STK_VAL values ------------------------------------------------------ */
|
||||
/* Bits [31:24] Reserved, must be kept cleared. */
|
||||
/* CURRENT[23:0]: Current counter value */
|
||||
|
||||
/* --- STK_CALIB values ---------------------------------------------------- */
|
||||
/* NOREF: NOREF flag */
|
||||
#define STK_CALIB_NOREF (1 << 31)
|
||||
/* SKEW: SKEW flag */
|
||||
#define STK_CALIB_SKEW (1 << 30)
|
||||
/* Bits [29:24] Reserved, must be kept cleared. */
|
||||
/* TENMS[23:0]: Calibration value */
|
||||
|
||||
/* --- Function Prototypes ------------------------------------------------- */
|
||||
|
||||
void systick_set_reload(u32 value);
|
||||
u32 systick_get_value(void);
|
||||
void systick_set_clocksource(u8 clocksource);
|
||||
void systick_interrupt_enable(void);
|
||||
void systick_interrupt_disable(void);
|
||||
void systick_counter_enable(void);
|
||||
void systick_counter_disable(void);
|
||||
u8 systick_get_countflag(void);
|
||||
|
||||
u32 systick_get_calib(void);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_TIMER_H
|
||||
#define LPC43XX_TIMER_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* Timer base addresses */
|
||||
#define TIMER0 TIMER0_BASE
|
||||
#define TIMER1 TIMER1_BASE
|
||||
#define TIMER2 TIMER2_BASE
|
||||
#define TIMER3 TIMER3_BASE
|
||||
|
||||
|
||||
/* --- Timer registers ----------------------------------------------------- */
|
||||
|
||||
/* Interrupt Register */
|
||||
#define TIMER_IR(timer) MMIO32(timer + 0x000)
|
||||
#define TIMER0_IR TIMER_IR(TIMER0)
|
||||
#define TIMER1_IR TIMER_IR(TIMER1)
|
||||
#define TIMER2_IR TIMER_IR(TIMER2)
|
||||
#define TIMER3_IR TIMER_IR(TIMER3)
|
||||
|
||||
/* Timer Control Register */
|
||||
#define TIMER_TCR(timer) MMIO32(timer + 0x004)
|
||||
#define TIMER0_TCR TIMER_TCR(TIMER0)
|
||||
#define TIMER1_TCR TIMER_TCR(TIMER1)
|
||||
#define TIMER2_TCR TIMER_TCR(TIMER2)
|
||||
#define TIMER3_TCR TIMER_TCR(TIMER3)
|
||||
|
||||
/* Timer Counter */
|
||||
#define TIMER_TC(timer) MMIO32(timer + 0x008)
|
||||
#define TIMER0_TC TIMER_TC(TIMER0)
|
||||
#define TIMER1_TC TIMER_TC(TIMER1)
|
||||
#define TIMER2_TC TIMER_TC(TIMER2)
|
||||
#define TIMER3_TC TIMER_TC(TIMER3)
|
||||
|
||||
/* Prescale Register */
|
||||
#define TIMER_PR(timer) MMIO32(timer + 0x00C)
|
||||
#define TIMER0_PR TIMER_PR(TIMER0)
|
||||
#define TIMER1_PR TIMER_PR(TIMER1)
|
||||
#define TIMER2_PR TIMER_PR(TIMER2)
|
||||
#define TIMER3_PR TIMER_PR(TIMER3)
|
||||
|
||||
/* Prescale Counter */
|
||||
#define TIMER_PC(timer) MMIO32(timer + 0x010)
|
||||
#define TIMER0_PC TIMER_PC(TIMER0)
|
||||
#define TIMER1_PC TIMER_PC(TIMER1)
|
||||
#define TIMER2_PC TIMER_PC(TIMER2)
|
||||
#define TIMER3_PC TIMER_PC(TIMER3)
|
||||
|
||||
/* Match Control Register */
|
||||
#define TIMER_MCR(timer) MMIO32(timer + 0x014)
|
||||
#define TIMER0_MCR TIMER_MCR(TIMER0)
|
||||
#define TIMER1_MCR TIMER_MCR(TIMER1)
|
||||
#define TIMER2_MCR TIMER_MCR(TIMER2)
|
||||
#define TIMER3_MCR TIMER_MCR(TIMER3)
|
||||
|
||||
/* Match Register 0 */
|
||||
#define TIMER_MR0(timer) MMIO32(timer + 0x018)
|
||||
#define TIMER0_MR0 TIMER_MR0(TIMER0)
|
||||
#define TIMER1_MR0 TIMER_MR0(TIMER1)
|
||||
#define TIMER2_MR0 TIMER_MR0(TIMER2)
|
||||
#define TIMER3_MR0 TIMER_MR0(TIMER3)
|
||||
|
||||
/* Match Register 1 */
|
||||
#define TIMER_MR1(timer) MMIO32(timer + 0x01C)
|
||||
#define TIMER0_MR1 TIMER_MR1(TIMER0)
|
||||
#define TIMER1_MR1 TIMER_MR1(TIMER1)
|
||||
#define TIMER2_MR1 TIMER_MR1(TIMER2)
|
||||
#define TIMER3_MR1 TIMER_MR1(TIMER3)
|
||||
|
||||
/* Match Register 2 */
|
||||
#define TIMER_MR2(timer) MMIO32(timer + 0x020)
|
||||
#define TIMER0_MR2 TIMER_MR2(TIMER0)
|
||||
#define TIMER1_MR2 TIMER_MR2(TIMER1)
|
||||
#define TIMER2_MR2 TIMER_MR2(TIMER2)
|
||||
#define TIMER3_MR2 TIMER_MR2(TIMER3)
|
||||
|
||||
/* Match Register 3 */
|
||||
#define TIMER_MR3(timer) MMIO32(timer + 0x024)
|
||||
#define TIMER0_MR3 TIMER_MR3(TIMER0)
|
||||
#define TIMER1_MR3 TIMER_MR3(TIMER1)
|
||||
#define TIMER2_MR3 TIMER_MR3(TIMER2)
|
||||
#define TIMER3_MR3 TIMER_MR3(TIMER3)
|
||||
|
||||
/* Capture Control Register */
|
||||
#define TIMER_CCR(timer) MMIO32(timer + 0x028)
|
||||
#define TIMER0_CCR TIMER_CCR(TIMER0)
|
||||
#define TIMER1_CCR TIMER_CCR(TIMER1)
|
||||
#define TIMER2_CCR TIMER_CCR(TIMER2)
|
||||
#define TIMER3_CCR TIMER_CCR(TIMER3)
|
||||
|
||||
/* Capture Register 0 */
|
||||
#define TIMER_CR0(timer) MMIO32(timer + 0x02C)
|
||||
#define TIMER0_CR0 TIMER_CR0(TIMER0)
|
||||
#define TIMER1_CR0 TIMER_CR0(TIMER1)
|
||||
#define TIMER2_CR0 TIMER_CR0(TIMER2)
|
||||
#define TIMER3_CR0 TIMER_CR0(TIMER3)
|
||||
|
||||
/* Capture Register 1 */
|
||||
#define TIMER_CR1(timer) MMIO32(timer + 0x030)
|
||||
#define TIMER0_CR1 TIMER_CR1(TIMER0)
|
||||
#define TIMER1_CR1 TIMER_CR1(TIMER1)
|
||||
#define TIMER2_CR1 TIMER_CR1(TIMER2)
|
||||
#define TIMER3_CR1 TIMER_CR1(TIMER3)
|
||||
|
||||
/* Capture Register 2 */
|
||||
#define TIMER_CR2(timer) MMIO32(timer + 0x034)
|
||||
#define TIMER0_CR2 TIMER_CR2(TIMER0)
|
||||
#define TIMER1_CR2 TIMER_CR2(TIMER1)
|
||||
#define TIMER2_CR2 TIMER_CR2(TIMER2)
|
||||
#define TIMER3_CR2 TIMER_CR2(TIMER3)
|
||||
|
||||
/* Capture Register 3 */
|
||||
#define TIMER_CR3(timer) MMIO32(timer + 0x038)
|
||||
#define TIMER0_CR3 TIMER_CR3(TIMER0)
|
||||
#define TIMER1_CR3 TIMER_CR3(TIMER1)
|
||||
#define TIMER2_CR3 TIMER_CR3(TIMER2)
|
||||
#define TIMER3_CR3 TIMER_CR3(TIMER3)
|
||||
|
||||
/* External Match Register */
|
||||
#define TIMER_EMR(timer) MMIO32(timer + 0x03C)
|
||||
#define TIMER0_EMR TIMER_EMR(TIMER0)
|
||||
#define TIMER1_EMR TIMER_EMR(TIMER1)
|
||||
#define TIMER2_EMR TIMER_EMR(TIMER2)
|
||||
#define TIMER3_EMR TIMER_EMR(TIMER3)
|
||||
|
||||
/* Count Control Register */
|
||||
#define TIMER_CTCR(timer) MMIO32(timer + 0x070)
|
||||
#define TIMER0_CTCR TIMER_CTCR(TIMER0)
|
||||
#define TIMER1_CTCR TIMER_CTCR(TIMER1)
|
||||
#define TIMER2_CTCR TIMER_CTCR(TIMER2)
|
||||
#define TIMER3_CTCR TIMER_CTCR(TIMER3)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_USB_H
|
||||
#define LPC43XX_USB_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- USB0 registers ------------------------------------------------------ */
|
||||
|
||||
/* Device/host capability registers */
|
||||
|
||||
/* Capability register length */
|
||||
#define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100)
|
||||
|
||||
/* Host controller structural parameters */
|
||||
#define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104)
|
||||
|
||||
/* Host controller capability parameters */
|
||||
#define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108)
|
||||
|
||||
/* Device interface version number */
|
||||
#define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120)
|
||||
|
||||
/* Device controller capability parameters */
|
||||
#define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124)
|
||||
|
||||
|
||||
/* Device/host operational registers */
|
||||
|
||||
/* USB command (device mode) */
|
||||
#define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140)
|
||||
|
||||
/* USB command (host mode) */
|
||||
#define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140)
|
||||
|
||||
/* USB status (device mode) */
|
||||
#define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144)
|
||||
|
||||
/* USB status (host mode) */
|
||||
#define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144)
|
||||
|
||||
/* USB interrupt enable (device mode) */
|
||||
#define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148)
|
||||
|
||||
/* USB interrupt enable (host mode) */
|
||||
#define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148)
|
||||
|
||||
/* USB frame index (device mode) */
|
||||
#define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C)
|
||||
|
||||
/* USB frame index (host mode) */
|
||||
#define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C)
|
||||
|
||||
/* USB device address (device mode) */
|
||||
#define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154)
|
||||
|
||||
/* Frame list base address (host mode) */
|
||||
#define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154)
|
||||
|
||||
/* Address of endpoint list in memory */
|
||||
#define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158)
|
||||
|
||||
/* Asynchronous list address */
|
||||
#define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158)
|
||||
|
||||
/* Asynchronous buffer status for embedded TT (host mode) */
|
||||
#define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C)
|
||||
|
||||
/* Programmable burst size */
|
||||
#define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160)
|
||||
|
||||
/* Host transmit pre-buffer packet tuning (host mode) */
|
||||
#define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164)
|
||||
|
||||
/* Length of virtual frame */
|
||||
#define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174)
|
||||
|
||||
/* Endpoint NAK (device mode) */
|
||||
#define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178)
|
||||
|
||||
/* Endpoint NAK Enable (device mode) */
|
||||
#define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C)
|
||||
|
||||
/* Port 1 status/control (device mode) */
|
||||
#define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184)
|
||||
|
||||
/* Port 1 status/control (host mode) */
|
||||
#define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184)
|
||||
|
||||
/* OTG status and control */
|
||||
#define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4)
|
||||
|
||||
/* USB device mode (device mode) */
|
||||
#define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8)
|
||||
|
||||
/* USB device mode (host mode) */
|
||||
#define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8)
|
||||
|
||||
|
||||
/* Device endpoint registers */
|
||||
|
||||
/* Endpoint setup status */
|
||||
#define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC)
|
||||
|
||||
/* Endpoint initialization */
|
||||
#define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0)
|
||||
|
||||
/* Endpoint de-initialization */
|
||||
#define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4)
|
||||
|
||||
/* Endpoint status */
|
||||
#define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8)
|
||||
|
||||
/* Endpoint complete */
|
||||
#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC)
|
||||
|
||||
/* Endpoint control 0 */
|
||||
#define USB0_ENDPTCTRL0 MMIO32(USB0_BASE + 0x1C0)
|
||||
|
||||
/* Endpoint control 1 */
|
||||
#define USB0_ENDPTCTRL1 MMIO32(USB0_BASE + 0x1C4)
|
||||
|
||||
/* Endpoint control 2 */
|
||||
#define USB0_ENDPTCTRL2 MMIO32(USB0_BASE + 0x1C8)
|
||||
|
||||
/* Endpoint control 3 */
|
||||
#define USB0_ENDPTCTRL3 MMIO32(USB0_BASE + 0x1CC)
|
||||
|
||||
/* Endpoint control 4 */
|
||||
#define USB0_ENDPTCTRL4 MMIO32(USB0_BASE + 0x1D0)
|
||||
|
||||
/* Endpoint control 5 */
|
||||
#define USB0_ENDPTCTRL5 MMIO32(USB0_BASE + 0x1D4)
|
||||
|
||||
|
||||
/* --- USB1 registers ------------------------------------------------------ */
|
||||
//TODO
|
||||
|
||||
#endif
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_WWDT_H
|
||||
#define LPC43XX_WWDT_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc43xx/memorymap.h>
|
||||
|
||||
/* --- Windowed Watchdog Timer (WWDT) registers ---------------------------- */
|
||||
|
||||
/* Watchdog mode register */
|
||||
#define WWDT_MOD MMIO32(WWDT_BASE + 0x000)
|
||||
|
||||
/* Watchdog timer constant register */
|
||||
#define WWDT_TC MMIO32(WWDT_BASE + 0x004)
|
||||
|
||||
/* Watchdog feed sequence register */
|
||||
#define WWDT_FEED MMIO32(WWDT_BASE + 0x008)
|
||||
|
||||
/* Watchdog timer value register */
|
||||
#define WWDT_TV MMIO32(WWDT_BASE + 0x00C)
|
||||
|
||||
/* Watchdog warning interrupt register */
|
||||
#define WWDT_WARNINT MMIO32(WWDT_BASE + 0x014)
|
||||
|
||||
/* Watchdog timer window register */
|
||||
#define WWDT_WINDOW MMIO32(WWDT_BASE + 0x018)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,61 @@
|
|||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
## Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
## Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
LIBNAME = libopencm3_lpc43xx
|
||||
|
||||
PREFIX ?= arm-none-eabi
|
||||
#PREFIX ?= arm-elf
|
||||
CC = $(PREFIX)-gcc
|
||||
AR = $(PREFIX)-ar
|
||||
CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \
|
||||
-mcpu=cortex-m4 -mthumb -Wstrict-prototypes \
|
||||
-ffunction-sections -fdata-sections -MD \
|
||||
-mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o
|
||||
|
||||
# VPATH += ../usb
|
||||
|
||||
# Be silent per default, but 'make V=1' will show all compiler calls.
|
||||
ifneq ($(V),1)
|
||||
Q := @
|
||||
endif
|
||||
|
||||
all: $(LIBNAME).a
|
||||
|
||||
$(LIBNAME).a: $(OBJS)
|
||||
@printf " AR $(subst $(shell pwd)/,,$(@))\n"
|
||||
$(Q)$(AR) $(ARFLAGS) $@ $^
|
||||
|
||||
%.o: %.c
|
||||
@printf " CC $(subst $(shell pwd)/,,$(@))\n"
|
||||
$(Q)$(CC) $(CFLAGS) -o $@ -c $<
|
||||
|
||||
clean:
|
||||
@printf " CLEAN lib/lpc43xx\n"
|
||||
$(Q)rm -f *.o *.d
|
||||
$(Q)rm -f $(LIBNAME).a
|
||||
|
||||
.PHONY: clean
|
||||
|
||||
-include $(OBJS:.o=.d)
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
|
||||
void gpio_set(u32 gpioport, u32 gpios)
|
||||
{
|
||||
GPIO_SET(gpioport) = gpios;
|
||||
}
|
||||
|
||||
void gpio_clear(u32 gpioport, u32 gpios)
|
||||
{
|
||||
GPIO_CLR(gpioport) = gpios;
|
||||
}
|
||||
|
||||
void gpio_toggle(u32 gpioport, u32 gpios)
|
||||
{
|
||||
GPIO_NOT(gpioport) = gpios;
|
||||
}
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is a very minimal I2C driver just to make sure we can get the
|
||||
* peripheral working.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/i2c.h>
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include <libopencm3/lpc43xx/cgu.h>
|
||||
|
||||
void i2c0_init(void)
|
||||
{
|
||||
/* enable input on SCL and SDA pins */
|
||||
SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
|
||||
|
||||
/* use IRC as clock source for APB1 (including I2C0) */
|
||||
CGU_BASE_APB1_CLK = (CGU_SRC_IRC << CGU_BASE_CLK_SEL_SHIFT);
|
||||
|
||||
/* FIXME assuming we're on IRC at 12 MHz */
|
||||
|
||||
/* 400 kHz I2C */
|
||||
I2C0_SCLH = 15;
|
||||
I2C0_SCLL = 15;
|
||||
|
||||
/* 100 kHz I2C */
|
||||
/*
|
||||
I2C0_SCLH = 60;
|
||||
I2C0_SCLL = 60;
|
||||
*/
|
||||
|
||||
/* clear the control bits */
|
||||
I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC
|
||||
| I2C_CONCLR_STAC | I2C_CONCLR_I2ENC);
|
||||
|
||||
/* enable I2C0 */
|
||||
I2C0_CONSET = I2C_CONSET_I2EN;
|
||||
}
|
||||
|
||||
/* transmit start bit */
|
||||
void i2c0_tx_start(void)
|
||||
{
|
||||
I2C0_CONCLR = I2C_CONCLR_SIC;
|
||||
I2C0_CONSET = I2C_CONSET_STA;
|
||||
while (!(I2C0_CONSET & I2C_CONSET_SI));
|
||||
I2C0_CONCLR = I2C_CONCLR_STAC;
|
||||
}
|
||||
|
||||
/* transmit data byte */
|
||||
void i2c0_tx_byte(u8 byte)
|
||||
{
|
||||
if (I2C0_CONSET & I2C_CONSET_STA)
|
||||
I2C0_CONCLR = I2C_CONCLR_STAC;
|
||||
I2C0_DAT = byte;
|
||||
I2C0_CONCLR = I2C_CONCLR_SIC;
|
||||
while (!(I2C0_CONSET & I2C_CONSET_SI));
|
||||
}
|
||||
|
||||
/* receive data byte */
|
||||
u8 i2c0_rx_byte(void)
|
||||
{
|
||||
if (I2C0_CONSET & I2C_CONSET_STA)
|
||||
I2C0_CONCLR = I2C_CONCLR_STAC;
|
||||
I2C0_CONCLR = I2C_CONCLR_SIC;
|
||||
while (!(I2C0_CONSET & I2C_CONSET_SI));
|
||||
return I2C0_DAT;
|
||||
}
|
||||
|
||||
/* transmit stop bit */
|
||||
void i2c0_stop(void)
|
||||
{
|
||||
if (I2C0_CONSET & I2C_CONSET_STA)
|
||||
I2C0_CONCLR = I2C_CONCLR_STAC;
|
||||
I2C0_CONSET = I2C_CONSET_STO;
|
||||
I2C0_CONCLR = I2C_CONCLR_SIC;
|
||||
}
|
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Generic linker script for LPC43XX targets using libopencm3. */
|
||||
|
||||
/* Memory regions must be defined in the ld script which includes this one. */
|
||||
|
||||
/* Enforce emmition of the vector table. */
|
||||
EXTERN (vector_table)
|
||||
|
||||
/* Define the entry point of the output file. */
|
||||
ENTRY(reset_handler)
|
||||
|
||||
/* Define sections. */
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(rom);
|
||||
|
||||
.text : {
|
||||
. = ALIGN(0x400);
|
||||
_text_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */
|
||||
*(.vectors) /* Vector table */
|
||||
*(.text*) /* Program code */
|
||||
. = ALIGN(4);
|
||||
*(.rodata*) /* Read-only data */
|
||||
. = ALIGN(4);
|
||||
} >rom
|
||||
|
||||
/* exception index - required due to libgcc.a issuing /0 exceptions */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > rom
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
_etext_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */
|
||||
_etext_rom = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */
|
||||
|
||||
. = ORIGIN(ram);
|
||||
|
||||
.data : {
|
||||
_data = .;
|
||||
*(.data*) /* Read-write initialized data */
|
||||
. = ALIGN(4);
|
||||
_edata = .;
|
||||
} >ram AT >rom
|
||||
|
||||
.bss : {
|
||||
*(.bss*) /* Read-write zero initialized data */
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
} >ram
|
||||
|
||||
/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} >ram
|
||||
|
||||
/*
|
||||
* The .eh_frame section appears to be used for C++ exception handling.
|
||||
* You may need to fix this if you're using C++.
|
||||
*/
|
||||
/DISCARD/ : { *(.eh_frame) }
|
||||
|
||||
/*
|
||||
* Another section used by C++ stuff, appears when using newlib with
|
||||
* 64bit (long long) printf support - discard it for now.
|
||||
*/
|
||||
/DISCARD/ : { *(.ARM.exidx) }
|
||||
|
||||
end = .;
|
||||
|
||||
/* Leave room above stack for IAP to run. */
|
||||
__StackTop = ORIGIN(ram) + LENGTH(ram) - 32;
|
||||
PROVIDE(_stack = __StackTop);
|
||||
}
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Generic linker script for LPC43XX targets using libopencm3. */
|
||||
|
||||
/* Memory regions must be defined in the ld script which includes this one. */
|
||||
|
||||
/* Enforce emmition of the vector table. */
|
||||
EXTERN (vector_table)
|
||||
|
||||
/* Define the entry point of the output file. */
|
||||
ENTRY(reset_handler)
|
||||
|
||||
/* Define sections. */
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(rom);
|
||||
|
||||
.text : {
|
||||
. = ALIGN(0x400);
|
||||
_text_ram = (. - ORIGIN(rom)) + ORIGIN(ram); /* Start of Code in RAM */
|
||||
|
||||
*(.vectors) /* Vector table */
|
||||
*(.text*) /* Program code */
|
||||
. = ALIGN(4);
|
||||
*(.rodata*) /* Read-only data */
|
||||
. = ALIGN(4);
|
||||
} >rom
|
||||
|
||||
/* exception index - required due to libgcc.a issuing /0 exceptions */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > rom
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
_etext_ram = (. - ORIGIN(rom)) + ORIGIN(ram);
|
||||
_etext_rom = (. - ORIGIN(rom)) + ORIGIN(rom_flash);
|
||||
|
||||
.data : {
|
||||
_data = .;
|
||||
*(.data*) /* Read-write initialized data */
|
||||
. = ALIGN(4);
|
||||
_edata = .;
|
||||
} >ram_data AT >rom
|
||||
|
||||
.bss : {
|
||||
. = _edata;
|
||||
*(.bss*) /* Read-write zero initialized data */
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
} >ram_data
|
||||
|
||||
/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
|
||||
.ARM.extab : {
|
||||
. = _ebss;
|
||||
*(.ARM.extab*)
|
||||
} >ram_data
|
||||
|
||||
/*
|
||||
* The .eh_frame section appears to be used for C++ exception handling.
|
||||
* You may need to fix this if you're using C++.
|
||||
*/
|
||||
/DISCARD/ : { *(.eh_frame) }
|
||||
|
||||
/*
|
||||
* Another section used by C++ stuff, appears when using newlib with
|
||||
* 64bit (long long) printf support - discard it for now.
|
||||
*/
|
||||
/DISCARD/ : { *(.ARM.exidx) }
|
||||
|
||||
end = .;
|
||||
|
||||
/* Leave room above stack for IAP to run. */
|
||||
__StackTop = ORIGIN(ram) + LENGTH(ram) - 32;
|
||||
PROVIDE(_stack = __StackTop);
|
||||
}
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <libopencm3/cm3/scs.h>
|
||||
#include <libopencm3/lpc43xx/nvic.h>
|
||||
|
||||
void nvic_enable_irq(u8 irqn)
|
||||
{
|
||||
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
|
||||
}
|
||||
|
||||
void nvic_disable_irq(u8 irqn)
|
||||
{
|
||||
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
|
||||
}
|
||||
|
||||
u8 nvic_get_pending_irq(u8 irqn)
|
||||
{
|
||||
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
|
||||
}
|
||||
|
||||
void nvic_set_pending_irq(u8 irqn)
|
||||
{
|
||||
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
|
||||
}
|
||||
|
||||
void nvic_clear_pending_irq(u8 irqn)
|
||||
{
|
||||
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
|
||||
}
|
||||
|
||||
u8 nvic_get_active_irq(u8 irqn)
|
||||
{
|
||||
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
|
||||
}
|
||||
|
||||
u8 nvic_get_irq_enabled(u8 irqn)
|
||||
{
|
||||
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
|
||||
}
|
||||
|
||||
void nvic_set_priority(u8 irqn, u8 priority)
|
||||
{
|
||||
if(irqn>NVIC_M4_QEI_IRQ)
|
||||
{
|
||||
/* Cortex-M system interrupts */
|
||||
SCS_SHPR( (irqn&0xF)-4 ) = priority;
|
||||
}else
|
||||
{
|
||||
/* Device specific interrupts */
|
||||
NVIC_IPR(irqn) = priority;
|
||||
}
|
||||
}
|
||||
|
||||
void nvic_generate_software_interrupt(u8 irqn)
|
||||
{
|
||||
if (irqn <= 239)
|
||||
NVIC_STIR |= irqn;
|
||||
}
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
|
||||
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */
|
||||
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf)
|
||||
{
|
||||
MMIO32(group_pin) = scu_conf;
|
||||
}
|
||||
|
||||
/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */
|
||||
|
||||
/* For Pin interrupt select register see scu.h SCU_PINTSEL0 & SCU_PINTSEL1 */
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/ssp.h>
|
||||
#include <libopencm3/lpc43xx/cgu.h>
|
||||
|
||||
#define CGU_SRC_32K 0x00
|
||||
#define CGU_SRC_IRC 0x01
|
||||
#define CGU_SRC_ENET_RX 0x02
|
||||
#define CGU_SRC_ENET_TX 0x03
|
||||
#define CGU_SRC_GP_CLKIN 0x04
|
||||
#define CGU_SRC_XTAL 0x06
|
||||
#define CGU_SRC_PLL0USB 0x07
|
||||
#define CGU_SRC_PLL0AUDIO 0x08
|
||||
#define CGU_SRC_PLL1 0x09
|
||||
#define CGU_SRC_IDIVA 0x0C
|
||||
#define CGU_SRC_IDIVB 0x0D
|
||||
#define CGU_SRC_IDIVC 0x0E
|
||||
#define CGU_SRC_IDIVD 0x0F
|
||||
#define CGU_SRC_IDIVE 0x10
|
||||
|
||||
#define CGU_AUTOBLOCK_CLOCK_BIT 11
|
||||
#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
|
||||
|
||||
/* Disable SSP */
|
||||
void ssp_disable(ssp_num_t ssp_num)
|
||||
{
|
||||
u32 ssp_port;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
/* Disable SSP */
|
||||
SSP_CR1(ssp_port) = 0x0;
|
||||
}
|
||||
|
||||
/*
|
||||
* SSP Init function
|
||||
*/
|
||||
void ssp_init(ssp_num_t ssp_num,
|
||||
ssp_datasize_t data_size,
|
||||
ssp_frame_format_t frame_format,
|
||||
ssp_cpol_cpha_t cpol_cpha_format,
|
||||
u8 serial_clock_rate,
|
||||
u8 clk_prescale,
|
||||
ssp_mode_t mode,
|
||||
ssp_master_slave_t master_slave,
|
||||
ssp_slave_option_t slave_option)
|
||||
{
|
||||
u32 ssp_port;
|
||||
u32 clock;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
|
||||
/* use PLL1 as clock source for SSP1 */
|
||||
CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) | (1<<CGU_AUTOBLOCK_CLOCK_BIT);
|
||||
|
||||
/* Disable SSP before to configure it */
|
||||
SSP_CR1(ssp_port) = 0x0;
|
||||
|
||||
/* Configure SSP */
|
||||
clock = serial_clock_rate;
|
||||
SSP_CPSR(ssp_port) = clk_prescale;
|
||||
SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) );
|
||||
|
||||
/* Enable SSP */
|
||||
SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option);
|
||||
}
|
||||
|
||||
/*
|
||||
* This Function Wait until Data RX Ready, and return Data Read from SSP.
|
||||
*/
|
||||
u16 ssp_read(ssp_num_t ssp_num)
|
||||
{
|
||||
u32 ssp_port;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
/* Wait Until Data Received (Rx FIFO not Empty) */
|
||||
while( (SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
|
||||
|
||||
return SSP_DR(ssp_port);
|
||||
}
|
||||
|
||||
void ssp_wait_until_not_busy(ssp_num_t ssp_num)
|
||||
{
|
||||
u32 ssp_port;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
|
||||
while( (SSP_SR(ssp_port) & SSP_SR_BSY) );
|
||||
}
|
||||
|
||||
/* This Function Wait Data TX Ready, and Write Data to SSP */
|
||||
void ssp_write(ssp_num_t ssp_num, u16 data)
|
||||
{
|
||||
u32 ssp_port;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
|
||||
/* Wait Until FIFO not full */
|
||||
while( (SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
|
||||
|
||||
SSP_DR(ssp_port) = data;
|
||||
|
||||
/* Wait for not busy, since we're controlling CS# of
|
||||
* devices manually and need to wait for the data to
|
||||
* be sent. It may also be important to wait here
|
||||
* in case we're configuring devices via SPI and also
|
||||
* with GPIO control -- we need to know when SPI
|
||||
* commands are effective before altering a device's
|
||||
* state with GPIO. I'm thinking the MAX2837, for
|
||||
* example...
|
||||
*/
|
||||
ssp_wait_until_not_busy(ssp_num);
|
||||
}
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/systick.h>
|
||||
|
||||
void systick_set_reload(u32 value)
|
||||
{
|
||||
STK_LOAD = (value & 0x00FFFFFF);
|
||||
}
|
||||
|
||||
u32 systick_get_value(void)
|
||||
{
|
||||
return STK_VAL;
|
||||
}
|
||||
|
||||
void systick_set_clocksource(u8 clocksource)
|
||||
{
|
||||
STK_CTRL |= clocksource;
|
||||
}
|
||||
|
||||
void systick_interrupt_enable(void)
|
||||
{
|
||||
STK_CTRL |= STK_CTRL_TICKINT;
|
||||
}
|
||||
|
||||
void systick_interrupt_disable(void)
|
||||
{
|
||||
STK_CTRL &= ~STK_CTRL_TICKINT;
|
||||
}
|
||||
|
||||
void systick_counter_enable(void)
|
||||
{
|
||||
STK_CTRL |= STK_CTRL_ENABLE;
|
||||
}
|
||||
|
||||
void systick_counter_disable(void)
|
||||
{
|
||||
STK_CTRL &= ~STK_CTRL_ENABLE;
|
||||
}
|
||||
|
||||
u8 systick_get_countflag(void)
|
||||
{
|
||||
if (STK_CTRL & STK_CTRL_COUNTFLAG)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 systick_get_calib(void)
|
||||
{
|
||||
return (STK_CALIB&0x00FFFFFF);
|
||||
}
|
|
@ -0,0 +1,263 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
|
||||
/* Symbols exported by the linker script(s). */
|
||||
extern unsigned _etext, _data, _edata, _ebss, _stack;
|
||||
extern unsigned _etext_ram, _text_ram, _etext_rom;
|
||||
|
||||
void main(void);
|
||||
void reset_handler(void);
|
||||
void blocking_handler(void);
|
||||
void null_handler(void);
|
||||
|
||||
void WEAK nmi_handler(void);
|
||||
void WEAK hard_fault_handler(void);
|
||||
void WEAK mem_manage_handler(void);
|
||||
void WEAK bus_fault_handler(void);
|
||||
void WEAK usage_fault_handler(void);
|
||||
void WEAK sv_call_handler(void);
|
||||
void WEAK debug_monitor_handler(void);
|
||||
void WEAK pend_sv_handler(void);
|
||||
void WEAK sys_tick_handler(void);
|
||||
void WEAK dac_irqhandler(void);
|
||||
void WEAK m0core_irqhandler(void);
|
||||
void WEAK dma_irqhandler(void);
|
||||
void WEAK ethernet_irqhandler(void);
|
||||
void WEAK sdio_irqhandler(void);
|
||||
void WEAK lcd_irqhandler(void);
|
||||
void WEAK usb0_irqhandler(void);
|
||||
void WEAK usb1_irqhandler(void);
|
||||
void WEAK sct_irqhandler(void);
|
||||
void WEAK ritimer_irqhandler(void);
|
||||
void WEAK timer0_irqhandler(void);
|
||||
void WEAK timer1_irqhandler(void);
|
||||
void WEAK timer2_irqhandler(void);
|
||||
void WEAK timer3_irqhandler(void);
|
||||
void WEAK mcpwm_irqhandler(void);
|
||||
void WEAK adc0_irqhandler(void);
|
||||
void WEAK i2c0_irqhandler(void);
|
||||
void WEAK i2c1_irqhandler(void);
|
||||
void WEAK spi_irqhandler(void);
|
||||
void WEAK adc1_irqhandler(void);
|
||||
void WEAK ssp0_irqhandler(void);
|
||||
void WEAK ssp1_irqhandler(void);
|
||||
void WEAK usart0_irqhandler(void);
|
||||
void WEAK uart1_irqhandler(void);
|
||||
void WEAK usart2_irqhandler(void);
|
||||
void WEAK usart3_irqhandler(void);
|
||||
void WEAK i2s0_irqhandler(void);
|
||||
void WEAK i2s1_irqhandler(void);
|
||||
void WEAK spifi_irqhandler(void);
|
||||
void WEAK sgpio_irqhandler(void);
|
||||
void WEAK pin_int0_irqhandler(void);
|
||||
void WEAK pin_int1_irqhandler(void);
|
||||
void WEAK pin_int2_irqhandler(void);
|
||||
void WEAK pin_int3_irqhandler(void);
|
||||
void WEAK pin_int4_irqhandler(void);
|
||||
void WEAK pin_int5_irqhandler(void);
|
||||
void WEAK pin_int6_irqhandler(void);
|
||||
void WEAK pin_int7_irqhandler(void);
|
||||
void WEAK gint0_irqhandler(void);
|
||||
void WEAK gint1_irqhandler(void);
|
||||
void WEAK eventrouter_irqhandler(void);
|
||||
void WEAK c_can1_irqhandler(void);
|
||||
void WEAK atimer_irqhandler(void);
|
||||
void WEAK rtc_irqhandler(void);
|
||||
void WEAK wwdt_irqhandler(void);
|
||||
void WEAK c_can0_irqhandler(void);
|
||||
void WEAK qei_irqhandler(void);
|
||||
|
||||
__attribute__ ((section(".vectors")))
|
||||
void (*const vector_table[]) (void) = {
|
||||
/* Cortex-M4 interrupts */
|
||||
(void*)&_stack,
|
||||
reset_handler,
|
||||
nmi_handler,
|
||||
hard_fault_handler,
|
||||
mem_manage_handler,
|
||||
bus_fault_handler,
|
||||
usage_fault_handler,
|
||||
0, 0, 0, 0, /* reserved */
|
||||
sv_call_handler,
|
||||
debug_monitor_handler,
|
||||
0, /* reserved */
|
||||
pend_sv_handler,
|
||||
sys_tick_handler,
|
||||
|
||||
/* LPC43xx interrupts */
|
||||
dac_irqhandler,
|
||||
m0core_irqhandler,
|
||||
dma_irqhandler,
|
||||
0, /* reserved */
|
||||
0, /* reserved */
|
||||
ethernet_irqhandler,
|
||||
sdio_irqhandler,
|
||||
lcd_irqhandler,
|
||||
usb0_irqhandler,
|
||||
usb1_irqhandler,
|
||||
sct_irqhandler,
|
||||
ritimer_irqhandler,
|
||||
timer0_irqhandler,
|
||||
timer1_irqhandler,
|
||||
timer2_irqhandler,
|
||||
timer3_irqhandler,
|
||||
mcpwm_irqhandler,
|
||||
adc0_irqhandler,
|
||||
i2c0_irqhandler,
|
||||
i2c1_irqhandler,
|
||||
spi_irqhandler,
|
||||
adc1_irqhandler,
|
||||
ssp0_irqhandler,
|
||||
ssp1_irqhandler,
|
||||
usart0_irqhandler,
|
||||
uart1_irqhandler,
|
||||
usart2_irqhandler,
|
||||
usart3_irqhandler,
|
||||
i2s0_irqhandler,
|
||||
i2s1_irqhandler,
|
||||
spifi_irqhandler,
|
||||
sgpio_irqhandler,
|
||||
pin_int0_irqhandler,
|
||||
pin_int1_irqhandler,
|
||||
pin_int2_irqhandler,
|
||||
pin_int3_irqhandler,
|
||||
pin_int4_irqhandler,
|
||||
pin_int5_irqhandler,
|
||||
pin_int6_irqhandler,
|
||||
pin_int7_irqhandler,
|
||||
gint0_irqhandler,
|
||||
gint1_irqhandler,
|
||||
eventrouter_irqhandler,
|
||||
c_can1_irqhandler,
|
||||
0, /* reserved */
|
||||
0, /* reserved */
|
||||
atimer_irqhandler,
|
||||
rtc_irqhandler,
|
||||
0, /* reserved */
|
||||
wwdt_irqhandler,
|
||||
0, /* reserved */
|
||||
c_can0_irqhandler,
|
||||
qei_irqhandler,
|
||||
};
|
||||
|
||||
#define MMIO32(addr) (*(volatile unsigned long*)(addr))
|
||||
#define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) )
|
||||
|
||||
void reset_handler(void)
|
||||
{
|
||||
volatile unsigned *src, *dest;
|
||||
__asm__("MSR msp, %0" : : "r"(&_stack));
|
||||
|
||||
/* Copy the code from ROM to Real RAM (if enabled) */
|
||||
if( (&_etext_ram-&_text_ram) > 0 )
|
||||
{
|
||||
src = &_etext_rom-(&_etext_ram-&_text_ram);
|
||||
/* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */
|
||||
CREG_M4MEMMAP = (unsigned long)src;
|
||||
|
||||
for(dest = &_text_ram; dest < &_etext_ram; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
/* Change Shadow memory to Real RAM */
|
||||
CREG_M4MEMMAP = (unsigned long)&_text_ram;
|
||||
|
||||
/* Continue Execution in RAM */
|
||||
}
|
||||
|
||||
for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
|
||||
*dest = *src;
|
||||
|
||||
while (dest < &_ebss)
|
||||
*dest++ = 0;
|
||||
|
||||
/* Call the application's entry point. */
|
||||
main();
|
||||
}
|
||||
|
||||
void blocking_handler(void)
|
||||
{
|
||||
while (1) ;
|
||||
}
|
||||
|
||||
void null_handler(void)
|
||||
{
|
||||
/* Do nothing. */
|
||||
}
|
||||
|
||||
#pragma weak nmi_handler = null_handler
|
||||
#pragma weak hard_fault_handler = blocking_handler
|
||||
#pragma weak mem_manage_handler = blocking_handler
|
||||
#pragma weak bus_fault_handler = blocking_handler
|
||||
#pragma weak usage_fault_handler = blocking_handler
|
||||
#pragma weak sv_call_handler = null_handler
|
||||
#pragma weak debug_monitor_handler = null_handler
|
||||
#pragma weak pend_sv_handler = null_handler
|
||||
#pragma weak sys_tick_handler = null_handler
|
||||
#pragma weak dac_irqhandler = null_handler
|
||||
#pragma weak m0core_irqhandler = null_handler
|
||||
#pragma weak dma_irqhandler = null_handler
|
||||
#pragma weak ethernet_irqhandler = null_handler
|
||||
#pragma weak sdio_irqhandler = null_handler
|
||||
#pragma weak lcd_irqhandler = null_handler
|
||||
#pragma weak usb0_irqhandler = null_handler
|
||||
#pragma weak usb1_irqhandler = null_handler
|
||||
#pragma weak sct_irqhandler = null_handler
|
||||
#pragma weak ritimer_irqhandler = null_handler
|
||||
#pragma weak timer0_irqhandler = null_handler
|
||||
#pragma weak timer1_irqhandler = null_handler
|
||||
#pragma weak timer2_irqhandler = null_handler
|
||||
#pragma weak timer3_irqhandler = null_handler
|
||||
#pragma weak mcpwm_irqhandler = null_handler
|
||||
#pragma weak adc0_irqhandler = null_handler
|
||||
#pragma weak i2c0_irqhandler = null_handler
|
||||
#pragma weak i2c1_irqhandler = null_handler
|
||||
#pragma weak spi_irqhandler = null_handler
|
||||
#pragma weak adc1_irqhandler = null_handler
|
||||
#pragma weak ssp0_irqhandler = null_handler
|
||||
#pragma weak ssp1_irqhandler = null_handler
|
||||
#pragma weak usart0_irqhandler = null_handler
|
||||
#pragma weak uart1_irqhandler = null_handler
|
||||
#pragma weak usart2_irqhandler = null_handler
|
||||
#pragma weak usart3_irqhandler = null_handler
|
||||
#pragma weak i2s0_irqhandler = null_handler
|
||||
#pragma weak i2s1_irqhandler = null_handler
|
||||
#pragma weak spifi_irqhandler = null_handler
|
||||
#pragma weak sgpio_irqhandler = null_handler
|
||||
#pragma weak pin_int0_irqhandler = null_handler
|
||||
#pragma weak pin_int1_irqhandler = null_handler
|
||||
#pragma weak pin_int2_irqhandler = null_handler
|
||||
#pragma weak pin_int3_irqhandler = null_handler
|
||||
#pragma weak pin_int4_irqhandler = null_handler
|
||||
#pragma weak pin_int5_irqhandler = null_handler
|
||||
#pragma weak pin_int6_irqhandler = null_handler
|
||||
#pragma weak pin_int7_irqhandler = null_handler
|
||||
#pragma weak gint0_irqhandler = null_handler
|
||||
#pragma weak gint1_irqhandler = null_handler
|
||||
#pragma weak eventrouter_irqhandler = null_handler
|
||||
#pragma weak c_can1_irqhandler = null_handler
|
||||
#pragma weak atimer_irqhandler = null_handler
|
||||
#pragma weak rtc_irqhandler = null_handler
|
||||
#pragma weak wwdt_irqhandler = null_handler
|
||||
#pragma weak c_can0_irqhandler = null_handler
|
||||
#pragma weak qei_irqhandler = null_handler
|
|
@ -0,0 +1,51 @@
|
|||
#!/usr/bin/python
|
||||
#
|
||||
# Compute and insert the vector table checksum required for booting the
|
||||
# LPC43xx and some other NXP ARM microcontrollers.
|
||||
#
|
||||
# usage: lpcvtcksum firmware.bin
|
||||
#
|
||||
# This file is part of the libopencm3 project.
|
||||
#
|
||||
# Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
#
|
||||
# This library is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU Lesser General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This library is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU Lesser General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU Lesser General Public License
|
||||
# along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
import sys, struct
|
||||
|
||||
binfile = open(sys.argv[1], 'r+b')
|
||||
rawvectors = binfile.read(32)
|
||||
vectors = list(struct.unpack('<IIIIIIII', rawvectors))
|
||||
|
||||
# compute vector table checksum
|
||||
sum = 0
|
||||
for i in range(7):
|
||||
sum += vectors[i]
|
||||
vectors[7] = 1 + (0xffffffff ^ (0xffffffff & sum))
|
||||
|
||||
print "computed vector table checksum: 0x%08x" % vectors[7]
|
||||
|
||||
rawremainder = binfile.read()
|
||||
remainder = list(struct.unpack('B' * len(rawremainder), rawremainder))
|
||||
numbytes = len(remainder) + 32
|
||||
|
||||
# pad to multiple of 4096 bytes to make GoodFET happy
|
||||
if (numbytes % 4096):
|
||||
remainder.extend([0] * (4096 - numbytes % 4096))
|
||||
|
||||
# rewrite file with checksum and padding
|
||||
data = vectors
|
||||
data.extend(remainder)
|
||||
binfile.seek(0)
|
||||
binfile.write(struct.pack('<IIIIIIII' + 'B' * len(remainder), *data))
|
Loading…
Reference in New Issue