From 3eb94bb335e4ee2ad24e2fa77166510d706e8782 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sun, 24 Jan 2021 22:10:05 +0000 Subject: [PATCH] stm32: dac: document: whitespace for legibility --- lib/stm32/common/dac_common_all.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/stm32/common/dac_common_all.c b/lib/stm32/common/dac_common_all.c index 4e54feb9..c4665fcf 100644 --- a/lib/stm32/common/dac_common_all.c +++ b/lib/stm32/common/dac_common_all.c @@ -85,11 +85,11 @@ Both DAC channels are enabled, and both triggers are set to the same timer 1 only to ensure that only one DMA request is generated. @code - dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT); - dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT); - dma_set_read_from_memory(DMA2,DMA_CHANNEL3); - dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(uint32_t) &DAC_DHR8RD); - dma_enable_channel(DMA2,DMA_CHANNEL3); + dma_set_memory_size(DMA2, DMA_CHANNEL3, DMA_CCR_MSIZE_16BIT); + dma_set_peripheral_size(DMA2, DMA_CHANNEL3, DMA_CCR_PSIZE_16BIT); + dma_set_read_from_memory(DMA2, DMA_CHANNEL3); + dma_set_peripheral_address(DMA2, DMA_CHANNEL3,(uint32_t) &DAC_DHR8RD); + dma_enable_channel(DMA2, DMA_CHANNEL3); ... dac_trigger_enable(DAC1, DAC_CHANNEL_BOTH); dac_set_trigger_source(DAC1, DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2);