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Fix numerous bugs in NVIC convenience functions, doing an |= on a clear register will clear ALL currently enabled irqs, not just the one you specified and other things of that sort. Also changed to support the full range of irq numbers supported by ARMv7M, not just the first 68 used in the STM32F1 series.

This commit is contained in:
Fergus Noble 2012-01-31 16:14:55 -08:00 committed by Uwe Hermann
parent 477c410be4
commit 3e47a46c5c
1 changed files with 8 additions and 45 deletions
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53
lib/stm32/nvic.c
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@ -2,6 +2,7 @@
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -21,75 +22,37 @@
void nvic_enable_irq(u8 irqn)
{
if (irqn < 32)
NVIC_ISER(0) |= (1 << irqn);
if ((irqn >= 32) & (irqn < 64))
NVIC_ISER(1) |= (1 << (irqn - 32));
if ((irqn >= 64) & (irqn < 68))
NVIC_ISER(2) |= (1 << (irqn - 64));
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
}
void nvic_disable_irq(u8 irqn)
{
if (irqn < 32)
NVIC_ICER(0) |= (1 << irqn);
if ((irqn >= 32) & (irqn < 64))
NVIC_ICER(1) |= (1 << (irqn - 32));
if ((irqn >= 64) & (irqn < 68))
NVIC_ICER(2) |= (1 << (irqn - 64));
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
}
u8 nvic_get_pending_irq(u8 irqn)
{
if (irqn < 32)
return (NVIC_ISPR(0) & (1 << irqn));
if ((irqn >= 32) & (irqn < 64))
return (NVIC_ISPR(1) & (1 << (irqn - 32)));
if ((irqn >= 64) & (irqn < 68))
return (NVIC_ISPR(2) & (1 << (irqn - 64)));
return 0;
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1:0;
}
void nvic_set_pending_irq(u8 irqn)
{
if (irqn < 32)
NVIC_ISPR(0) |= (1 << irqn);
if ((irqn >= 32) & (irqn < 64))
NVIC_ISPR(1) |= (1 << (irqn - 32));
if ((irqn >= 64) & (irqn < 68))
NVIC_ISPR(2) |= (1 << (irqn - 64));
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
}
void nvic_clear_pending_irq(u8 irqn)
{
if (irqn < 32)
NVIC_ICPR(0) |= (1 << irqn);
if ((irqn >= 32) & (irqn < 64))
NVIC_ICPR(1) |= (1 << (irqn - 32));
if ((irqn >= 64) & (irqn < 68))
NVIC_ICPR(2) |= (1 << (irqn - 64));
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
}
u8 nvic_get_active_irq(u8 irqn)
{
if (irqn < 32)
return (NVIC_IABR(0) & (1 << irqn));
if ((irqn >= 32) & (irqn < 64))
return (NVIC_IABR(1) & (1 << (irqn - 32)));
if ((irqn >= 64) & (irqn < 68))
return (NVIC_IABR(2) & (1 << (irqn - 64)));
return 0;
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1:0;
}
u8 nvic_get_irq_enabled(u8 irqn)
{
if (irqn < 32)
return (NVIC_ISER(0) & (1 << irqn));
if ((irqn >= 32) & (irqn < 64))
return (NVIC_ISER(1) & (1 << (irqn - 32)));
if ((irqn >= 64) & (irqn < 68))
return (NVIC_ISER(2) & (1 << (irqn - 64)));
return 0;
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1:0;
}
void nvic_set_priority(u8 irqn, u8 priority)