resolved minor conflict
This commit is contained in:
Michael Ossmann
commit
3a4a6b75de
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@ -94,6 +94,7 @@ clean:
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$(Q)rm -f *.hex
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$(Q)rm -f *.srec
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$(Q)rm -f *.list
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$(Q)rm -f *.map
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# FIXME: Replace STM32 stuff with proper LPC43XX OpenOCD support later.
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ifeq ($(OOCD_SERIAL),)
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@ -27,9 +27,9 @@ extern "C"
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#include <libopencm3/lpc43xx/scu.h>
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/************************/
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/* JellyBean SCU PinMux */
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/************************/
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/*
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* JellyBean SCU PinMux
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*/
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/* GPIO Output PinMux */
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#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */
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@ -44,12 +44,17 @@ extern "C"
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#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
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#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
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/* SSP1 Peripheral PinMux */
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#define SCU_SSP1_MISO (P1_3) /* P1_3 */
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#define SCU_SSP1_MOSI (P1_4) /* P1_4 */
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#define SCU_SSP1_SCK (P1_19) /* P1_19 */
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#define SCU_SSP1_SSEL (P1_20) /* P1_20 */
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/* TODO add other Pins */
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/**********************/
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/* JellyBean GPIO Pin */
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/**********************/
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/*
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* JellyBean GPIO Pin
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*/
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/* GPIO Output */
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#define PIN_LED1 (BIT1) /* GPIO2[1] on P4_1 */
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#define PIN_LED2 (BIT2) /* GPIO2[2] on P4_2 */
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@ -1,22 +1,22 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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||||
* it under the terms of the GNU Lesser General Public License as published by
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||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
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||||
*
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* This library is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
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||||
*
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* You should have received a copy of the GNU Lesser General Public License
|
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
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||||
*
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* This library is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/lpc43xx/gpio.h>
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#include <libopencm3/lpc43xx/scu.h>
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@ -25,32 +25,38 @@
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void gpio_setup(void)
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{
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/* Configure SCU Pin Mux as GPIO */
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scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
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/* Configure SCU Pin Mux as GPIO */
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scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
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/* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */
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SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
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/* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */
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SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
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/* Configure all GPIO as Input (safe state) */
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GPIO0_DIR = 0;
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GPIO1_DIR = 0;
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GPIO2_DIR = 0;
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GPIO3_DIR = 0;
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GPIO4_DIR = 0;
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GPIO5_DIR = 0;
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GPIO6_DIR = 0;
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GPIO7_DIR = 0;
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/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
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scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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/* Configure GPIO as Output */
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/* Configure all GPIO as Input (safe state) */
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GPIO0_DIR = 0;
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GPIO1_DIR = 0;
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GPIO2_DIR = 0;
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GPIO3_DIR = 0;
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GPIO4_DIR = 0;
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GPIO5_DIR = 0;
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GPIO6_DIR = 0;
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GPIO7_DIR = 0;
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/* Configure GPIO as Output */
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GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
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GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
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}
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@ -62,16 +68,16 @@ int main(void)
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int i;
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gpio_setup();
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/* Set 1V8 */
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gpio_set(PORT_EN1V8, PIN_EN1V8);
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/* Set 1V8 */
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gpio_set(PORT_EN1V8, PIN_EN1V8);
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/* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */
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while (1)
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{
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boot0 = BOOT0_STATE;
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boot1 = BOOT1_STATE;
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boot2 = BOOT2_STATE;
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boot3 = BOOT3_STATE;
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{
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boot0 = BOOT0_STATE;
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boot1 = BOOT1_STATE;
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boot2 = BOOT2_STATE;
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boot3 = BOOT3_STATE;
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gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
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for (i = 0; i < 2000000; i++) /* Wait a bit. */
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@ -0,0 +1,24 @@
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##
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## This file is part of the libopencm3 project.
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##
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## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This library is free software: you can redistribute it and/or modify
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## it under the terms of the GNU Lesser General Public License as published by
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## the Free Software Foundation, either version 3 of the License, or
|
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## (at your option) any later version.
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##
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## This library is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU Lesser General Public License for more details.
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##
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## You should have received a copy of the GNU Lesser General Public License
|
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## along with this library. If not, see <http://www.gnu.org/licenses/>.
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##
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BINARY = sspdemo
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LDSCRIPT = ../jellybean-lpc4330.ld
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include ../../Makefile.include
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@ -0,0 +1,20 @@
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------------------------------------------------------------------------------
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README
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------------------------------------------------------------------------------
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This program exercises the SSP1 peripheral on Jellybean's LPC43xx.
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Jellybean (connector)
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P9 SPI
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|-----------------|
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| Pin2 Pin4 Pin6 |
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||------| |
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|| Pin1 |Pin3 Pin5 |
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||------|----------|
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|-------|
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SSP1_MISO: Jellybean P9 SPI Pin6
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SSP1_MOSI: Jellybean P9 SPI Pin4
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SSP1_SCK: Jellybean P9 SPI Pin2
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SSP1_SSEL: Jellybean P9 SPI Pin3
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GND: Can be connected to P12 SD Pin1
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@ -0,0 +1,99 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
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#include <libopencm3/lpc43xx/gpio.h>
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/cgu.h>
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#include <libopencm3/lpc43xx/ssp.h>
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#include "../jellybean_conf.h"
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void gpio_setup(void)
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{
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/* Configure SCU Pin Mux as GPIO */
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scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
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/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
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scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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/* Configure all GPIO as Input (safe state) */
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GPIO0_DIR = 0;
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GPIO1_DIR = 0;
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GPIO2_DIR = 0;
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GPIO3_DIR = 0;
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GPIO4_DIR = 0;
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GPIO5_DIR = 0;
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GPIO6_DIR = 0;
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GPIO7_DIR = 0;
|
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/* Configure GPIO as Output */
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GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
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GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
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}
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int main(void)
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{
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int i;
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u8 ssp_val;
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u8 serial_clock_rate;
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gpio_setup();
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|
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/* FIX Me freq */
|
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serial_clock_rate = 128;
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ssp_init(SSP1_NUM,
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SSP_DATA_8BITS,
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SSP_FRAME_SPI,
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SSP_CPOL_0_CPHA_0,
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serial_clock_rate,
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SSP_MODE_NORMAL,
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SSP_MASTER,
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SSP_SLAVE_OUT_ENABLE);
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ssp_val = 0x0;
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while (1) {
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ssp_write(SSP1_NUM, (u16)ssp_val);
|
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|
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gpio_set(GPIO2, GPIOPIN1); /* LED on */
|
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|
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for (i = 0; i < 1000; i++) /* Wait a bit. */
|
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__asm__("nop");
|
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|
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gpio_clear(GPIO2, GPIOPIN1); /* LED off */
|
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|
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ssp_val++;
|
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}
|
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|
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return 0;
|
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}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,21 +1,21 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC43XX_SSP_H
|
||||
#define LPC43XX_SSP_H
|
||||
|
|
@ -26,60 +26,150 @@
|
|||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* SSP port base addresses (for convenience) */
|
||||
#define SSP0 SSP0_BASE
|
||||
#define SSP1 SSP1_BASE
|
||||
#define SSP0 SSP0_BASE
|
||||
#define SSP1 SSP1_BASE
|
||||
|
||||
|
||||
/* --- SSP registers ------------------------------------------------------- */
|
||||
|
||||
/* Control Register 0 */
|
||||
#define SSP_CR0(port) MMIO32(port + 0x000)
|
||||
#define SSP0_CR0 SSP_CR0(SSP0)
|
||||
#define SSP1_CR0 SSP_CR0(SSP1)
|
||||
#define SSP_CR0(port) MMIO32(port + 0x000)
|
||||
#define SSP0_CR0 SSP_CR0(SSP0)
|
||||
#define SSP1_CR0 SSP_CR0(SSP1)
|
||||
|
||||
/* Control Register 1 */
|
||||
#define SSP_CR1(port) MMIO32(port + 0x004)
|
||||
#define SSP0_CR1 SSP_CR1(SSP0)
|
||||
#define SSP1_CR1 SSP_CR1(SSP1)
|
||||
#define SSP_CR1(port) MMIO32(port + 0x004)
|
||||
#define SSP0_CR1 SSP_CR1(SSP0)
|
||||
#define SSP1_CR1 SSP_CR1(SSP1)
|
||||
|
||||
/* Data Register */
|
||||
#define SSP_DR(port) MMIO32(port + 0x008)
|
||||
#define SSP0_DR SSP_DR(SSP0)
|
||||
#define SSP1_DR SSP_DR(SSP1)
|
||||
#define SSP_DR(port) MMIO32(port + 0x008)
|
||||
#define SSP0_DR SSP_DR(SSP0)
|
||||
#define SSP1_DR SSP_DR(SSP1)
|
||||
|
||||
/* Status Register */
|
||||
#define SSP_SR(port) MMIO32(port + 0x00C)
|
||||
#define SSP0_SR SSP_SR(SSP0)
|
||||
#define SSP1_SR SSP_SR(SSP1)
|
||||
#define SSP_SR(port) MMIO32(port + 0x00C)
|
||||
#define SSP0_SR SSP_SR(SSP0)
|
||||
#define SSP1_SR SSP_SR(SSP1)
|
||||
|
||||
#define SSP_SR_TFE BIT0
|
||||
#define SSP_SR_TNF BIT1
|
||||
#define SSP_SR_RNE BIT2
|
||||
#define SSP_SR_RFF BIT3
|
||||
#define SSP_SR_BSY BIT4
|
||||
|
||||
/* Clock Prescale Register */
|
||||
#define SSP_CPSR(port) MMIO32(port + 0x010)
|
||||
#define SSP0_CPSR SSP_CPSR(SSP0)
|
||||
#define SSP1_CPSR SSP_CPSR(SSP1)
|
||||
#define SSP_CPSR(port) MMIO32(port + 0x010)
|
||||
#define SSP0_CPSR SSP_CPSR(SSP0)
|
||||
#define SSP1_CPSR SSP_CPSR(SSP1)
|
||||
|
||||
/* Interrupt Mask Set and Clear Register */
|
||||
#define SSP_IMSC(port) MMIO32(port + 0x014)
|
||||
#define SSP0_IMSC SSP_IMSC(SSP0)
|
||||
#define SSP1_IMSC SSP_IMSC(SSP1)
|
||||
#define SSP_IMSC(port) MMIO32(port + 0x014)
|
||||
#define SSP0_IMSC SSP_IMSC(SSP0)
|
||||
#define SSP1_IMSC SSP_IMSC(SSP1)
|
||||
|
||||
/* Raw Interrupt Status Register */
|
||||
#define SSP_RIS(port) MMIO32(port + 0x018)
|
||||
#define SSP0_RIS SSP_RIS(SSP0)
|
||||
#define SSP1_RIS SSP_RIS(SSP1)
|
||||
#define SSP_RIS(port) MMIO32(port + 0x018)
|
||||
#define SSP0_RIS SSP_RIS(SSP0)
|
||||
#define SSP1_RIS SSP_RIS(SSP1)
|
||||
|
||||
/* Masked Interrupt Status Register */
|
||||
#define SSP_MIS(port) MMIO32(port + 0x01C)
|
||||
#define SSP0_MIS SSP_MIS(SSP0)
|
||||
#define SSP1_MIS SSP_MIS(SSP1)
|
||||
#define SSP_MIS(port) MMIO32(port + 0x01C)
|
||||
#define SSP0_MIS SSP_MIS(SSP0)
|
||||
#define SSP1_MIS SSP_MIS(SSP1)
|
||||
|
||||
/* SSPICR Interrupt Clear Register */
|
||||
#define SSP_ICR(port) MMIO32(port + 0x020)
|
||||
#define SSP0_ICR SSP_ICR(SSP0)
|
||||
#define SSP1_ICR SSP_ICR(SSP1)
|
||||
#define SSP_ICR(port) MMIO32(port + 0x020)
|
||||
#define SSP0_ICR SSP_ICR(SSP0)
|
||||
#define SSP1_ICR SSP_ICR(SSP1)
|
||||
|
||||
/* SSP1 DMA control register */
|
||||
#define SSP_DMACR(port) MMIO32(port + 0x024)
|
||||
#define SSP0_DMACR SSP_DMACR(SSP0)
|
||||
#define SSP1_DMACR SSP_DMACR(SSP1)
|
||||
#define SSP_DMACR(port) MMIO32(port + 0x024)
|
||||
#define SSP0_DMACR SSP_DMACR(SSP0)
|
||||
#define SSP1_DMACR SSP_DMACR(SSP1)
|
||||
|
||||
typedef enum {
|
||||
SSP0_NUM = 0x0,
|
||||
SSP1_NUM = 0x1
|
||||
} ssp_num_t;
|
||||
|
||||
/*
|
||||
* SSP Control Register 0
|
||||
*/
|
||||
/* SSP Data Size Bits 0 to 3 */
|
||||
typedef enum {
|
||||
SSP_DATA_4BITS = 0x3,
|
||||
SSP_DATA_5BITS = 0x4,
|
||||
SSP_DATA_6BITS = 0x5,
|
||||
SSP_DATA_7BITS = 0x6,
|
||||
SSP_DATA_8BITS = 0x7,
|
||||
SSP_DATA_9BITS = 0x8,
|
||||
SSP_DATA_10BITS = 0x9,
|
||||
SSP_DATA_11BITS = 0xA,
|
||||
SSP_DATA_12BITS = 0xB,
|
||||
SSP_DATA_13BITS = 0xC,
|
||||
SSP_DATA_14BITS = 0xD,
|
||||
SSP_DATA_15BITS = 0xE,
|
||||
SSP_DATA_16BITS = 0xF
|
||||
} ssp_datasize_t;
|
||||
|
||||
/* SSP Frame Format/Type Bits 4 & 5 */
|
||||
typedef enum {
|
||||
SSP_FRAME_SPI = 0x00,
|
||||
SSP_FRAME_TI = BIT4,
|
||||
SSP_FRAM_MICROWIRE = BIT5
|
||||
} ssp_frame_format_t;
|
||||
|
||||
/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */
|
||||
typedef enum {
|
||||
SSP_CPOL_0_CPHA_0 = 0x0,
|
||||
SSP_CPOL_1_CPHA_0 = BIT6,
|
||||
SSP_CPOL_0_CPHA_1 = BIT7,
|
||||
SSP_CPOL_1_CPHA_1 = (BIT6|BIT7)
|
||||
} ssp_cpol_cpha_t;
|
||||
|
||||
/*
|
||||
* SSP Control Register 1
|
||||
*/
|
||||
/* SSP Mode Bit0 */
|
||||
typedef enum {
|
||||
SSP_MODE_NORMAL = 0x0,
|
||||
SSP_MODE_LOOPBACK = BIT0
|
||||
} ssp_mode_t;
|
||||
|
||||
/* SSP Enable Bit1 */
|
||||
#define SSP_ENABLE BIT1
|
||||
|
||||
/* SSP Master/Slave Mode Bit2 */
|
||||
typedef enum {
|
||||
SSP_MASTER = 0x0,
|
||||
SSP_SLAVE = BIT2
|
||||
} ssp_master_slave_t;
|
||||
|
||||
/*
|
||||
* SSP Slave Output Disable Bit3
|
||||
* Slave Output Disable. This bit is relevant only in slave mode
|
||||
* (MS = 1). If it is 1, this blocks this SSP controller from driving the
|
||||
* transmit data line (MISO).
|
||||
*/
|
||||
typedef enum {
|
||||
SSP_SLAVE_OUT_ENABLE = 0x0,
|
||||
SSP_SLAVE_OUT_DISABLE = BIT3
|
||||
} ssp_slave_option_t; /* This option is relevant only in slave mode */
|
||||
|
||||
void ssp_disable(ssp_num_t ssp_num);
|
||||
|
||||
void ssp_init( ssp_num_t ssp_num,
|
||||
ssp_datasize_t data_size,
|
||||
ssp_frame_format_t frame_format,
|
||||
ssp_cpol_cpha_t cpol_cpha_format,
|
||||
u8 serial_clock_rate,
|
||||
ssp_mode_t mode,
|
||||
ssp_master_slave_t master_slave,
|
||||
ssp_slave_option_t slave_option);
|
||||
|
||||
u16 ssp_read(ssp_num_t ssp_num);
|
||||
|
||||
void ssp_write(ssp_num_t ssp_num, u16 data);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \
|
|||
-mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
OBJS = gpio.o vector.o scu.o i2c.o
|
||||
OBJS = gpio.o vector.o scu.o i2c.o ssp.o
|
||||
|
||||
# VPATH += ../usb
|
||||
|
||||
|
|
|
|||
|
|
@ -1,28 +1,28 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
|
||||
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */
|
||||
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf)
|
||||
{
|
||||
MMIO32(group_pin) = scu_conf;
|
||||
MMIO32(group_pin) = scu_conf;
|
||||
}
|
||||
|
||||
/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/ssp.h>
|
||||
#include <libopencm3/lpc43xx/cgu.h>
|
||||
|
||||
#define CGU_SRC_32K 0x00
|
||||
#define CGU_SRC_IRC 0x01
|
||||
#define CGU_SRC_ENET_RX 0x02
|
||||
#define CGU_SRC_ENET_TX 0x03
|
||||
#define CGU_SRC_GP_CLKIN 0x04
|
||||
#define CGU_SRC_XTAL 0x06
|
||||
#define CGU_SRC_PLL0USB 0x07
|
||||
#define CGU_SRC_PLL0AUDIO 0x08
|
||||
#define CGU_SRC_PLL1 0x09
|
||||
#define CGU_SRC_IDIVA 0x0C
|
||||
#define CGU_SRC_IDIVB 0x0D
|
||||
#define CGU_SRC_IDIVC 0x0E
|
||||
#define CGU_SRC_IDIVD 0x0F
|
||||
#define CGU_SRC_IDIVE 0x10
|
||||
|
||||
#define CGU_AUTOBLOCK_CLOCK_BIT 11
|
||||
#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
|
||||
|
||||
/* Disable SSP */
|
||||
void ssp_disable(ssp_num_t ssp_num)
|
||||
{
|
||||
u32 ssp_port;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
/* Disable SSP */
|
||||
SSP_CR1(ssp_port) = 0x0;
|
||||
}
|
||||
|
||||
/*
|
||||
* SSP Init function
|
||||
*/
|
||||
void ssp_init(ssp_num_t ssp_num,
|
||||
ssp_datasize_t data_size,
|
||||
ssp_frame_format_t frame_format,
|
||||
ssp_cpol_cpha_t cpol_cpha_format,
|
||||
u8 serial_clock_rate,
|
||||
ssp_mode_t mode,
|
||||
ssp_master_slave_t master_slave,
|
||||
ssp_slave_option_t slave_option)
|
||||
{
|
||||
u32 ssp_port;
|
||||
u32 clock;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
|
||||
/* use PLL1 as clock source for SSP1 */
|
||||
CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) | (1<<CGU_AUTOBLOCK_CLOCK_BIT);
|
||||
|
||||
/* Disable SSP before to configure it */
|
||||
SSP_CR1(ssp_port) = 0x0;
|
||||
|
||||
/* Configure SSP */
|
||||
clock = serial_clock_rate;
|
||||
SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) );
|
||||
|
||||
/* Enable SSP */
|
||||
SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option);
|
||||
}
|
||||
|
||||
/*
|
||||
* This Function Wait until Data RX Ready, and return Data Read from SSP.
|
||||
*/
|
||||
u16 ssp_read(ssp_num_t ssp_num)
|
||||
{
|
||||
u32 ssp_port;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
/* Wait Until Data Received (Rx FIFO not Empty) */
|
||||
while( (SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
|
||||
|
||||
return SSP_DR(ssp_port);
|
||||
}
|
||||
|
||||
/* This Function Wait Data TX Ready, and Write Data to SSP */
|
||||
void ssp_write(ssp_num_t ssp_num, u16 data)
|
||||
{
|
||||
u32 ssp_port;
|
||||
|
||||
if(ssp_num == SSP0_NUM)
|
||||
{
|
||||
ssp_port = SSP0;
|
||||
}else
|
||||
{
|
||||
ssp_port = SSP1;
|
||||
}
|
||||
|
||||
/* Wait Until FIFO not full */
|
||||
while( (SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
|
||||
|
||||
SSP_DR(ssp_port) = data;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue