Only allow one packet in TX fifos.
This fixes a problem where packets were written too quickly. The hardware disabled the endpoint after the fist packet is sent, and others just waited in the queue.
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7546ad9736
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30e188cf07
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@ -245,7 +245,7 @@ static u16 stm32f107_ep_write_packet(u8 addr, const void *buf, u16 len)
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addr &= 0x7F;
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/* Return if endpoint is already enabled. */
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if(OTG_FS_DTXFSTS(addr) < (len >> 2))
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if(OTG_FS_DIEPTSIZ(addr) & OTG_FS_DIEPSIZ0_PKTCNT)
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return 0;
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/* Enable endpoint for transmission */
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