Partial merge of RCC support work contributed by Federico Ruiz-Ugalde.
For now, this adds a bunch of #defines, double-checked against the datasheet by me (added a few missing values for "connectivity line" STM32s).
This commit is contained in:
Uwe Hermann
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -22,8 +23,113 @@
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#include "libopenstm32.h"
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/* RCC registers */
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/* Note: AHBRSTR/CFGR2 only exist in "connectivity line" STM32s. */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
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#define RCC_CIR MMIO32(RCC_BASE + 0x08)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
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#define RCC_CSR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* See note */
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#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* See note */
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/* RCC_APB2ENR values */
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/* Note: IOPFEN/IOPGEN are reserved in "connectivity line" STM32s. */
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#define RCC_AFIOEN (1 << 0)
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#define RCC_IOPAEN (1 << 2)
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#define RCC_IOPBEN (1 << 3)
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#define RCC_IOPCEN (1 << 4)
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#define RCC_IOPDEN (1 << 5)
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#define RCC_IOPEEN (1 << 6)
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#define RCC_IOPFEN (1 << 7) /* N/A in all devices */
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#define RCC_IOPGEN (1 << 8) /* N/A in all devices */
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#define RCC_ADC1EN (1 << 9)
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#define RCC_ADC2EN (1 << 10)
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#define RCC_TIM1EN (1 << 11)
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#define RCC_SPI1EN (1 << 12)
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#define RCC_USART1EN (1 << 14)
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/* --- RCC_CFGS values ----------------------------------------------------- */
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/* TODO: SW */
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/* TODO: SWS */
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/* HPRE: AHB prescaler */
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#define HPRE_SYSCLK 0x0
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#define HPRE_SYSCLK_DIV2 0x8
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#define HPRE_SYSCLK_DIV4 0x9
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#define HPRE_SYSCLK_DIV8 0xa
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#define HPRE_SYSCLK_DIV16 0xb
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#define HPRE_SYSCLK_DIV64 0xc
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#define HPRE_SYSCLK_DIV128 0xd
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#define HPRE_SYSCLK_DIV256 0xe
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#define HPRE_SYSCLK_DIV512 0xf
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/* PPRE1: APB low-speed prescaler (APB1) */
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#define PPRE1_HCLK 0x0
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#define PPRE1_HCLK_DIV2 0x4
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#define PPRE1_HCLK_DIV4 0x5
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#define PPRE1_HCLK_DIV8 0x6
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#define PPRE1_HCLK_DIV16 0x7
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define PPRE2_HCLK 0x0
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#define PPRE2_HCLK_DIV2 0x4
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#define PPRE2_HCLK_DIV4 0x5
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#define PPRE2_HCLK_DIV8 0x6
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#define PPRE2_HCLK_DIV16 0x7
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/* ADCPRE: ADC prescaler */
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#define ADCPRE_PLCLK2_DIV2 0x0
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#define ADCPRE_PLCLK2_DIV4 0x1
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#define ADCPRE_PLCLK2_DIV6 0x2
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#define ADCPRE_PLCLK2_DIV8 0x3
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/* PLLSRC: PLL entry clock source */
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#define PLLSRC_HSI_CLKDIV2 0x0
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#define PLLSRC_HSE_CLK 0x1
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/* PLLXTPRE: HSE divider for PLL entry */
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#define PLLXTPRE_HSE_CLK 0x0
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#define PLLXTPRE_HSE_CLK_DIV2 0x1
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/* PLLMUL: PLL multiplication factor */
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#define PLLMUL_PLLCLK_MUL2 0x0
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#define PLLMUL_PLLCLK_MUL3 0x1
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#define PLLMUL_PLLCLK_MUL4 0x2
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#define PLLMUL_PLLCLK_MUL5 0x3
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#define PLLMUL_PLLCLK_MUL6 0x4
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#define PLLMUL_PLLCLK_MUL7 0x5
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#define PLLMUL_PLLCLK_MUL8 0x6
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#define PLLMUL_PLLCLK_MUL9 0x7
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#define PLLMUL_PLLCLK_MUL10 0x8
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#define PLLMUL_PLLCLK_MUL11 0x9
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#define PLLMUL_PLLCLK_MUL12 0xa
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#define PLLMUL_PLLCLK_MUL13 0xb
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#define PLLMUL_PLLCLK_MUL14 0xc
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#define PLLMUL_PLLCLK_MUL15 0xd
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#define PLLMUL_PLLCLK_MUL16 0xe
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// #define PLLMUL_PLLCLK_MUL16 0xf /* Errata? 17? */
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/* USBPRE: USB prescaler */
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#define USBPRE_PLLCLK_DIV1_5 0x0
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#define USBPRE_PLLCLK 0x1
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/* MCO: Microcontroller clock output */
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#define MCO_NOCLK 0x0
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#define MCO_SYSCLK 0x4
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#define MCO_HSICLK 0x5
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#define MCO_HSECLK 0x6
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#define MCO_PLLCLK_DIV2 0x7
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#define MCO_PLL2CLK 0x8
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#define MCO_PLL3CLK_DIV2 0x9
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#define MCO_XT1 0xa
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#define MCO_PLL3 0xb
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#endif
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