stm32l0: rcc: add more helper routines.
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@ -622,7 +622,14 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc);
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void rcc_osc_ready_int_disable(enum rcc_osc osc);
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int rcc_osc_ready_int_flag(enum rcc_osc osc);
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void rcc_wait_for_osc_ready(enum rcc_osc osc);
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void rcc_set_hsi48_source_rc48(void);
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void rcc_set_hsi48_source_pll(void);
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void rcc_set_sysclk_source(enum rcc_osc osc);
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void rcc_set_pll_multiplier(uint32_t factor);
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void rcc_set_pll_divider(uint32_t factor);
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void rcc_set_ppre2(uint32_t ppre2);
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void rcc_set_ppre1(uint32_t ppre1);
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void rcc_set_hpre(uint32_t hpre);
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/* TODO */
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END_DECLS
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@ -290,5 +290,117 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc)
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set HSI48 clock source to the RC48 (CRS)
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*/
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void rcc_set_hsi48_source_rc48(void) {
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RCC_CCIPR |= RCC_CCIPR_HSI48SEL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set HSI48 clock source to the PLL
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*/
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void rcc_set_hsi48_source_pll(void) {
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RCC_CCIPR &= ~RCC_CCIPR_HSI48SEL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the Source for the System Clock.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, HSI16, MSI and PLL have
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* effect.
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*/
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void rcc_set_sysclk_source(enum rcc_osc osc)
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{
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switch (osc) {
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case PLL:
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RCC_CFGR |= RCC_CFGR_SW_PLL;
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break;
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case HSE:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSE;
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break;
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case HSI16:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSI16;
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break;
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case MSI:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_MSI;
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break;
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case HSI48:
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case LSE:
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case LSI:
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Multiplication Factor.
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*
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* @note This only has effect when the PLL is disabled.
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*
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* @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll_multiplier(uint32_t factor)
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{
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uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLMUL_MASK<<RCC_CFGR_PLLMUL_SHIFT);
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RCC_CFGR = reg | (factor << RCC_CFGR_PLLMUL_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Division Factor.
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*
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* @note This only has effect when the PLL is disabled.
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*
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* @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pdf
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*/
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void rcc_set_pll_divider(uint32_t factor)
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{
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uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLDIV_MASK<<RCC_CFGR_PLLDIV_SHIFT);
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RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB1 Prescale Factor.
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*
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* @note The APB1 clock frequency must not exceed 32MHz.
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*
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* @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre
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*/
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void rcc_set_ppre1(uint32_t ppre)
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{
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uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE1_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB2 Prescale Factor.
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*
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* @note The APB2 clock frequency must not exceed 32MHz.
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*
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* @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb2pre
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*/
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void rcc_set_ppre2(uint32_t ppre)
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{
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uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE2_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the AHB Prescale Factor.
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*
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* @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
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*/
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg = RCC_CFGR & ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT);
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}
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/**@}*/
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