stm32f4: add HSI clock configurations
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@ -795,6 +795,7 @@ struct rcc_clock_scale {
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uint32_t apb2_frequency;
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uint32_t apb2_frequency;
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};
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};
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extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END];
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extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END];
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extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END];
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extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END];
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extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END];
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extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END];
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extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END];
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@ -49,6 +49,94 @@ uint32_t rcc_ahb_frequency = 16000000;
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uint32_t rcc_apb1_frequency = 16000000;
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uint32_t rcc_apb1_frequency = 16000000;
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uint32_t rcc_apb2_frequency = 16000000;
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uint32_t rcc_apb2_frequency = 16000000;
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const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 16,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_1WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 84MHz */
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.pllm = 16,
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.plln = 336,
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.pllp = 4,
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.pllq = 7,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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{ /* 120MHz */
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.pllm = 16,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 16,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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{ /* 180MHz */
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.pllm = 16,
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.plln = 360,
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.pllp = 2,
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.pllq = 8,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 180000000,
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.apb1_frequency = 45000000,
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.apb2_frequency = 90000000,
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},
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};
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const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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{ /* 48MHz */
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{ /* 48MHz */
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.pllm = 8,
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.pllm = 8,
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