SDIO register definitions
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_SDIO_H
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#define LPC43XX_SDIO_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- SDIO registers ----------------------------------------------------- */
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/* Control Register */
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#define SDIO_CTRL MMIO32(SDIO_BASE + 0x000)
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/* Power Enable Register */
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#define SDIO_PWREN MMIO32(SDIO_BASE + 0x004)
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/* Clock Divider Register */
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#define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008)
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/* SD Clock Source Register */
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#define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C)
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/* Clock Enable Register */
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#define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010)
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/* Time-out Register */
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#define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014)
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/* Card Type Register */
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#define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018)
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/* Block Size Register */
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#define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C)
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/* Byte Count Register */
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#define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020)
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/* Interrupt Mask Register */
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#define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024)
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/* Command Argument Register */
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#define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028)
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/* Command Register */
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#define SDIO_CMD MMIO32(SDIO_BASE + 0x02C)
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/* Response Register 0 */
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#define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030)
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/* Response Register 1 */
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#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034)
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/* Response Register 2 */
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#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038)
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/* Response Register 3 */
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#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C)
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/* Masked Interrupt Status Register */
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#define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040)
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/* Raw Interrupt Status Register */
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#define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044)
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/* Status Register */
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#define SDIO_STATUS MMIO32(SDIO_BASE + 0x048)
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/* FIFO Threshold Watermark Register */
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#define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C)
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/* Card Detect Register */
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#define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050)
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/* Write Protect Register */
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#define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054)
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/* Transferred CIU Card Byte Count Register */
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#define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C)
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/* Transferred Host to BIU-FIFO Byte Count Register */
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#define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060)
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/* Debounce Count Register */
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#define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064)
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/* UHS-1 Register */
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#define SDIO_UHS_REG MMIO32(SDIO_BASE + 0x074)
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/* Hardware Reset */
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#define SDIO_RST_N MMIO32(SDIO_BASE + 0x078)
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/* Bus Mode Register */
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#define SDIO_BMOD MMIO32(SDIO_BASE + 0x080)
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/* Poll Demand Register */
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#define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084)
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/* Descriptor List Base Address Register */
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#define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088)
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/* Internal DMAC Status Register */
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#define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C)
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/* Internal DMAC Interrupt Enable Register */
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#define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090)
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/* Current Host Descriptor Address Register */
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#define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094)
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/* Current Buffer Descriptor Address Register */
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#define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098)
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/* Data FIFO read/write */
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#define SDIO_DATA MMIO32(SDIO_BASE + 0x100)
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#endif
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