From 1abb945dcd0102bf88398f5126672ef07b50412a Mon Sep 17 00:00:00 2001
From: Karl Palsson <karlp@tweak.net.au>
Date: Thu, 10 Dec 2020 22:26:05 +0000
Subject: [PATCH] stm32f7: flash: doxygenize existing comments.

Just putting it in a different place and it all gets included in the
output nicely.
---
 include/libopencm3/stm32/f7/flash.h | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/include/libopencm3/stm32/f7/flash.h b/include/libopencm3/stm32/f7/flash.h
index 79abbbff..031e0d77 100644
--- a/include/libopencm3/stm32/f7/flash.h
+++ b/include/libopencm3/stm32/f7/flash.h
@@ -9,6 +9,15 @@
  * @author @htmlonly &copy; @endhtmlonly 2010
  * Mark Butler <mbutler@physics.otago.ac.nz>
  *
+ * Differences between F7 and F4:
+ * 1. 	icache and dcache are now combined into a unified ART cache. The CPU has
+ * 	its own d/i-caches, but those are unrelated to this. They are on the
+ *	AXIM bus.
+ * 4. 	FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
+ *	erase sequence error).
+ * 6. 	There are now two watchdogs - IWDG (independent watchdog) and WWDG (
+ * 	window watchdog).
+ *
  */
 /*
  * This file is part of the libopencm3 project.
@@ -38,17 +47,6 @@
 #include <libopencm3/stm32/common/flash_common_f.h>
 #include <libopencm3/stm32/common/flash_common_f24.h>
 
-/*
- * Differences between F7 and F4:
- * 1. 	icache and dcache are now combined into a unified ART cache. The CPU has
- * 	its own d/i-caches, but those are unrelated to this. They are on the
- *	AXIM bus.
- * 4. 	FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
- *	erase sequence error).
- * 6. 	There are now two watchdogs - IWDG (independent watchdog) and WWDG (
- * 	window watchdog).
- */
-
 /**@{*/
 
 /* --- FLASH_ACR values ---------------------------------------------------- */