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nvic unification 

* created include/libopencm3/cm3/nvic.h from the respective stm32 and
  lpc43xx files. the chip specific definitions were left in place (they
  were already split out in sthe stm32 case).
* created lib/cm3/nvic.c from the respective stm32 and lpc43xx files. a
  hack from the lpc43xx was taken over (for manipulating the internal
  interrupts); for now it'll work.
* created a include/libopencm3/dispatch/ directory where the dispatching
  of files with common interfaces but different implenentations can
  happen; for now, an nvic.h there includes the respective irq name
  definitions. (future implementations might have some automation or
  preprocessor magic there; so far, it's manual dispatching based on
  defines.)
* for efm32, an nvic.h gets generated from an interrupt list, the
  rationale for code generation is, in this case, that this can't be
  done easily in c preprocessor, and it's really just a list of
  definitions and not code proper.
* examples now include <libopencm3/cm3/nvic.h> instead of
  <libopencm3/stm32/nvic.h>
This commit is contained in:
chrysn 2012-10-18 13:30:19 +02:00
parent 7c33025c31 94ce82396b
commit 172ce56e3c
38 changed files with 234 additions and 376 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
examples/stm32/f1/lisa-m-1/can/can.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h>
#include <libopencm3/stm32/can.h>

2
examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c
View File

@ -25,7 +25,7 @@
#include <libopencm3/stm32/f1/adc.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
volatile u16 temperature = 0;

2
examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c
View File

@ -25,7 +25,7 @@
#include <libopencm3/stm32/f1/adc.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
volatile u16 temperature = 0;
volatile u16 v_refint = 0;

2
examples/stm32/f1/lisa-m-2/usart_dma/usart_dma.c
View File

@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/f1/dma.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
void clock_setup(void)
{

2
examples/stm32/f1/lisa-m-2/usart_irq/usart_irq.c
View File

@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
void clock_setup(void)
{

2
examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c
View File

@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h>
#include <stdio.h>
#include <errno.h>

2
examples/stm32/f1/lisa-m-2/usart_printf/usart_printf.c
View File

@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <stdio.h>
#include <errno.h>

2
examples/stm32/f1/obldc/can/can.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h>
#include <libopencm3/stm32/can.h>

2
examples/stm32/f1/obldc/systick/systick.c
View File

@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h>
u32 temp32;

2
examples/stm32/f1/obldc/usart_irq/usart_irq.c
View File

@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
void clock_setup(void)
{

2
examples/stm32/f1/other/dogm128/main.c
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@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/spi.h>
#include "./dogm128.h"

2
examples/stm32/f1/other/rtc/rtc.c
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@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/rtc.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
void clock_setup(void)
{

2
examples/stm32/f1/other/systick/systick.c
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@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h>
u32 temp32;

2
examples/stm32/f1/other/timer_interrupt/timer.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
void gpio_setup(void)
{

2
examples/stm32/f1/stm32-h103/button/button.c
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@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/exti.h>
u16 exti_line_state;

2
examples/stm32/f1/stm32-h103/exti_both/exti_both.c
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@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/exti.h>
u16 exti_line_state;

2
examples/stm32/f1/stm32-h103/exti_rising_falling/exti_rising_falling.c
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@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/exti.h>
#define FALLING 0

2
examples/stm32/f1/stm32-h103/pwm_6step/pwm_6step.c
View File

@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/exti.h>
#define FALLING 0

2
examples/stm32/f1/stm32-h103/timer/timer.c
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@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/exti.h>
u16 frequency_sequence[18] = {

2
examples/stm32/f1/stm32-h103/usart_irq/usart_irq.c
View File

@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
void clock_setup(void)
{

2
examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c
View File

@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h>
#include <stdio.h>
#include <errno.h>

2
examples/stm32/f1/stm32-h103/usart_printf/usart_printf.c
View File

@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <stdio.h>
#include <errno.h>

2
examples/stm32/f1/stm32vl-discovery/rtc/rtc.c
View File

@ -23,7 +23,7 @@
#include <libopencm3/stm32/f1/rtc.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
void clock_setup(void)
{

2
examples/stm32/f2/jobygps/spi_test/spi_test.c
View File

@ -22,7 +22,7 @@
#include <errno.h>
#include <libopencm3/stm32/spi.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/f2/gpio.h>
#include <libopencm3/stm32/f2/rcc.h>

2
examples/stm32/f2/jobygps/usart_printf/usart_printf.c
View File

@ -22,7 +22,7 @@
#include <errno.h>
#include <libopencm3/stm32/f2/gpio.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/f2/rcc.h>
void clock_setup(void)

52
include/libopencm3/stm32/nvic.h → include/libopencm3/cm3/nvic.h
View File

@ -1,21 +1,9 @@
/** @defgroup STM32F_nvic_defines NVIC Defines
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@ -30,13 +18,27 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup CM3_nvic_defines NVIC Defines
@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
@ingroup CM3_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/**@{*/
#ifndef LIBOPENCM3_NVIC_H
#define LIBOPENCM3_NVIC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/memorymap.h>
/* --- NVIC Registers ------------------------------------------------------ */
@ -79,9 +81,9 @@ LGPL License Terms @ref lgpl_license
/* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M3 System Interrupts */
/** @defgroup nvic_sysint Cortex M3 System Interrupts
@ingroup STM32F_nvic_defines
/* Cortex M3 and M4 System Interrupts */
/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts
@ingroup CM3_nvic_defines
IRQ numbers -3 and -6 to -9 are reserved
@{*/
@ -98,21 +100,11 @@ IRQ numbers -3 and -6 to -9 are reserved
#define NVIC_SYSTICK_IRQ -1
/**@}*/
/* Note: User interrupts are family specific and are defined in a family
* specific header file in the corresponding subfolder.
*/
#if defined(STM32F1)
# include <libopencm3/stm32/f1/nvic_f1.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/nvic_f2.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/nvic_f4.h>
#else
# error "stm32 family not defined."
#endif
#include <libopencm3/dispatch/nvic.h>
/* --- NVIC functions ------------------------------------------------------ */
@ -131,5 +123,3 @@ void nvic_generate_software_interrupt(u16 irqn);
END_DECLS
#endif
/**@}*/

5
include/libopencm3/cm3/vector.h
View File

@ -38,8 +38,7 @@
#define LIBOPENCM3_VECTOR_H
#include <libopencm3/cm3/common.h>
// #include "irq.h" /* we'll nede some definitions */
#include <libopencm3/cm3/nvic.h>
/** Type of an interrupt function. Only used to avoid hard-to-read function
* pointers in the efm32_vector_table_t struct. */
@ -59,7 +58,7 @@ typedef struct {
vector_table_entry_t reserved_x0034;
vector_table_entry_t pend_sv;
vector_table_entry_t systick;
vector_table_entry_t irq[IRQ_COUNT];
vector_table_entry_t irq[NVIC_IRQ_COUNT];
} vector_table_t;
#endif

20
include/libopencm3/dispatch/nvic.h Normal file
View File

@ -0,0 +1,20 @@
#if defined(STM32F1)
# include <libopencm3/stm32/f1/nvic_f1.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/nvic_f2.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/nvic_f4.h>
#elif defined(TINYGECKO)
# include <libopencm3/efm32/tinygecko/nvic.h>
#elif defined(LPC43XX)
# include <libopencm3/lpc43xx/nvic.h>
#else
# warning"no chipset defined; user interrupts are disabled"
#define NVIC_IRQ_COUNT 0
#define IRQ_HANDLERS
#endif

2
include/libopencm3/efm32/tinygecko/Makefile Normal file
View File

@ -0,0 +1,2 @@
nvic.h: irq.yaml
./irq2nvic_h

130
include/libopencm3/efm32/tinygecko/irq.h
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@ -1,130 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
*
* Definitions of interrupt names on EFM32 Tiny Gecko systems
*
* The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
*/
#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
#define IRQ_DMA 0
#define IRQ_GPIO_EVEN 1
#define IRQ_TIMER0 2
#define IRQ_USART0_RX 3
#define IRQ_USART0_TX 4
#define IRQ_ACMP01 5
#define IRQ_ADC0 6
#define IRQ_DAC0 7
#define IRQ_I2C0 8
#define IRQ_GPIO_ODD 9
#define IRQ_TIMER1 10
#define IRQ_USART1_RX 11
#define IRQ_USART1_TX 12
#define IRQ_LESENSE 13
#define IRQ_LEUART0 14
#define IRQ_LETIMER0 15
#define IRQ_PCNT0 16
#define IRQ_RTC 17
#define IRQ_CMU 18
#define IRQ_VCMP 19
#define IRQ_LCD 20
#define IRQ_MSC 21
#define IRQ_AES 22
#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */
#define WEAK __attribute__ ((weak))
void WEAK dma_isr(void);
void WEAK gpio_even_isr(void);
void WEAK timer0_isr(void);
void WEAK usart0_rx_isr(void);
void WEAK usart0_tx_isr(void);
void WEAK acmp01_isr(void);
void WEAK adc0_isr(void);
void WEAK dac0_isr(void);
void WEAK i2c0_isr(void);
void WEAK gpio_odd_isr(void);
void WEAK timer1_isr(void);
void WEAK usart1_rx_isr(void);
void WEAK usart1_tx_isr(void);
void WEAK lesense_isr(void);
void WEAK leuart0_isr(void);
void WEAK letimer0_isr(void);
void WEAK pcnt0_isr(void);
void WEAK rtc_isr(void);
void WEAK cmu_isr(void);
void WEAK vcmp_isr(void);
void WEAK lcd_isr(void);
void WEAK msc_isr(void);
void WEAK aes_isr(void);
#pragma weak dma_isr = blocking_handler
#pragma weak gpio_even_isr = blocking_handler
#pragma weak timer0_isr = blocking_handler
#pragma weak usart0_rx_isr = blocking_handler
#pragma weak usart0_tx_isr = blocking_handler
#pragma weak acmp01_isr = blocking_handler
#pragma weak adc0_isr = blocking_handler
#pragma weak dac0_isr = blocking_handler
#pragma weak i2c0_isr = blocking_handler
#pragma weak gpio_odd_isr = blocking_handler
#pragma weak timer1_isr = blocking_handler
#pragma weak usart1_rx_isr = blocking_handler
#pragma weak usart1_tx_isr = blocking_handler
#pragma weak lesense_isr = blocking_handler
#pragma weak leuart0_isr = blocking_handler
#pragma weak letimer0_isr = blocking_handler
#pragma weak pcnt0_isr = blocking_handler
#pragma weak rtc_isr = blocking_handler
#pragma weak cmu_isr = blocking_handler
#pragma weak vcmp_isr = blocking_handler
#pragma weak lcd_isr = blocking_handler
#pragma weak msc_isr = blocking_handler
#pragma weak aes_isr = blocking_handler
#define IRQ_HANDLERS \
[IRQ_DMA] = dma_isr, \
[IRQ_GPIO_EVEN] = gpio_even_isr, \
[IRQ_TIMER0] = timer0_isr, \
[IRQ_USART0_RX] = usart0_rx_isr, \
[IRQ_USART0_TX] = usart0_tx_isr, \
[IRQ_ACMP01] = acmp01_isr, \
[IRQ_ADC0] = adc0_isr, \
[IRQ_DAC0] = dac0_isr, \
[IRQ_I2C0] = i2c0_isr, \
[IRQ_GPIO_ODD] = gpio_odd_isr, \
[IRQ_TIMER1] = timer1_isr, \
[IRQ_USART1_RX] = usart1_rx_isr, \
[IRQ_USART1_TX] = usart1_tx_isr, \
[IRQ_LESENSE] = lesense_isr, \
[IRQ_LEUART0] = leuart0_isr, \
[IRQ_LETIMER0] = letimer0_isr, \
[IRQ_PCNT0] = pcnt0_isr, \
[IRQ_RTC] = rtc_isr, \
[IRQ_CMU] = cmu_isr, \
[IRQ_VCMP] = vcmp_isr, \
[IRQ_LCD] = lcd_isr, \
[IRQ_MSC] = msc_isr, \
[IRQ_AES] = aes_isr,
#endif

28
include/libopencm3/efm32/tinygecko/irq.yaml Normal file
View File

@ -0,0 +1,28 @@
includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
partname_humanreadable: EFM32 Tiny Gecko series
partname_doxygen: EFM32TG
# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
irqs:
- dma
- gpio_even
- timer0
- usart0_rx
- usart0_tx
- acmp01
- adc0
- dac0
- i2c0
- gpio_odd
- timer1
- usart1_rx
- usart1_tx
- lesense
- leuart0
- letimer0
- pcnt0
- rtc
- cmu
- vcmp
- lcd
- msc
- aes

92
include/libopencm3/efm32/tinygecko/irq2nvic_h Executable file
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@ -0,0 +1,92 @@
#!/usr/bin/env python
# This file is part of the libopencm3 project.
#
# Copyright (C) 2012 chrysn <chrysn@fsfe.org>
#
# This library is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with this library. If not, see <http://www.gnu.org/licenses/>.
import sys
import yaml
template = '''\
/* This file is part of the libopencm3 project.
*
* It was generated by the irq2nvic_h script.
*/
#ifndef {includeguard}
#define {includeguard}
/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable}
@ingroup CM3_nvic_defines
@{{*/
{irqdefinitions}
#define NVIC_IRQ_COUNT {irqcount}
/**@}}*/
#define WEAK __attribute__ ((weak))
/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable}
@ingroup CM3_nvic_isrprototypes
@{{*/
{isrprototypes}
/**@}}*/
/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable}
@ingroup CM3_nvic_isrpragmas
@{{*/
{isrpragmas}
/**@}}*/
/* Initialization template for the interrupt vector table. This definition is
* used by the startup code generator (vector.c) to set the initial values for
* the interrupt handling routines to the chip family specific _isr weak
* symbols. */
#define IRQ_HANDLERS \\
{vectortableinitialization}
#endif /* {includeguard} */
'''
def convert(infile, outfile):
data = yaml.load(infile)
irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items())
irqnames = [v for (k,v) in irq2name]
data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name)
data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary?
data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames)
data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames)
data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames)
outfile.write(template.format(**data))
def main():
convert(open('irq.yaml'), open('nvic.h', 'w'))
if __name__ == "__main__":
main()

87
include/libopencm3/lpc43xx/nvic.h
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@ -1,70 +1,3 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_NVIC_H
#define LPC43XX_NVIC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/lpc43xx/memorymap.h>
/* --- NVIC Registers ------------------------------------------------------ */
/* ISER: Interrupt Set Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
/* ICER: Interrupt Clear Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
/* ISPR: Interrupt Set Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
/* ICPR: Interrupt Clear Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
/* IABR: Interrupt Active Bit Register */
/* Note: 8 32bit Registers */
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
/* IPR: Interrupt Priority Registers */
/* Note: 240 8bit Registers */
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
/* STIR: Software Trigger Interrupt Register */
#define NVIC_STIR MMIO32(STIR_BASE)
/* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M4 System Interrupts */
@ -129,23 +62,7 @@
#define NVIC_M4_C_CAN0_IRQ 51
#define NVIC_M4_QEI_IRQ 52
#define NVIC_IRQ_COUNT 53
/* LPC43xx M0 specific user interrupts */
//TODO
/* --- NVIC functions ------------------------------------------------------ */
BEGIN_DECLS
void nvic_enable_irq(u8 irqn);
void nvic_disable_irq(u8 irqn);
u8 nvic_get_pending_irq(u8 irqn);
void nvic_set_pending_irq(u8 irqn);
void nvic_clear_pending_irq(u8 irqn);
u8 nvic_get_active_irq(u8 irqn);
u8 nvic_get_irq_enabled(u8 irqn);
void nvic_set_priority(u8 irqn, u8 priority);
void nvic_generate_software_interrupt(u8 irqn);
END_DECLS
#endif

2
include/libopencm3/stm32/f1/nvic_f1.h
View File

@ -109,6 +109,8 @@ LGPL License Terms @ref lgpl_license
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
#define NVIC_IRQ_COUNT 68
/**@}*/
#endif

2
include/libopencm3/stm32/f2/nvic_f2.h
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@ -109,4 +109,6 @@
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#define NVIC_IRQ_COUNT 81
#endif

2
include/libopencm3/stm32/f4/nvic_f4.h
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@ -109,4 +109,6 @@
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#define NVIC_IRQ_COUNT 81
#endif

62
lib/stm32/nvic.c → lib/cm3/nvic.c
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@ -1,31 +1,9 @@
/** @defgroup STM32F_nvic_file NVIC
@ingroup STM32F_files
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Fergus Noble <fergusnoble@gmail.com>
@date 18 August 2012
The STM32F series provides up to 68 maskable user interrupts for the STM32F10x
series, and 87 for the STM32F2xx and STM32F4xx series.
The NVIC registers are defined by the ARM standards but the STM32F series have some
additional limitations
@see Cortex-M3 Devices Generic User Guide
@see STM32F10xxx Cortex-M3 programming manual
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@ -40,10 +18,32 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup CM3_nvic_file NVIC
@ingroup CM3_files
@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Fergus Noble <fergusnoble@gmail.com>
@date 18 August 2012
Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults,
systicks etc.) and varying numbers of implementation defined interrupts
(typically peripherial interrupts and DMA).
@see Cortex-M3 Devices Generic User Guide
@see STM32F10xxx Cortex-M3 programming manual
LGPL License Terms @ref lgpl_license
*/
/**@{*/
#include <libopencm3/stm32/nvic.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/cm3/scs.h>
/*-----------------------------------------------------------------------------*/
/** @brief NVIC Enable Interrupt
@ -153,7 +153,18 @@ Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping.
void nvic_set_priority(u8 irqn, u8 priority)
{
NVIC_IPR(irqn) = priority;
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
* negative interrupt numbers assigned to the system interrupts. better
* handling would mean signed integers. */
if(irqn>=NVIC_IRQ_COUNT)
{
/* Cortex-M system interrupts */
SCS_SHPR( (irqn&0xF)-4 ) = priority;
}else
{
/* Device specific interrupts */
NVIC_IPR(irqn) = priority;
}
}
/*-----------------------------------------------------------------------------*/
@ -171,4 +182,3 @@ void nvic_generate_software_interrupt(u16 irqn)
NVIC_STIR |= irqn;
}
/**@}*/

76
lib/lpc43xx/nvic.c
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@ -1,76 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/cm3/scs.h>
#include <libopencm3/lpc43xx/nvic.h>
void nvic_enable_irq(u8 irqn)
{
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
}
void nvic_disable_irq(u8 irqn)
{
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
}
u8 nvic_get_pending_irq(u8 irqn)
{
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
void nvic_set_pending_irq(u8 irqn)
{
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
}
void nvic_clear_pending_irq(u8 irqn)
{
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
}
u8 nvic_get_active_irq(u8 irqn)
{
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
u8 nvic_get_irq_enabled(u8 irqn)
{
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
void nvic_set_priority(u8 irqn, u8 priority)
{
if(irqn>NVIC_M4_QEI_IRQ)
{
/* Cortex-M system interrupts */
SCS_SHPR( (irqn&0xF)-4 ) = priority;
}else
{
/* Device specific interrupts */
NVIC_IPR(irqn) = priority;
}
}
void nvic_generate_software_interrupt(u8 irqn)
{
if (irqn <= 239)
NVIC_STIR |= irqn;
}