Changed rcc.c to use the new definitions.
This commit is contained in:
Thomas Otto
parent
dd5553f122
commit
141a291e8d
147
lib/rcc.c
147
lib/rcc.c
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@ -26,19 +26,19 @@ void rcc_osc_ready_int_clear(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= PLLRDYC;
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CR |= HSERDYC;
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CR |= HSIRDYC;
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= LSERDYC;
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= LSIRDYC;
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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@ -47,19 +47,19 @@ void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= PLLRDYIE;
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CR |= HSERDYIE;
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CR |= HSIRDYIE;
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= LSERDYIE;
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= LSIRDYIE;
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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@ -68,19 +68,19 @@ void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~PLLRDYIE;
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CR &= ~HSERDYIE;
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CR &= ~HSIRDYIE;
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~LSERDYIE;
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~LSIRDYIE;
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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@ -89,19 +89,19 @@ int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CR & PLLRDYF) != 0);
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CR & HSERDYF) != 0);
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CR & HSIRDYF) != 0);
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & LSERDYF) != 0);
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & LSIRDYF) != 0);
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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@ -111,31 +111,31 @@ int rcc_osc_ready_int_flag(osc_t osc)
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= CSSC;
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & CSSF) != 0);
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & PLLRDY) == 0);
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & HSERDY) == 0);
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case HSI:
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while ((RCC_CR & HSIRDY) == 0);
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case LSE:
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while ((RCC_BDCR & LSERDY) == 0);
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case LSI:
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while ((RCC_CSR & LSIRDY) == 0);
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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@ -144,19 +144,19 @@ void rcc_osc_on(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= PLLON;
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RCC_CR |= RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR |= HSEON;
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RCC_CR |= RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR |= HSION;
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RCC_CR |= RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR |= LSEON;
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR |= LSION;
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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@ -165,41 +165,41 @@ void rcc_osc_off(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~PLLON;
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR &= ~HSEON;
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR &= ~HSION;
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR &= ~LSEON;
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR &= ~LSION;
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= CSSON;
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~CSSON;
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR |= HSEBYP;
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR |= LSEBYP;
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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@ -213,10 +213,10 @@ void rcc_osc_bypass_disable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR &= ~HSEBYP;
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR &= ~LSEBYP;
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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@ -335,16 +335,16 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(ADCPRE_PLCK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(PPRE2_HCLK_NODIV); /* Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/*
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* Sysclk is running with 64MHz -> 2 waitstates.
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@ -358,17 +358,17 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
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* Set the PLL multiplication factor to 16.
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* 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz
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*/
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL16);
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16);
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/* Select HSI/2 as PLL source. */
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rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2);
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
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@ -378,21 +378,21 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/* Enable external high-speed oscillator 8MHz. */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(ADCPRE_PLCK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(PPRE2_HCLK_NODIV); /* Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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@ -406,23 +406,23 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
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* Set the PLL multiplication factor to 9.
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* 8MHz (external) * 9 (multiplier) = 72MHz
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*/
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9);
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/* Select HSE as PLL source. */
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rcc_set_pll_source(PLLSRC_HSE_CLK);
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
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/*
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* External frequency undivided before entering PLL
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* (only valid/needed for HSE).
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*/
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rcc_set_pllxtpre(PLLXTPRE_HSE_CLK);
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rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
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@ -432,44 +432,45 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/* enable External High Speed Oscillator 16MHz */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
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/* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */
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rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
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rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
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rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
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rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
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/* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
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flash_set_ws(FLASH_LATENCY_2WS);
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/* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9);
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/* Select HSI as PLL source. */
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rcc_set_pll_source(PLLSRC_HSE_CLK);
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
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/* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
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rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
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rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_backupdomain_reset(void)
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{
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/* Set the backup domain software reset. */
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RCC_BDCR |= BDRST;
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RCC_BDCR |= RCC_BDCR_BDRST;
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/* Clear the backup domain software reset. */
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RCC_BDCR &= ~BDRST;
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RCC_BDCR &= ~RCC_BDCR_BDRST;
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}
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